1 /* 2 * ibmstbx25.h 3 * 4 * Current maintainer 5 * Armin Kuster akuster@mvista.com 6 * July, 2002 7 * 8 * 9 * Copyright 2002 MontaVista Softare Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 * Version 1.0 July 10, 2002 - A. Kuster 32 * Initial version 33 * 34 * Version 1.1 July 24, 02 - Armin 35 * added Power Managment defines 36 * 37 * 38 */ 39 40 #ifdef __KERNEL__ 41 #ifndef __ASM_IBMSTBX25_H__ 42 #define __ASM_IBMSTBX25_H__ 43 44 #include <linux/config.h> 45 #include <platforms/ibm_ocp.h> 46 47 /* serial port defines */ 48 #define STBx25xx_IO_BASE ((uint)0xe0000000) 49 #define PPC4xx_ONB_IO_PADDR STBx25xx_IO_BASE 50 #define PPC4xx_ONB_IO_VADDR ((uint)0xe0000000) 51 #define PPC4xx_ONB_IO_SIZE ((uint)14*64*1024) 52 53 /* 54 * map STBxxxx internal i/o address (0x400x00xx) to an address 55 * which is below the 2GB limit... 56 * 57 * 4000 000x uart1 -> 0xe000 000x 58 * 4001 00xx uart2 59 * 4002 00xx smart card 60 * 4003 000x iic 61 * 4004 000x uart0 62 * 4005 0xxx timer 63 * 4006 00xx gpio 64 * 4007 00xx smart card 65 * 400b 000x iic 66 * 400c 000x scp 67 * 400d 000x modem 68 * 400e 000x uart2 69 */ 70 #define STBx25xx_MAP_IO_ADDR(a) (((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000)) 71 72 #define RS_TABLE_SIZE 3 73 74 #ifdef __BOOTER__ 75 #define UART1_IO_BASE 0x40000000 76 #define UART2_IO_BASE 0x40010000 77 #else 78 #define UART1_IO_BASE 0xe0000000 79 #define UART2_IO_BASE 0xe0010000 80 #endif 81 #define SC0_BASE 0x40020000 /* smart card #0 */ 82 #define IIC0_BASE 0x40030000 83 #ifdef __BOOTER__ 84 #define UART0_IO_BASE 0x40040000 85 #else 86 #define UART0_IO_BASE 0xe0040000 87 #endif 88 #define SCC0_BASE 0x40040000 /* Serial 0 controller IrdA */ 89 #define GPT0_BASE 0x40050000 /* General purpose timers */ 90 #define OPB0_BASE 0x40000000 91 #define GPIO0_BASE 0x40060000 92 #define SC0_base 0x40070000 /* smart card #1 */ 93 #define SCP0_base 0x400C0000 /* Serial Controller Port */ 94 #define SSP0_BASE 0x400D0000 /* Sync serial port */ 95 96 #define REDWOOD_IDE_CMD 0xf0100000 97 #define REDWOOD_IDE_CTRL 0xf1100000 98 99 #define RTCFPC_IRQ 0 100 #define XPORT_IRQ 1 101 #define AUD_IRQ 2 102 #define AID_IRQ 3 103 #define DMA0 4 104 #define DMA1_IRQ 5 105 #define DMA2_IRQ 6 106 #define DMA3_IRQ 7 107 #define SC0_IRQ 8 108 #define IIC0_IRQ 9 109 #define IIR0_IRQ 10 110 #define GPT0_IRQ 11 111 #define GPT1_IRQ 12 112 #define SCP0_IRQ 13 113 #define SSP0_IRQ 14 114 #define GPT2_IRQ 15 /* count down timer */ 115 #define SC1_IRQ 16 116 /* IRQ 17 - 19 external */ 117 #define UART0_INT 20 118 #define UART1_INT 21 119 #define UART2_INT 22 120 #define XPTDMA_IRQ 23 121 #define DCRIDE_IRQ 24 122 /* IRQ 25 - 30 external */ 123 #define IDE0_IRQ 26 124 125 #define IIC_NUMS 1 126 #define UART_NUMS 3 127 #define IIC_OWN 0x55 128 #define IIC_CLOCK 50 129 130 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i] 131 132 #define STD_UART_OP(num) \ 133 { 0, BASE_BAUD, 0, UART##num##_INT, \ 134 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ 135 iomem_base: (u8 *)UART##num##_IO_BASE, \ 136 io_type: SERIAL_IO_MEM}, 137 138 #if defined(CONFIG_UART0_TTYS0) 139 #define SERIAL_DEBUG_IO_BASE UART0_IO_BASE 140 #define SERIAL_PORT_DFNS \ 141 STD_UART_OP(0) \ 142 STD_UART_OP(1) \ 143 STD_UART_OP(2) 144 #endif 145 146 #if defined(CONFIG_UART0_TTYS1) 147 #define SERIAL_DEBUG_IO_BASE UART2_IO_BASE 148 #define SERIAL_PORT_DFNS \ 149 STD_UART_OP(1) \ 150 STD_UART_OP(0) \ 151 STD_UART_OP(2) 152 #endif 153 154 #if defined(CONFIG_UART0_TTYS2) 155 #define SERIAL_DEBUG_IO_BASE UART2_IO_BASE 156 #define SERIAL_PORT_DFNS \ 157 STD_UART_OP(2) \ 158 STD_UART_OP(0) \ 159 STD_UART_OP(1) 160 #endif 161 162 #define DCRN_BE_BASE 0x090 163 #define DCRN_DMA0_BASE 0x0C0 164 #define DCRN_DMA1_BASE 0x0C8 165 #define DCRN_DMA2_BASE 0x0D0 166 #define DCRN_DMA3_BASE 0x0D8 167 #define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ 168 #define DCRN_DMASR_BASE 0x0E0 169 #define DCRN_PLB0_BASE 0x054 170 #define DCRN_PLB1_BASE 0x064 171 #define DCRN_POB0_BASE 0x0B0 172 #define DCRN_SCCR_BASE 0x120 173 #define DCRN_UIC0_BASE 0x040 174 #define DCRN_BE_BASE 0x090 175 #define DCRN_DMA0_BASE 0x0C0 176 #define DCRN_DMA1_BASE 0x0C8 177 #define DCRN_DMA2_BASE 0x0D0 178 #define DCRN_DMA3_BASE 0x0D8 179 #define DCRN_CIC_BASE 0x030 180 #define DCRN_DMASR_BASE 0x0E0 181 #define DCRN_EBIMC_BASE 0x070 182 #define DCRN_DCRX_BASE 0x020 183 #define DCRN_CPMFR_BASE 0x102 184 #define DCRN_SCCR_BASE 0x120 185 #define DCRN_RTCFP_BASE 0x310 186 187 #define UIC0 DCRN_UIC0_BASE 188 189 #define IBM_CPM_IIC0 0x80000000 /* IIC 0 interface */ 190 #define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */ 191 #define IBM_CPM_AUD 0x08000000 /* Audio Decoder */ 192 #define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */ 193 #define IBM_CPM_IRR 0x02000000 /* Infrared reciever */ 194 #define IBM_CPM_DMA 0x01000000 /* DMA controller */ 195 #define IBM_CPM_UART2 0x00200000 /* Serial Control Port */ 196 #define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */ 197 #define IBM_CPM_UART0 0x00080000 /* Serial 0 / 16550 */ 198 #define IBM_PM_DCRIDE 0x00040000 /* DCR timeout & IDE line Mode clock */ 199 #define IBM_CPM_SC0 0x00020000 /* Smart Card 0 */ 200 #define IBM_CPM_VID 0x00010000 /* reserved */ 201 #define IBM_CPM_SC1 0x00008000 /* Smart Card 0 */ 202 #define IBM_CPM_XPT0 0x00002000 /* Transport - 54 Mhz */ 203 #define IBM_CPM_CBS 0x00001000 /* Cross Bar Switch */ 204 #define IBM_CPM_GPT 0x00000800 /* GPTPWM */ 205 #define IBM_CPM_GPIO0 0x00000400 /* General Purpose IO 0 */ 206 #define IBM_CPM_DENC 0x00000200 /* Digital video Encoder */ 207 #define IBM_CPM_C405T 0x00000100 /* CPU timers */ 208 #define IBM_CPM_XPT27 0x00000080 /* Transport - 27 Mhz */ 209 #define IBM_CPM_UIC 0x00000040 /* Universal Interrupt Controller */ 210 #define IBM_CPM_RTCFPC 0x00000020 /* Realtime clock and front panel */ 211 #define IBM_CPM_SSP 0x00000010 /* Modem Serial Interface (SSP) */ 212 #define IBM_CPM_VID2 0x00000002 /* Video Decoder clock domain 2 */ 213 #define DFLT_IBM4xx_PM ~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA \ 214 | IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T \ 215 | IBM_CPM_XPT27 | IBM_CPM_UIC) 216 217 #define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ 218 #define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */ 219 /* DCRN_BESR */ 220 #define BESR_DSES 0x80000000 /* Data-Side Error Status */ 221 #define BESR_DMES 0x40000000 /* DMA Error Status */ 222 #define BESR_RWS 0x20000000 /* Read/Write Status */ 223 #define BESR_ETMASK 0x1C000000 /* Error Type */ 224 #define ET_PROT 0 225 #define ET_PARITY 1 226 #define ET_NCFG 2 227 #define ET_BUSERR 4 228 #define ET_BUSTO 6 229 230 #define CHR1_CETE 0x00800000 /* CPU external timer enable */ 231 #define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ 232 233 #define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ 234 #define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ 235 #define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ 236 #define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ 237 #define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ 238 #define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ 239 #define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ 240 #define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ 241 #define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ 242 243 #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ 244 #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ 245 #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ 246 #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ 247 #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ 248 #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ 249 #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ 250 #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ 251 252 #define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ 253 #define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ 254 #define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ 255 #define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ 256 #define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ 257 #define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ 258 #define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ 259 #define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ 260 #define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10) /* BRC 0 */ 261 #define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11) /* BRC 1 */ 262 #define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12) /* BRC 2 */ 263 #define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13) /* BRC 3 */ 264 #define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14) /* BRC 4 */ 265 #define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15) /* BRC 5 */ 266 #define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16) /* BRC 6 */ 267 #define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17) /* BRC 7 */ 268 #define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20) /* Bus Error Address Register */ 269 #define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21) /* Bus Error Status Register */ 270 #define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A) /* Bus Interfac Unit Ctrl Reg */ 271 272 #define DCRN_RTC_FPC0_CNTL (DCRN_RTCFP_BASE + 0x00) /* RTC cntl */ 273 #define DCRN_RTC_FPC0_INT (DCRN_RTCFP_BASE + 0x01) /* RTC Interrupt */ 274 #define DCRN_RTC_FPC0_TIME (DCRN_RTCFP_BASE + 0x02) /* RTC time reg */ 275 #define DCRN_RTC_FPC0_ALRM (DCRN_RTCFP_BASE + 0x03) /* RTC Alarm reg */ 276 #define DCRN_RTC_FPC0_D1 (DCRN_RTCFP_BASE + 0x04) /* LED Data 1 */ 277 #define DCRN_RTC_FPC0_D2 (DCRN_RTCFP_BASE + 0x05) /* LED Data 2 */ 278 #define DCRN_RTC_FPC0_D3 (DCRN_RTCFP_BASE + 0x06) /* LED Data 3 */ 279 #define DCRN_RTC_FPC0_D4 (DCRN_RTCFP_BASE + 0x07) /* LED Data 4 */ 280 #define DCRN_RTC_FPC0_D5 (DCRN_RTCFP_BASE + 0x08) /* LED Data 5 */ 281 #define DCRN_RTC_FPC0_FCNTL (DCRN_RTCFP_BASE + 0x09) /* LED control */ 282 #define DCRN_RTC_FPC0_BRT (DCRN_RTCFP_BASE + 0x0A) /* Brightness cntl */ 283 284 #include <platforms/ibm405.h> 285 286 #endif /* __ASM_IBMSTBX25_H__ */ 287 #endif /* __KERNEL__ */ 288