1 /* 2 * ibm405gp.h 3 * 4 * This was derived from the ppc4xx.h and all 405GP specific 5 * definition and board inclusions were moved here. 6 * 7 * Original author: Armin Kuster akuster@mvista.com 8 * Oct, 2001 9 * 10 * 11 * Copyright 2001 MontaVista Softare Inc. 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms of the GNU General Public License as published by the 15 * Free Software Foundation; either version 2 of the License, or (at your 16 * option) any later version. 17 * 18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, write to the Free Software Foundation, Inc., 31 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 * 33 */ 34 35 #ifdef __KERNEL__ 36 #ifndef __ASM_IBM405GP_H__ 37 #define __ASM_IBM405GP_H__ 38 39 #include <linux/config.h> 40 41 /* ibm405.h is included at the bottom of this file */ 42 43 /* PCI 44 * PCI Bridge config reg definitions 45 * see 17-19 of manual 46 */ 47 48 #define PPC405_PCI_CONFIG_ADDR 0xeec00000 49 #define PPC405_PCI_CONFIG_DATA 0xeec00004 50 51 #define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */ 52 /* setbat */ 53 #define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */ 54 #define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */ 55 #define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */ 56 57 #define PPC405_PCI_LOWER_MEM 0x80000000 /* hose_a->mem_space.start */ 58 #define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */ 59 #define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */ 60 #define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */ 61 62 #define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE 63 64 #define PPC4xx_PCI_IO_PADDR ((uint)PPC405_PCI_PHY_IO_BASE) 65 #define PPC4xx_PCI_IO_VADDR PPC4xx_PCI_IO_PADDR 66 #define PPC4xx_PCI_IO_SIZE ((uint)64*1024) 67 #define PPC4xx_PCI_CFG_PADDR ((uint)PPC405_PCI_CONFIG_ADDR) 68 #define PPC4xx_PCI_CFG_VADDR PPC4xx_PCI_CFG_PADDR 69 #define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) 70 #define PPC4xx_PCI_LCFG_PADDR ((uint)0xef400000) 71 #define PPC4xx_PCI_LCFG_VADDR PPC4xx_PCI_LCFG_PADDR 72 #define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) 73 #define PPC4xx_ONB_IO_PADDR ((uint)0xef600000) 74 #define PPC4xx_ONB_IO_VADDR PPC4xx_ONB_IO_PADDR 75 #define PPC4xx_ONB_IO_SIZE ((uint)4*1024) 76 77 #define OPB_BASE_START 0x40000000 78 #define EBIU_BASE_START 0xF0100000 79 80 /* serial port defines */ 81 #define RS_TABLE_SIZE 2 82 83 #define UART0_INT 0 84 #define UART1_INT 1 85 86 #define PCIL0_BASE 0xEF400000 87 #define UART0_IO_BASE 0xEF600300 88 #define UART1_IO_BASE 0xEF600400 89 #define IIC0_BASE 0xEF600500 90 #define OPB0_BASE 0xEF600600 91 #define GPIO0_BASE 0xEF600700 92 #define EMAC0_BASE 0xEF600800 93 #define BL_MAC_WOL 9 /* WOL */ 94 #define BL_MAL_SERR 10 /* MAL SERR */ 95 #define BL_MAL_TXDE 13 /* MAL TXDE */ 96 #define BL_MAL_RXDE 14 /* MAL RXDE */ 97 #define BL_MAL_TXEOB 11 /* MAL TX EOB */ 98 #define BL_MAL_RXEOB 12 /* MAL RX EOB */ 99 #define BL_MAC_ETH0 15 /* MAC */ 100 101 #define EMAC_NUMS 1 102 #define IIC0_IRQ 2 103 #define IIC1_IRQ 0 104 105 #define IIC_OWN 0x55 106 #define IIC_CLOCK 50 107 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i] 108 109 #define STD_UART_OP(num) \ 110 { 0, BASE_BAUD, 0, UART##num##_INT, \ 111 ASYNC_BOOT_AUTOCONF, \ 112 iomem_base: (u8 *)UART##num##_IO_BASE, \ 113 io_type: SERIAL_IO_MEM}, 114 115 #if defined(CONFIG_UART0_TTYS0) 116 #define SERIAL_DEBUG_IO_BASE UART0_IO_BASE 117 #define SERIAL_PORT_DFNS \ 118 STD_UART_OP(0) \ 119 STD_UART_OP(1) 120 #endif 121 122 #if defined(CONFIG_UART0_TTYS1) 123 #define SERIAL_DEBUG_IO_BASE UART1_IO_BASE 124 #define SERIAL_PORT_DFNS \ 125 STD_UART_OP(1) \ 126 STD_UART_OP(0) 127 #endif 128 129 /* DCR defines */ 130 #define DCRN_CHCR_BASE 0x0B1 131 #define DCRN_CHPSR_BASE 0x0B4 132 #define DCRN_CPMSR_BASE 0x0B8 133 #define DCRN_CPMFR_BASE 0x0BA 134 135 #define CHR0_U0EC 0x00000080 /* Select external clock for UART0 */ 136 #define CHR0_U1EC 0x00000040 /* Select external clock for UART1 */ 137 #define CHR0_UDIV 0x0000003E /* UART internal clock divisor */ 138 #define CHR1_CETE 0x00800000 /* CPU external timer enable */ 139 140 #define DCRN_CHPSR_BASE 0x0B4 141 #define PSR_PLL_FWD_MASK 0xC0000000 142 #define PSR_PLL_FDBACK_MASK 0x30000000 143 #define PSR_PLL_TUNING_MASK 0x0E000000 144 #define PSR_PLB_CPU_MASK 0x01800000 145 #define PSR_OPB_PLB_MASK 0x00600000 146 #define PSR_PCI_PLB_MASK 0x00180000 147 #define PSR_EB_PLB_MASK 0x00060000 148 #define PSR_ROM_WIDTH_MASK 0x00018000 149 #define PSR_ROM_LOC 0x00004000 150 #define PSR_PCI_ASYNC_EN 0x00001000 151 #define PSR_PCI_ARBIT_EN 0x00000400 152 153 #define IBM_CPM_IIC0 0x80000000 /* IIC interface */ 154 #define IBM_CPM_PCI 0x40000000 /* PCI bridge */ 155 #define IBM_CPM_CPU 0x20000000 /* processor core */ 156 #define IBM_CPM_DMA 0x10000000 /* DMA controller */ 157 #define IBM_CPM_OPB 0x08000000 /* PLB to OPB bridge */ 158 #define IBM_CPM_DCP 0x04000000 /* CodePack */ 159 #define IBM_CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */ 160 #define IBM_CPM_SDRAM0 0x01000000 /* SDRAM memory controller */ 161 #define IBM_CPM_PLB 0x00800000 /* PLB bus arbiter */ 162 #define IBM_CPM_GPIO0 0x00400000 /* General Purpose IO (??) */ 163 #define IBM_CPM_UART0 0x00200000 /* serial port 0 */ 164 #define IBM_CPM_UART1 0x00100000 /* serial port 1 */ 165 #define IBM_CPM_UIC 0x00080000 /* Universal Interrupt Controller */ 166 #define IBM_CPM_TMRCLK 0x00040000 /* CPU timers */ 167 #define IBM_CPM_EMAC0 0x00020000 /* on-chip ethernet MM unit */ 168 #define DFLT_IBM4xx_PM ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \ 169 | IBM_CPM_OPB | IBM_CPM_EBC \ 170 | IBM_CPM_SDRAM0 | IBM_CPM_PLB \ 171 | IBM_CPM_UIC | IBM_CPM_TMRCLK) 172 173 #define DCRN_DMA0_BASE 0x100 174 #define DCRN_DMA1_BASE 0x108 175 #define DCRN_DMA2_BASE 0x110 176 #define DCRN_DMA3_BASE 0x118 177 #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 178 #define DCRN_DMASR_BASE 0x120 179 #define DCRN_EBC_BASE 0x012 180 #define DCRN_DCP0_BASE 0x014 181 #define DCRN_MAL_BASE 0x180 182 #define DCRN_OCM0_BASE 0x018 183 #define DCRN_PLB0_BASE 0x084 184 #define DCRN_PLLMR_BASE 0x0B0 185 #define DCRN_POB0_BASE 0x0A0 186 #define DCRN_SDRAM0_BASE 0x010 187 #define DCRN_UIC0_BASE 0x0C0 188 #define UIC0 DCRN_UIC0_BASE 189 190 #include <platforms/ibm405.h> 191 192 #endif /* __ASM_IBM405GP_H__ */ 193 #endif /* __KERNEL__ */ 194