1 /*
2 * arch/ppc/kernel/traps.c
3 *
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Modified by Cort Dougan (cort@cs.nmt.edu)
12 * and Paul Mackerras (paulus@cs.anu.edu.au)
13 */
14
15 /*
16 * This file handles the architecture-dependent parts of hardware exceptions
17 */
18
19 #include <linux/errno.h>
20 #include <linux/sched.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/slab.h>
27 #include <linux/user.h>
28 #include <linux/a.out.h>
29 #include <linux/interrupt.h>
30 #include <linux/config.h>
31 #include <linux/init.h>
32
33 #include <asm/pgtable.h>
34 #include <asm/uaccess.h>
35 #include <asm/system.h>
36 #include <asm/io.h>
37 #include <asm/processor.h>
38 #ifdef CONFIG_PMAC_BACKLIGHT
39 #include <asm/backlight.h>
40 #endif
41
42 extern int fix_alignment(struct pt_regs *);
43 extern void bad_page_fault(struct pt_regs *, unsigned long, int sig);
44
45 #ifdef CONFIG_XMON
46 extern void xmon(struct pt_regs *regs);
47 extern int xmon_bpt(struct pt_regs *regs);
48 extern int xmon_sstep(struct pt_regs *regs);
49 extern int xmon_iabr_match(struct pt_regs *regs);
50 extern int xmon_dabr_match(struct pt_regs *regs);
51 extern void (*xmon_fault_handler)(struct pt_regs *regs);
52 #endif
53
54 #ifdef CONFIG_XMON
55 void (*debugger)(struct pt_regs *regs) = xmon;
56 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
57 int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
58 int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
59 int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
60 void (*debugger_fault_handler)(struct pt_regs *regs);
61 #else
62 #ifdef CONFIG_KGDB
63 void (*debugger)(struct pt_regs *regs);
64 int (*debugger_bpt)(struct pt_regs *regs);
65 int (*debugger_sstep)(struct pt_regs *regs);
66 int (*debugger_iabr_match)(struct pt_regs *regs);
67 int (*debugger_dabr_match)(struct pt_regs *regs);
68 void (*debugger_fault_handler)(struct pt_regs *regs);
69 #else
70 #define debugger(regs) do { } while (0)
71 #define debugger_bpt(regs) 0
72 #define debugger_sstep(regs) 0
73 #define debugger_iabr_match(regs) 0
74 #define debugger_dabr_match(regs) 0
75 #define debugger_fault_handler ((void (*)(struct pt_regs *))0)
76 #endif
77 #endif
78
79 /*
80 * Trap & Exception support
81 */
82
83
84 spinlock_t die_lock = SPIN_LOCK_UNLOCKED;
85
die(const char * str,struct pt_regs * fp,long err)86 void die(const char * str, struct pt_regs * fp, long err)
87 {
88 console_verbose();
89 spin_lock_irq(&die_lock);
90 #ifdef CONFIG_PMAC_BACKLIGHT
91 if (_machine == _MACH_Pmac) {
92 set_backlight_enable(1);
93 set_backlight_level(BACKLIGHT_MAX);
94 }
95 #endif
96 printk("Oops: %s, sig: %ld\n", str, err);
97 show_regs(fp);
98 spin_unlock_irq(&die_lock);
99 /* do_exit() should take care of panic'ing from an interrupt
100 * context so we don't handle it here
101 */
102 do_exit(err);
103 }
104
105 void
_exception(int signr,struct pt_regs * regs,int code,unsigned long addr)106 _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
107 {
108 siginfo_t info;
109
110 if (!user_mode(regs)) {
111 debugger(regs);
112 die("Exception in kernel mode", regs, signr);
113 }
114 info.si_signo = signr;
115 info.si_errno = 0;
116 info.si_code = code;
117 info.si_addr = (void *) addr;
118 force_sig_info(signr, &info, current);
119 }
120
121 /*
122 * I/O accesses can cause machine checks on powermacs.
123 * Check if the NIP corresponds to the address of a sync
124 * instruction for which there is an entry in the exception
125 * table.
126 * Note that the 601 only takes a machine check on TEA
127 * (transfer error ack) signal assertion, and does not
128 * set any of the top 16 bits of SRR1.
129 * -- paulus.
130 */
check_io_access(struct pt_regs * regs)131 static inline int check_io_access(struct pt_regs *regs)
132 {
133 #ifdef CONFIG_ALL_PPC
134 unsigned long fixup;
135 unsigned long msr = regs->msr;
136
137 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
138 && (fixup = search_exception_table(regs->nip)) != 0) {
139 /*
140 * Check that it's a sync instruction, or somewhere
141 * in the twi; isync; nop sequence that inb/inw/inl uses.
142 * As the address is in the exception table
143 * we should be able to read the instr there.
144 * For the debug message, we look at the preceding
145 * load or store.
146 */
147 unsigned int *nip = (unsigned int *)regs->nip;
148 if (*nip == 0x60000000) /* nop */
149 nip -= 2;
150 else if (*nip == 0x4c00012c) /* isync */
151 --nip;
152 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
153 /* sync or twi */
154 unsigned int rb;
155
156 --nip;
157 rb = (*nip >> 11) & 0x1f;
158 printk(KERN_DEBUG "%s bad port %lx at %p\n",
159 (*nip & 0x100)? "OUT to": "IN from",
160 regs->gpr[rb] - _IO_BASE, nip);
161 regs->nip = fixup;
162 return 1;
163 }
164 }
165 #endif /* CONFIG_ALL_PPC */
166 return 0;
167 }
168
169 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
170 /* On 4xx, the reason for the machine check or program exception
171 is in the ESR. */
172 #define get_reason(regs) ((regs)->dsisr)
173 #define REASON_FP 0
174 #define REASON_ILLEGAL ESR_PIL
175 #define REASON_PRIVILEGED ESR_PPR
176 #define REASON_TRAP ESR_PTR
177
178 /* single-step stuff */
179 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
180 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
181
182 #else
183 /* On non-4xx, the reason for the machine check or program
184 exception is in the MSR. */
185 #define get_reason(regs) ((regs)->msr)
186 #define REASON_FP 0x100000
187 #define REASON_ILLEGAL 0x80000
188 #define REASON_PRIVILEGED 0x40000
189 #define REASON_TRAP 0x20000
190
191 #define single_stepping(regs) ((regs)->msr & MSR_SE)
192 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
193 #endif
194
195 void
MachineCheckException(struct pt_regs * regs)196 MachineCheckException(struct pt_regs *regs)
197 {
198 unsigned long reason = get_reason(regs);
199
200 if (user_mode(regs)) {
201 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
202 return;
203 }
204
205 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
206 /* the qspan pci read routines can cause machine checks -- Cort */
207 bad_page_fault(regs, regs->dar, SIGBUS);
208 return;
209 #endif
210 if (debugger_fault_handler) {
211 debugger_fault_handler(regs);
212 return;
213 }
214 if (check_io_access(regs))
215 return;
216
217 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
218 if (reason & ESR_IMCP) {
219 printk("Instruction");
220 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
221 } else
222 printk("Data");
223 printk(" machine check in kernel mode.\n");
224 #elif defined(CONFIG_440A)
225 printk("Machine check in kernel mode.\n");
226 if (reason & ESR_IMCP){
227 printk("Instruction Synchronous Machine Check exception\n");
228 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
229 }
230 else {
231 u32 mcsr = mfspr(SPRN_MCSR);
232 if (mcsr & MCSR_IB)
233 printk("Instruction Read PLB Error\n");
234 if (mcsr & MCSR_DRB)
235 printk("Data Read PLB Error\n");
236 if (mcsr & MCSR_DWB)
237 printk("Data Write PLB Error\n");
238 if (mcsr & MCSR_TLBP)
239 printk("TLB Parity Error\n");
240 if (mcsr & MCSR_ICP){
241 flush_instruction_cache();
242 printk("I-Cache Parity Error\n");
243 }
244 if (mcsr & MCSR_DCSP)
245 printk("D-Cache Search Parity Error\n");
246 if (mcsr & MCSR_DCFP)
247 printk("D-Cache Flush Parity Error\n");
248 if (mcsr & MCSR_IMPE)
249 printk("Machine Check exception is imprecise\n");
250
251 /* Clear MCSR */
252 mtspr(SPRN_MCSR, mcsr);
253 }
254 #else /* !CONFIG_4xx && !CONFIG_E500 */
255 printk("Machine check in kernel mode.\n");
256 printk("Caused by (from SRR1=%lx): ", reason);
257 switch (reason & 0x601F0000) {
258 case 0x80000:
259 printk("Machine check signal\n");
260 break;
261 case 0: /* for 601 */
262 case 0x40000:
263 case 0x140000: /* 7450 MSS error and TEA */
264 printk("Transfer error ack signal\n");
265 break;
266 case 0x20000:
267 printk("Data parity error signal\n");
268 break;
269 case 0x10000:
270 printk("Address parity error signal\n");
271 break;
272 case 0x20000000:
273 printk("L1 Data Cache error\n");
274 break;
275 case 0x40000000:
276 printk("L1 Instruction Cache error\n");
277 break;
278 case 0x00100000:
279 printk("L2 data cache parity error\n");
280 break;
281 default:
282 printk("Unknown values in msr\n");
283 }
284 #endif /* CONFIG_4xx */
285
286 debugger(regs);
287 die("machine check", regs, SIGBUS);
288 }
289
290 void
SMIException(struct pt_regs * regs)291 SMIException(struct pt_regs *regs)
292 {
293 debugger(regs);
294 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
295 show_regs(regs);
296 panic("System Management Interrupt");
297 #endif
298 }
299
300 void
UnknownException(struct pt_regs * regs)301 UnknownException(struct pt_regs *regs)
302 {
303 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx %s\n",
304 regs->nip, regs->msr, regs->trap, print_tainted());
305 _exception(SIGTRAP, regs, 0, 0);
306 }
307
308 void
InstructionBreakpoint(struct pt_regs * regs)309 InstructionBreakpoint(struct pt_regs *regs)
310 {
311 if (debugger_iabr_match(regs))
312 return;
313 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
314 }
315
316 void
RunModeException(struct pt_regs * regs)317 RunModeException(struct pt_regs *regs)
318 {
319 _exception(SIGTRAP, regs, 0, 0);
320 }
321
322 /* Illegal instruction emulation support. Originally written to
323 * provide the PVR to user applications using the mfspr rd, PVR.
324 * Return non-zero if we can't emulate, or EFAULT if the associated
325 * memory access caused an access fault. Return zero on success.
326 *
327 * There are a couple of ways to do this, either "decode" the instruction
328 * or directly match lots of bits. In this case, matching lots of
329 * bits is faster and easier.
330 *
331 */
332 #define INST_MFSPR_PVR 0x7c1f42a6
333 #define INST_MFSPR_PVR_MASK 0xfc1fffff
334
335 static int
emulate_instruction(struct pt_regs * regs)336 emulate_instruction(struct pt_regs *regs)
337 {
338 u32 instword;
339 u32 rd;
340 int retval;
341
342 retval = -EINVAL;
343
344 if (!user_mode(regs))
345 return retval;
346
347 if (get_user(instword, (u32 *)(regs->nip)))
348 return -EFAULT;
349
350 /* Emulate the mfspr rD, PVR.
351 */
352 if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
353 rd = (instword >> 21) & 0x1f;
354 regs->gpr[rd] = mfspr(PVR);
355 retval = 0;
356 regs->nip += 4;
357 }
358 return retval;
359 }
360
361 /*
362 * After we have successfully emulated an instruction, we have to
363 * check if the instruction was being single-stepped, and if so,
364 * pretend we got a single-step exception. This was pointed out
365 * by Kumar Gala. -- paulus
366 */
emulate_single_step(struct pt_regs * regs)367 static void emulate_single_step(struct pt_regs *regs)
368 {
369 if (single_stepping(regs)) {
370 clear_single_step(regs);
371 if (debugger_sstep(regs))
372 return;
373 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
374 }
375 }
376
377 void
ProgramCheckException(struct pt_regs * regs)378 ProgramCheckException(struct pt_regs *regs)
379 {
380 unsigned int reason = get_reason(regs);
381 extern int do_mathemu(struct pt_regs *regs);
382
383 #ifdef CONFIG_MATH_EMULATION
384 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
385 * but there seems to be a hardware bug on the 405GP (RevD)
386 * that means ESR is sometimes set incorrectly - either to
387 * ESR_DST (!?) or 0. In the process of chasing this with the
388 * hardware people - not sure if it can happen on any illegal
389 * instruction or only on FP instructions, whether there is a
390 * pattern to occurences etc. -dgibson 31/Mar/2003 */
391 if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
392 emulate_single_step(regs);
393 return;
394 }
395 #endif /* CONFIG_MATH_EMULATION */
396
397 if (reason & REASON_FP) {
398 /* IEEE FP exception */
399 int code = 0;
400 u32 fpscr;
401
402 if (regs->msr & MSR_FP)
403 giveup_fpu(current);
404 fpscr = current->thread.fpscr;
405 fpscr &= fpscr << 22; /* mask summary bits with enables */
406 if (fpscr & FPSCR_VX)
407 code = FPE_FLTINV;
408 else if (fpscr & FPSCR_OX)
409 code = FPE_FLTOVF;
410 else if (fpscr & FPSCR_UX)
411 code = FPE_FLTUND;
412 else if (fpscr & FPSCR_ZX)
413 code = FPE_FLTDIV;
414 else if (fpscr & FPSCR_XX)
415 code = FPE_FLTRES;
416 _exception(SIGFPE, regs, code, regs->nip);
417 return;
418 }
419
420 if (reason & REASON_TRAP) {
421 /* trap exception */
422 if (debugger_bpt(regs))
423 return;
424 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
425 return;
426 }
427
428 if (reason & REASON_PRIVILEGED) {
429 /* Try to emulate it if we should. */
430 if (emulate_instruction(regs) == 0) {
431 emulate_single_step(regs);
432 return;
433 }
434 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
435 return;
436 }
437
438 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
439 }
440
441 void
SingleStepException(struct pt_regs * regs)442 SingleStepException(struct pt_regs *regs)
443 {
444 regs->msr &= ~MSR_SE; /* Turn off 'trace' bit */
445 if (debugger_sstep(regs))
446 return;
447 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
448 }
449
450 void
AlignmentException(struct pt_regs * regs)451 AlignmentException(struct pt_regs *regs)
452 {
453 int fixed;
454
455 fixed = fix_alignment(regs);
456 if (fixed == 1) {
457 regs->nip += 4; /* skip over emulated instruction */
458 emulate_single_step(regs);
459 return;
460 }
461 if (fixed == -EFAULT) {
462 /* fixed == -EFAULT means the operand address was bad */
463 if (user_mode(regs))
464 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
465 else
466 bad_page_fault(regs, regs->dar, SIGSEGV);
467 return;
468 }
469 _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
470 }
471
472 void
StackOverflow(struct pt_regs * regs)473 StackOverflow(struct pt_regs *regs)
474 {
475 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
476 current, regs->gpr[1]);
477 debugger(regs);
478 show_regs(regs);
479 panic("kernel stack overflow");
480 }
481
482 void
trace_syscall(struct pt_regs * regs)483 trace_syscall(struct pt_regs *regs)
484 {
485 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
486 current, current->pid, regs->nip, regs->link, regs->gpr[0],
487 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
488 }
489
490 #ifdef CONFIG_8xx
491 void
SoftwareEmulation(struct pt_regs * regs)492 SoftwareEmulation(struct pt_regs *regs)
493 {
494 extern int do_mathemu(struct pt_regs *);
495 extern int Soft_emulate_8xx(struct pt_regs *);
496 int errcode;
497
498 if (!user_mode(regs)) {
499 debugger(regs);
500 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
501 }
502
503 #ifdef CONFIG_MATH_EMULATION
504 errcode = do_mathemu(regs);
505 #else
506 errcode = Soft_emulate_8xx(regs);
507 #endif
508 if (errcode) {
509 if (errcode > 0)
510 _exception(SIGFPE, regs, 0, 0);
511 else if (errcode == -EFAULT)
512 _exception(SIGSEGV, regs, 0, 0);
513 else
514 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
515 } else
516 emulate_single_step(regs);
517 }
518 #endif /* CONFIG_8xx */
519
520 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
521
DebugException(struct pt_regs * regs)522 void DebugException(struct pt_regs *regs)
523 {
524 unsigned long debug_status;
525
526 debug_status = mfspr(SPRN_DBSR);
527
528 regs->msr &= ~MSR_DE; /* Turn off 'debug' bit */
529 if (debug_status & DBSR_TIE) { /* trap instruction*/
530
531 mtspr(SPRN_DBSR, DBSR_TIE);
532
533 if (!user_mode(regs) && debugger_bpt(regs))
534 return;
535 _exception(SIGTRAP, regs, 0, 0);
536
537 } else if (debug_status & DBSR_IC) { /* instruction completion */
538
539 mtspr(SPRN_DBSR, DBSR_IC);
540 current->thread.dbcr0 &= ~DBCR0_IC;
541
542 if (!user_mode(regs) && debugger_sstep(regs))
543 return;
544 _exception(SIGTRAP, regs, 0, 0);
545 }
546 }
547 #endif /* CONFIG_4xx || CONFIG_BOOKE */
548
549 #if !defined(CONFIG_TAU_INT)
550 void
TAUException(struct pt_regs * regs)551 TAUException(struct pt_regs *regs)
552 {
553 printk("Thermal trap at PC: %lx, SR: %lx, vector=%lx %s\n",
554 regs->nip, regs->msr, regs->trap, print_tainted());
555 }
556 #endif /* CONFIG_INT_TAU */
557
558 #ifdef CONFIG_ALTIVEC
559 void
AltivecAssistException(struct pt_regs * regs)560 AltivecAssistException(struct pt_regs *regs)
561 {
562 if (regs->msr & MSR_VEC)
563 giveup_altivec(current);
564 /* XXX quick hack for now: set the non-Java bit in the VSCR */
565 current->thread.vscr.u[3] |= 0x10000;
566 }
567 #endif /* CONFIG_ALTIVEC */
568
trap_init(void)569 void __init trap_init(void)
570 {
571 }
572