1 /*
2 * arch/ppc/kernel/pplus_common.c
3 *
4 * Common Motorola PowerPlus Platform--really Falcon/Raven or HAWK.
5 *
6 * Author: Mark A. Greer
7 * mgreer@mvista.com
8 *
9 * Copyright 2001 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19
20 #include <asm/byteorder.h>
21 #include <asm/io.h>
22 #include <asm/irq.h>
23 #include <asm/pci.h>
24 #include <asm/pci-bridge.h>
25 #include <asm/open_pic.h>
26 #include <asm/pplus.h>
27
28 /*
29 * The Falcon/Raven and HAWK has 4 sets of registers:
30 * 1) PPC Registers which define the mappings from PPC bus to PCI bus,
31 * etc.
32 * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the
33 * MPIC base address.
34 * 3) MPIC registers.
35 * 4) System Memory Controller (SMC) registers.
36 */
37
38 /*
39 * Initialize the Motorola MCG Raven or HAWK host bridge.
40 *
41 * This means setting up the PPC bus to PCI memory and I/O space mappings,
42 * setting the PCI memory space address of the MPIC (mapped straight
43 * through), and ioremap'ing the mpic registers.
44 * This routine will set the PCI_CONFIG_ADDR or PCI_CONFIG_DATA
45 * addresses based on the PCI I/O address that is passed in.
46 * 'OpenPIC_Addr' will be set correctly by this routine.
47 */
48 int __init
pplus_init(struct pci_controller * hose,uint ppc_reg_base,ulong processor_pci_mem_start,ulong processor_pci_mem_end,ulong processor_pci_io_start,ulong processor_pci_io_end,ulong processor_mpic_base)49 pplus_init(struct pci_controller *hose,
50 uint ppc_reg_base,
51 ulong processor_pci_mem_start,
52 ulong processor_pci_mem_end,
53 ulong processor_pci_io_start,
54 ulong processor_pci_io_end,
55 ulong processor_mpic_base)
56 {
57 uint addr, offset;
58
59 /*
60 * Some sanity checks...
61 */
62 if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) ||
63 ((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) {
64 printk("pplus_init: %s\n",
65 "PPC to PCI mappings must start on 64 KB boundaries");
66 return -1;
67 }
68
69 if (((processor_pci_mem_end &0x0000ffff) != 0x0000ffff) ||
70 ((processor_pci_io_end &0x0000ffff) != 0x0000ffff)) {
71 printk("pplus_init: PPC to PCI mappings %s\n",
72 "must end just before a 64 KB boundaries");
73 return -1;
74 }
75
76 if (((processor_pci_mem_end - processor_pci_mem_start) !=
77 (hose->mem_space.end - hose->mem_space.start)) ||
78 ((processor_pci_io_end - processor_pci_io_start) !=
79 (hose->io_space.end - hose->io_space.start))) {
80 printk("pplus_init: %s\n",
81 "PPC and PCI memory or I/O space sizes don't match");
82 return -1;
83 }
84
85 if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
86 printk("pplus_init: %s\n",
87 "MPIC address must start on 256 MB boundary");
88 return -1;
89 }
90
91 if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
92 printk("pplus_init: %s\n",
93 "pci_dram_offset must be multiple of 64 KB");
94 return -1;
95 }
96
97 /*
98 * Disable previous PPC->PCI mappings.
99 */
100 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), 0x00000000);
101 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), 0x00000000);
102 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF2_OFF), 0x00000000);
103 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), 0x00000000);
104
105 /*
106 * Program the XSADD/XSOFF registers to set up the PCI Mem & I/O
107 * space mappings. These are the mappings going from the processor to
108 * the PCI bus.
109 *
110 * Note: Don't need to 'AND' start/end addresses with 0xffff0000
111 * because sanity check above ensures that they are properly
112 * aligned.
113 */
114
115 /* Set up PPC->PCI Mem mapping */
116 addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
117 offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2;
118 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD0_OFF), addr);
119 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), offset);
120
121 /* Set up PPC->MPIC mapping on the bridge */
122 addr = processor_mpic_base |
123 (((processor_mpic_base + PPLUS_MPIC_SIZE) >> 16) - 1);
124 offset = 0xc2; /* No write posting for this PCI Mem space */
125 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD1_OFF), addr);
126 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), offset);
127
128 /* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
129 addr = processor_pci_io_start | (processor_pci_io_end >> 16);
130 offset = (hose->io_space.start - processor_pci_io_start) | 0xc0;
131 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD3_OFF), addr);
132 out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), offset);
133
134 hose->io_base_virt = (void *)ioremap(processor_pci_io_start,
135 (processor_pci_io_end - processor_pci_io_start + 1));
136
137 /*
138 * Set up the indirect method of accessing PCI config space.
139 * The PCI config addr/data pair based on start addr of PCI I/O space.
140 */
141 setup_indirect_pci(hose,
142 processor_pci_io_start + PPLUS_PCI_CONFIG_ADDR_OFF,
143 processor_pci_io_start + PPLUS_PCI_CONFIG_DATA_OFF);
144
145 /*
146 * Disable previous PCI->PPC mappings.
147 */
148
149 /* XXXX Put in mappings from PCI bus to processor bus XXXX */
150
151 /*
152 * Disable MPIC response to PCI I/O space (BAR 0).
153 * Make MPIC respond to PCI Mem space at specified address.
154 * (BAR 1).
155 */
156 early_write_config_dword(hose,
157 0,
158 PCI_DEVFN(0,0),
159 PCI_BASE_ADDRESS_0,
160 0x00000000 | 0x1);
161
162 early_write_config_dword(hose,
163 0,
164 PCI_DEVFN(0,0),
165 PCI_BASE_ADDRESS_1,
166 processor_mpic_base | 0x0);
167
168 /* Map MPIC into vitual memory */
169 OpenPIC_Addr = ioremap(processor_mpic_base, PPLUS_MPIC_SIZE);
170
171 return 0;
172 }
173
174 /*
175 * Find the amount of RAM present.
176 * This assumes that PPCBug has initialized the memory controller (SMC)
177 * on the Falcon/HAWK correctly (i.e., it does no sanity checking).
178 * It also assumes that the memory base registers are set to configure the
179 * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc.
180 * however, RAM base registers can be skipped (e.g. A, B, C are set,
181 * D is skipped but E is set is okay).
182 */
183 #define MB (1024*1024)
184
185 static uint reg_offset_table[] __initdata = {
186 PPLUS_SMC_RAM_A_SIZE_REG_OFF,
187 PPLUS_SMC_RAM_B_SIZE_REG_OFF,
188 PPLUS_SMC_RAM_C_SIZE_REG_OFF,
189 PPLUS_SMC_RAM_D_SIZE_REG_OFF,
190 PPLUS_SMC_RAM_E_SIZE_REG_OFF,
191 PPLUS_SMC_RAM_F_SIZE_REG_OFF,
192 PPLUS_SMC_RAM_G_SIZE_REG_OFF,
193 PPLUS_SMC_RAM_H_SIZE_REG_OFF
194 };
195
196 static uint falcon_size_table[] __initdata = {
197 0 * MB, /* 0 ==> 0 MB */
198 16 * MB, /* 1 ==> 16 MB */
199 32 * MB, /* 2 ==> 32 MB */
200 64 * MB, /* 3 ==> 64 MB */
201 128 * MB, /* 4 ==> 128 MB */
202 256 * MB, /* 5 ==> 256 MB */
203 1024 * MB, /* 6 ==> 1024 MB (1 GB) */
204 };
205
206 static uint hawk_size_table[] __initdata = {
207 0 * MB, /* 0 ==> 0 MB */
208 32 * MB, /* 1 ==> 32 MB */
209 64 * MB, /* 2 ==> 64 MB */
210 64 * MB, /* 3 ==> 64 MB */
211 128 * MB, /* 4 ==> 128 MB */
212 128 * MB, /* 5 ==> 128 MB */
213 128 * MB, /* 6 ==> 128 MB */
214 256 * MB, /* 7 ==> 256 MB */
215 256 * MB, /* 8 ==> 256 MB */
216 512 * MB, /* 9 ==> 512 MB */
217 };
218
219 /*
220 * *** WARNING: You MUST have a BAT set up to map in the SMC regs ***
221 *
222 * Read the memory controller's registers to determine the amount of system
223 * memory. Assumes that the memory controller registers are already mapped
224 * into virtual memory--too early to use ioremap().
225 */
226 unsigned long __init
pplus_get_mem_size(uint smc_base)227 pplus_get_mem_size(uint smc_base)
228 {
229 unsigned long total;
230 int i, size_table_entries, reg_limit;
231 uint vend_dev_id;
232 uint *size_table;
233 u_char val;
234
235
236 vend_dev_id = in_be32((uint *)smc_base + PCI_VENDOR_ID);
237
238 if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
239 printk("pplus_get_mem_size: %s (0x%x)\n",
240 "Not a Motorola Memory Controller", vend_dev_id);
241 return 0;
242 }
243
244 vend_dev_id &= 0x0000ffff;
245
246 if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_FALCON) {
247 size_table = falcon_size_table;
248 size_table_entries = sizeof(falcon_size_table) /
249 sizeof(falcon_size_table[0]);
250
251 reg_limit = PPLUS_FALCON_SMC_REG_COUNT;
252 }
253 else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) {
254 size_table = hawk_size_table;
255 size_table_entries = sizeof(hawk_size_table) /
256 sizeof(hawk_size_table[0]);
257 reg_limit = PPLUS_HAWK_SMC_REG_COUNT;
258 }
259 else {
260 printk("pplus_get_mem_size: %s (0x%x)\n",
261 "Not a Falcon or HAWK", vend_dev_id);
262 return 0;
263 }
264
265 total = 0;
266
267 /* Check every reg because PPCBug may skip some */
268 for (i=0; i<reg_limit; i++) {
269 val = in_8((u_char *)(smc_base + reg_offset_table[i]));
270
271 if (val & 0x80) { /* If enabled */
272 val &= 0x0f;
273
274 /* Don't go past end of size_table */
275 if (val < size_table_entries) {
276 total += size_table[val];
277 }
278 else { /* Register not set correctly */
279 break;
280 }
281 }
282 }
283
284 return total;
285 }
286
287 int __init
pplus_mpic_init(unsigned int pci_mem_offset)288 pplus_mpic_init(unsigned int pci_mem_offset)
289 {
290 unsigned short devid;
291 unsigned int pci_membase;
292
293 /* Check the first PCI device to see if it is a Raven or Hawk. */
294 early_read_config_word(0, 0, 0, PCI_DEVICE_ID, &devid);
295
296 switch (devid) {
297 case PCI_DEVICE_ID_MOTOROLA_RAVEN:
298 case PCI_DEVICE_ID_MOTOROLA_HAWK:
299 break;
300 default:
301 OpenPIC_Addr = NULL;
302 return 1;
303 }
304
305 /* Read the memory base register. */
306 early_read_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
307
308 if (pci_membase == 0) {
309 OpenPIC_Addr = NULL;
310 return 1;
311 }
312
313 /* Map the MPIC registers to virtual memory. */
314 OpenPIC_Addr = ioremap(pci_membase + pci_mem_offset, 0x22000);
315
316 return 0;
317 }
318