1 /*
2 * FILE NAME
3 * arch/mips/vr41xx/common/bcu.c
4 *
5 * BRIEF MODULE DESCRIPTION
6 * Bus Control Unit routines for the NEC VR4100 series.
7 *
8 * Author: Yoichi Yuasa
9 * yyuasa@mvista.com or source@mvista.com
10 *
11 * Copyright 2002 MontaVista Software Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
26 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
27 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33 /*
34 * Changes:
35 * MontaVista Software Inc. <yyuasa@mvista.com> or <source@mvista.com>
36 * - New creation, NEC VR4122 and VR4131 are supported.
37 * - Added support for NEC VR4111 and VR4121.
38 *
39 * Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
40 * - Added support for NEC VR4133.
41 */
42 #include <linux/init.h>
43 #include <linux/types.h>
44
45 #include <asm/cpu.h>
46 #include <asm/io.h>
47
48 #define CLKSPEEDREG_TYPE1 KSEG1ADDR(0x0b000014)
49 #define CLKSPEEDREG_TYPE2 KSEG1ADDR(0x0f000014)
50 #define CLKSP(x) ((x) & 0x001f)
51 #define CLKSP_VR4133(x) ((x) & 0x0007)
52
53 #define DIV2B 0x8000
54 #define DIV3B 0x4000
55 #define DIV4B 0x2000
56
57 #define DIVT(x) (((x) & 0xf000) >> 12)
58 #define DIVVT(x) (((x) & 0x0f00) >> 8)
59
60 #define TDIVMODE(x) (2 << (((x) & 0x1000) >> 12))
61 #define VTDIVMODE(x) (((x) & 0x0700) >> 8)
62
63 static unsigned long vr41xx_vtclock;
64 static unsigned long vr41xx_tclock;
65
vr41xx_get_vtclock_frequency(void)66 unsigned long vr41xx_get_vtclock_frequency(void)
67 {
68 return vr41xx_vtclock;
69 }
70
vr41xx_get_tclock_frequency(void)71 unsigned long vr41xx_get_tclock_frequency(void)
72 {
73 return vr41xx_tclock;
74 }
75
read_clkspeed(void)76 static inline uint16_t read_clkspeed(void)
77 {
78 switch (current_cpu_data.cputype) {
79 case CPU_VR4111:
80 case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1);
81 case CPU_VR4122:
82 case CPU_VR4131:
83 case CPU_VR4133: return readw(CLKSPEEDREG_TYPE2);
84 default:
85 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
86 break;
87 }
88
89 return 0;
90 }
91
calculate_pclock(uint16_t clkspeed)92 static inline unsigned long calculate_pclock(uint16_t clkspeed)
93 {
94 unsigned long pclock = 0;
95
96 switch (current_cpu_data.cputype) {
97 case CPU_VR4111:
98 case CPU_VR4121:
99 pclock = 18432000 * 64;
100 pclock /= CLKSP(clkspeed);
101 break;
102 case CPU_VR4122:
103 pclock = 18432000 * 98;
104 pclock /= CLKSP(clkspeed);
105 break;
106 case CPU_VR4131:
107 pclock = 18432000 * 108;
108 pclock /= CLKSP(clkspeed);
109 break;
110 case CPU_VR4133:
111 switch (CLKSP_VR4133(clkspeed)) {
112 case 0:
113 pclock = 133000000;
114 break;
115 case 1:
116 pclock = 149000000;
117 break;
118 case 2:
119 pclock = 165900000;
120 break;
121 case 3:
122 pclock = 199100000;
123 break;
124 case 4:
125 pclock = 265900000;
126 break;
127 default:
128 printk(KERN_INFO "Unknown PClock speed for NEC VR4133\n");
129 break;
130 }
131 break;
132 default:
133 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
134 break;
135 }
136
137 printk(KERN_INFO "PClock: %ldHz\n", pclock);
138
139 return pclock;
140 }
141
calculate_vtclock(uint16_t clkspeed,unsigned long pclock)142 static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long pclock)
143 {
144 unsigned long vtclock = 0;
145
146 switch (current_cpu_data.cputype) {
147 case CPU_VR4111:
148 /* The NEC VR4111 doesn't have the VTClock. */
149 break;
150 case CPU_VR4121:
151 vtclock = pclock;
152 /* DIVVT == 9 Divide by 1.5 . VTClock = (PClock * 6) / 9 */
153 if (DIVVT(clkspeed) == 9)
154 vtclock = pclock * 6;
155 /* DIVVT == 10 Divide by 2.5 . VTClock = (PClock * 4) / 10 */
156 else if (DIVVT(clkspeed) == 10)
157 vtclock = pclock * 4;
158 vtclock /= DIVVT(clkspeed);
159 printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
160 break;
161 case CPU_VR4122:
162 if(VTDIVMODE(clkspeed) == 7)
163 vtclock = pclock / 1;
164 else if(VTDIVMODE(clkspeed) == 1)
165 vtclock = pclock / 2;
166 else
167 vtclock = pclock / VTDIVMODE(clkspeed);
168 printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
169 break;
170 case CPU_VR4131:
171 case CPU_VR4133:
172 vtclock = pclock / VTDIVMODE(clkspeed);
173 printk(KERN_INFO "VTClock: %ldHz\n", vtclock);
174 break;
175 default:
176 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
177 break;
178 }
179
180 return vtclock;
181 }
182
calculate_tclock(uint16_t clkspeed,unsigned long pclock,unsigned long vtclock)183 static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pclock,
184 unsigned long vtclock)
185 {
186 unsigned long tclock = 0;
187
188 switch (current_cpu_data.cputype) {
189 case CPU_VR4111:
190 if (!(clkspeed & DIV2B))
191 tclock = pclock / 2;
192 else if (!(clkspeed & DIV3B))
193 tclock = pclock / 3;
194 else if (!(clkspeed & DIV4B))
195 tclock = pclock / 4;
196 break;
197 case CPU_VR4121:
198 tclock = pclock / DIVT(clkspeed);
199 break;
200 case CPU_VR4122:
201 case CPU_VR4131:
202 case CPU_VR4133:
203 tclock = vtclock / TDIVMODE(clkspeed);
204 break;
205 default:
206 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
207 break;
208 }
209
210 printk(KERN_INFO "TClock: %ldHz\n", tclock);
211
212 return tclock;
213 }
214
vr41xx_bcu_init(void)215 void __init vr41xx_bcu_init(void)
216 {
217 unsigned long pclock;
218 uint16_t clkspeed;
219
220 clkspeed = read_clkspeed();
221
222 pclock = calculate_pclock(clkspeed);
223 vr41xx_vtclock = calculate_vtclock(clkspeed, pclock);
224 vr41xx_tclock = calculate_tclock(clkspeed, pclock, vr41xx_vtclock);
225 }
226