1 /*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Routines for generic manipulation of the interrupts found on the MIPS
20 * Malta board.
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
23 */
24 #include <linux/config.h>
25 #include <linux/init.h>
26 #include <linux/irq.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/random.h>
32
33 #include <asm/i8259.h>
34 #include <asm/io.h>
35 #include <asm/mips-boards/malta.h>
36 #include <asm/mips-boards/maltaint.h>
37 #include <asm/mips-boards/piix4.h>
38 #include <asm/gt64120/gt64120.h>
39 #include <asm/mips-boards/generic.h>
40 #include <asm/mips-boards/msc01_pci.h>
41
42 extern asmlinkage void mipsIRQ(void);
43 extern int mips_pcibios_iack(void);
44
45 #ifdef CONFIG_KGDB
46 extern void breakpoint(void);
47 extern void set_debug_traps(void);
48 extern int remote_debug;
49 #endif
50
51 static spinlock_t mips_irq_lock = SPIN_LOCK_UNLOCKED;
52
53 /*
54 * Algorithmics Bonito64 system controller register base.
55 */
56 static char * const _bonito = (char *)KSEG1ADDR(BONITO_REG_BASE);
57
mips_pcibios_iack(void)58 static inline int mips_pcibios_iack(void)
59 {
60 int irq;
61 u32 dummy;
62
63 /*
64 * Determine highest priority pending interrupt by performing
65 * a PCI Interrupt Acknowledge cycle.
66 */
67 switch(mips_revision_corid) {
68 case MIPS_REVISION_CORID_QED_RM5261:
69 case MIPS_REVISION_CORID_CORE_LV:
70 case MIPS_REVISION_CORID_CORE_FPGA:
71 case MIPS_REVISION_CORID_CORE_MSC:
72 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_MSC)
73 MSC_READ(MSC01_PCI_IACK, irq);
74 else
75 irq = GT_READ(GT_PCI0_IACK_OFS);
76 irq &= 0xff;
77 break;
78 case MIPS_REVISION_CORID_BONITO64:
79 case MIPS_REVISION_CORID_CORE_20K:
80 /* The following will generate a PCI IACK cycle on the
81 * Bonito controller. It's a little bit kludgy, but it
82 * was the easiest way to implement it in hardware at
83 * the given time.
84 */
85 BONITO_PCIMAP_CFG = 0x20000;
86
87 /* Flush Bonito register block */
88 dummy = BONITO_PCIMAP_CFG;
89 iob(); /* sync */
90
91 irq = *(volatile u32 *)(KSEG1ADDR(BONITO_PCICFG_BASE));
92 iob(); /* sync */
93 irq &= 0xff;
94 BONITO_PCIMAP_CFG = 0;
95 break;
96 default:
97 printk("Unknown Core card, don't know the system controller.\n");
98 return -1;
99 }
100 return irq;
101 }
102
get_int(int * irq)103 static inline int get_int(int *irq)
104 {
105 unsigned long flags;
106
107 spin_lock_irqsave(&mips_irq_lock, flags);
108
109 *irq = mips_pcibios_iack();
110
111 /*
112 * IRQ7 is used to detect spurious interrupts.
113 * The interrupt acknowledge cycle returns IRQ7, if no
114 * interrupts is requested.
115 * We can differentiate between this situation and a
116 * "Normal" IRQ7 by reading the ISR.
117 */
118 if (*irq == 7)
119 {
120 outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
121 PIIX4_ICTLR1_OCW3);
122 if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
123 spin_unlock_irqrestore(&mips_irq_lock, flags);
124 printk("We got a spurious interrupt from PIIX4.\n");
125 atomic_inc(&irq_err_count);
126 return -1; /* Spurious interrupt. */
127 }
128 }
129
130 spin_unlock_irqrestore(&mips_irq_lock, flags);
131
132 return 0;
133 }
134
malta_hw0_irqdispatch(struct pt_regs * regs)135 void malta_hw0_irqdispatch(struct pt_regs *regs)
136 {
137 int irq;
138
139 if (get_int(&irq))
140 return; /* interrupt has already been cleared */
141
142 do_IRQ(irq, regs);
143 }
144
corehi_irqdispatch(struct pt_regs * regs)145 void corehi_irqdispatch(struct pt_regs *regs)
146 {
147 unsigned int data,datahi;
148
149 /* Mask out corehi interrupt. */
150 clear_c0_status(IE_IRQ3);
151
152 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
153 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
154 , regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
155 switch(mips_revision_corid) {
156 case MIPS_REVISION_CORID_CORE_MSC:
157 break;
158 case MIPS_REVISION_CORID_QED_RM5261:
159 case MIPS_REVISION_CORID_CORE_LV:
160 case MIPS_REVISION_CORID_CORE_FPGA:
161 data = GT_READ(GT_INTRCAUSE_OFS);
162 printk("GT_INTRCAUSE = %08x\n", data);
163 data = GT_READ(0x70);
164 datahi = GT_READ(0x78);
165 printk("GT_CPU_ERR_ADDR = %02x%08x\n", datahi, data);
166 break;
167 case MIPS_REVISION_CORID_BONITO64:
168 case MIPS_REVISION_CORID_CORE_20K:
169 data = BONITO_INTISR;
170 printk("BONITO_INTISR = %08x\n", data);
171 data = BONITO_INTEN;
172 printk("BONITO_INTEN = %08x\n", data);
173 data = BONITO_INTPOL;
174 printk("BONITO_INTPOL = %08x\n", data);
175 data = BONITO_INTEDGE;
176 printk("BONITO_INTEDGE = %08x\n", data);
177 data = BONITO_INTSTEER;
178 printk("BONITO_INTSTEER = %08x\n", data);
179 data = BONITO_PCICMD;
180 printk("BONITO_PCICMD = %08x\n", data);
181 break;
182 }
183
184 /* We die here*/
185 die("CoreHi interrupt", regs);
186 }
187
init_IRQ(void)188 void __init init_IRQ(void)
189 {
190 set_except_vector(0, mipsIRQ);
191 init_generic_irq();
192 init_i8259_irqs();
193
194 #ifdef CONFIG_KGDB
195 if (remote_debug) {
196 set_debug_traps();
197 breakpoint();
198 }
199 #endif
200 }
201
202
203