1 /*
2 * setup.c: Baget/MIPS specific setup, including init of the feature struct.
3 *
4 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
5 */
6 #include <linux/init.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <asm/irq.h>
10 #include <asm/addrspace.h>
11 #include <asm/reboot.h>
12
13 #include <asm/baget/baget.h>
14
15 long int vac_memory_upper;
16
17 #define CACHEABLE_STR(val) ((val) ? "not cached" : "cached")
18 #define MIN(a,b) (((a)<(b)) ? (a):(b))
19
vac_show(void)20 static void __init vac_show(void)
21 {
22 int i;
23 unsigned short val, decode = vac_inw(VAC_DECODE_CTRL);
24 unsigned short a24_base = vac_inw(VAC_A24_BASE);
25 unsigned long a24_addr = ((unsigned long)
26 (a24_base & VAC_A24_MASK)) << 16;
27 char *decode_mode[] = { "eprom", "vsb", "shared", "dram" };
28 char *address_mode[] = { "", ", A16", ", A32/A24", ", A32/A24/A16" };
29 char *state[] = { "", " on write", " on read", " on read/write", };
30 char *region_mode[] = { "inactive", "shared", "vsb", "vme" };
31 char *asiz[] = { "user", "A32", "A16", "A24" };
32 unsigned short regs[] = { VAC_REG1, VAC_REG2, VAC_REG3 };
33 unsigned short bndr[] = { VAC_DRAM_MASK,VAC_BNDR2,VAC_BNDR3 };
34 unsigned short io_sels[] = { VAC_IOSEL0_CTRL,
35 VAC_IOSEL1_CTRL,
36 VAC_IOSEL2_CTRL,
37 VAC_IOSEL3_CTRL,
38 VAC_IOSEL4_CTRL,
39 VAC_IOSEL5_CTRL };
40
41 printk("[DSACKi %s, DRAMCS%s qualified, boundary%s qualified%s]\n",
42 (decode & VAC_DECODE_DSACKI) ? "on" : "off",
43 (decode & VAC_DECODE_QFY_DRAMCS) ? "" : " not",
44 (decode & VAC_DECODE_QFY_BNDR) ? "" : " not",
45 (decode & VAC_DECODE_FPUCS) ? ", fpu" : "");
46
47 printk("slave0 ");
48 if (decode & VAC_DECODE_RDR_SLSEL0)
49 printk("at %08lx (%d MB)\t[dram %s]\n",
50 ((unsigned long)vac_inw(VAC_SLSEL0_BASE))<<16,
51 ((0xffff ^ vac_inw(VAC_SLSEL0_MASK)) + 1) >> 4,
52 (decode & VAC_DECODE_QFY_SLSEL0) ? "qualified" : "");
53 else
54 printk("off\n");
55
56 printk("slave1 ");
57 if (decode & VAC_DECODE_RDR_SLSEL1)
58 printk("at %08lx (%d MB)\t[%s%s, %s]\n",
59 ((unsigned long)vac_inw(VAC_SLSEL1_BASE))<<16,
60 ((0xffff ^ vac_inw(VAC_SLSEL1_MASK)) + 1) >> 4,
61 decode_mode[VAC_DECODE_MODE_VAL(decode)],
62 address_mode[VAC_DECODE_CMP_SLSEL1_VAL(decode)],
63 (decode & VAC_DECODE_QFY_SLSEL1) ? "qualified" : "");
64 else
65 printk("off\n");
66
67 printk("icf global at %04x, module at %04x [%s]\n",
68 ((unsigned int)
69 VAC_ICFSEL_GLOBAL_VAL(vac_inw(VAC_ICFSEL_BASE)))<<4,
70 ((unsigned int)
71 VAC_ICFSEL_MODULE_VAL(vac_inw(VAC_ICFSEL_BASE)))<<4,
72 (decode & VAC_DECODE_QFY_ICFSEL) ? "qualified" : "");
73
74
75 printk("region0 at 00000000 (%dMB)\t[dram, %s, delay %d cpuclk"
76 ", cached]\n",
77 (vac_inw(VAC_DRAM_MASK)+1)>>4,
78 (decode & VAC_DECODE_DSACK) ? "D32" : "3state",
79 VAC_DECODE_CPUCLK_VAL(decode));
80
81 for (i = 0; i < sizeof(regs)/sizeof(regs[0]); i++) {
82 unsigned long from =
83 ((unsigned long)vac_inw(bndr[i]))<<16;
84 unsigned long to =
85 ((unsigned long)
86 ((i+1 == sizeof(bndr)/sizeof(bndr[0])) ?
87 0xff00 : vac_inw(bndr[i+1])))<<16;
88
89
90 val = vac_inw(regs[i]);
91 printk("region%d at %08lx (%dMB)\t[%s %s/%s, %s]\n",
92 i+1,
93 from,
94 (unsigned int)((to - from) >> 20),
95 region_mode[VAC_REG_MODE(val)],
96 asiz[VAC_REG_ASIZ_VAL(val)],
97 ((val & VAC_REG_WORD) ? "D16" : "D32"),
98 CACHEABLE_STR(val&VAC_A24_A24_CACHINH));
99
100 if (a24_addr >= from && a24_addr < to)
101 printk("\ta24 at %08lx (%dMB)\t[vme, A24/%s, %s]\n",
102 a24_addr,
103 MIN((unsigned int)(a24_addr - from)>>20, 32),
104 (a24_base & VAC_A24_DATAPATH) ? "user" :
105 ((a24_base & VAC_A24_D32_ENABLE) ?
106 "D32" : "D16"),
107 CACHEABLE_STR(a24_base & VAC_A24_A24_CACHINH));
108 }
109
110 printk("region4 at ff000000 (15MB)\t[eprom]\n");
111 val = vac_inw(VAC_EPROMCS_CTRL);
112 printk("\t[ack %d cpuclk%s, %s%srecovery %d cpuclk, "
113 "read %d%s, write %d%s, assert %d%s]\n",
114 VAC_CTRL_DELAY_DSACKI_VAL(val),
115 state[val & (VAC_CTRL_IORD|VAC_CTRL_IOWR)],
116 (val & VAC_CTRL_DSACK0) ? "dsack0*, " : "",
117 (val & VAC_CTRL_DSACK1) ? "dsack1*, " : "",
118 VAC_CTRL_RECOVERY_IOSELI_VAL(val),
119 VAC_CTRL_DELAY_IORD_VAL(val)/2,
120 (VAC_CTRL_DELAY_IORD_VAL(val)&1) ? ".5" : "",
121 VAC_CTRL_DELAY_IOWR_VAL(val)/2,
122 (VAC_CTRL_DELAY_IOWR_VAL(val)&1) ? ".5" : "",
123 VAC_CTRL_DELAY_IOSELI_VAL(val)/2,
124 (VAC_CTRL_DELAY_IOSELI_VAL(val)&1) ? ".5" : "");
125
126 printk("region5 at fff00000 (896KB)\t[local io, %s]\n",
127 CACHEABLE_STR(vac_inw(VAC_A24_BASE) & VAC_A24_IO_CACHINH));
128
129 for (i = 0; i < sizeof(io_sels)/sizeof(io_sels[0]); i++) {
130 val = vac_inw(io_sels[i]);
131 printk("\tio%d[ack %d cpuclk%s, %s%srecovery %d cpuclk, "
132 "\n\t read %d%s cpuclk, write %d%s cpuclk, "
133 "assert %d%s%s cpuclk]\n",
134 i,
135 VAC_CTRL_DELAY_DSACKI_VAL(val),
136 state[val & (VAC_CTRL_IORD|VAC_CTRL_IOWR)],
137 (val & VAC_CTRL_DSACK0) ? "dsack0*, " : "",
138 (val & VAC_CTRL_DSACK1) ? "dsack1*, " : "",
139 VAC_CTRL_RECOVERY_IOSELI_VAL(val),
140 VAC_CTRL_DELAY_IORD_VAL(val)/2,
141 (VAC_CTRL_DELAY_IORD_VAL(val)&1) ? ".5" : "",
142 VAC_CTRL_DELAY_IOWR_VAL(val)/2,
143 (VAC_CTRL_DELAY_IOWR_VAL(val)&1) ? ".5" : "",
144 VAC_CTRL_DELAY_IOSELI_VAL(val)/2,
145 (VAC_CTRL_DELAY_IOSELI_VAL(val)&1) ? ".5" : "",
146 (vac_inw(VAC_DEV_LOC) & VAC_DEV_LOC_IOSEL(i)) ?
147 ", id" : "");
148 }
149
150 printk("region6 at fffe0000 (128KB)\t[vme, A16/%s, "
151 "not cached]\n",
152 (a24_base & VAC_A24_A16D32_ENABLE) ?
153 ((a24_base & VAC_A24_A16D32) ? "D32" : "D16") : "user");
154
155 val = vac_inw(VAC_SHRCS_CTRL);
156 printk("shared[ack %d cpuclk%s, %s%srecovery %d cpuclk, "
157 "read %d%s, write %d%s, assert %d%s]\n",
158 VAC_CTRL_DELAY_DSACKI_VAL(val),
159 state[val & (VAC_CTRL_IORD|VAC_CTRL_IOWR)],
160 (val & VAC_CTRL_DSACK0) ? "dsack0*, " : "",
161 (val & VAC_CTRL_DSACK1) ? "dsack1*, " : "",
162 VAC_CTRL_RECOVERY_IOSELI_VAL(val),
163 VAC_CTRL_DELAY_IORD_VAL(val)/2,
164 (VAC_CTRL_DELAY_IORD_VAL(val)&1) ? ".5" : "",
165 VAC_CTRL_DELAY_IOWR_VAL(val)/2,
166 (VAC_CTRL_DELAY_IOWR_VAL(val)&1) ? ".5" : "",
167 VAC_CTRL_DELAY_IOSELI_VAL(val)/2,
168 (VAC_CTRL_DELAY_IOSELI_VAL(val)&1) ? ".5" : "");
169 }
170
vac_init(void)171 static void __init vac_init(void)
172 {
173 unsigned short mem_limit = (vac_memory_upper >> 16);
174
175 switch(vac_inw(VAC_ID)) {
176 case 0x1AC0:
177 printk("VAC068-F5: ");
178 break;
179 case 0x1AC1:
180 printk("VAC068A: ");
181 break;
182 default:
183 panic("Unknown VAC revision number");
184 }
185
186 vac_outw(mem_limit-1, VAC_DRAM_MASK);
187 vac_outw(mem_limit, VAC_BNDR2);
188 vac_outw(mem_limit, VAC_BNDR3);
189 vac_outw(((BAGET_A24M_BASE>>16)&~VAC_A24_D32_ENABLE)|VAC_A24_DATAPATH,
190 VAC_A24_BASE);
191 vac_outw(VAC_REG_INACTIVE|VAC_REG_ASIZ0,VAC_REG1);
192 vac_outw(VAC_REG_INACTIVE|VAC_REG_ASIZ0,VAC_REG2);
193 vac_outw(VAC_REG_MWB|VAC_REG_ASIZ1,VAC_REG3);
194 vac_outw(BAGET_A24S_BASE>>16,VAC_SLSEL0_BASE);
195 vac_outw(BAGET_A24S_MASK>>16,VAC_SLSEL0_MASK);
196 vac_outw(BAGET_A24S_BASE>>16,VAC_SLSEL1_BASE);
197 vac_outw(BAGET_A24S_MASK>>16,VAC_SLSEL1_MASK);
198 vac_outw(BAGET_GSW_BASE|BAGET_MSW_BASE(0),VAC_ICFSEL_BASE);
199 vac_outw(VAC_DECODE_FPUCS|
200 VAC_DECODE_CPUCLK(3)|
201 VAC_DECODE_RDR_SLSEL0|VAC_DECODE_RDR_SLSEL1|
202 VAC_DECODE_DSACK|
203 VAC_DECODE_QFY_BNDR|
204 VAC_DECODE_QFY_ICFSEL|
205 VAC_DECODE_QFY_SLSEL1|VAC_DECODE_QFY_SLSEL0|
206 VAC_DECODE_CMP_SLSEL1_HI|
207 VAC_DECODE_DRAMCS|
208 VAC_DECODE_QFY_DRAMCS|
209 VAC_DECODE_DSACKI,VAC_DECODE_CTRL);
210 vac_outw(VAC_PIO_FUNC_UART_A_TX|VAC_PIO_FUNC_UART_A_RX|
211 VAC_PIO_FUNC_UART_B_TX|VAC_PIO_FUNC_UART_B_RX|
212 VAC_PIO_FUNC_IOWR|
213 VAC_PIO_FUNC_IOSEL3|
214 VAC_PIO_FUNC_IRQ7|VAC_PIO_FUNC_IRQ10|VAC_PIO_FUNC_IRQ11|
215 VAC_PIO_FUNC_IOSEL2|
216 VAC_PIO_FUNC_FCIACK,VAC_PIO_FUNC);
217 vac_outw(VAC_PIO_DIR_FCIACK |
218 VAC_PIO_DIR_OUT(0) |
219 VAC_PIO_DIR_OUT(1) |
220 VAC_PIO_DIR_OUT(2) |
221 VAC_PIO_DIR_OUT(3) |
222 VAC_PIO_DIR_IN(4) |
223 VAC_PIO_DIR_OUT(5) |
224 VAC_PIO_DIR_OUT(6) |
225 VAC_PIO_DIR_OUT(7) |
226 VAC_PIO_DIR_OUT(8) |
227 VAC_PIO_DIR_IN(9) |
228 VAC_PIO_DIR_OUT(10)|
229 VAC_PIO_DIR_OUT(11)|
230 VAC_PIO_DIR_OUT(12)|
231 VAC_PIO_DIR_OUT(13),VAC_PIO_DIRECTION);
232 vac_outw(VAC_DEV_LOC_IOSEL(2),VAC_DEV_LOC);
233 vac_outw(VAC_CTRL_IOWR|
234 VAC_CTRL_DELAY_IOWR(3)|
235 VAC_CTRL_DELAY_IORD(3)|
236 VAC_CTRL_RECOVERY_IOSELI(1)|
237 VAC_CTRL_DELAY_DSACKI(8),VAC_SHRCS_CTRL);
238 vac_outw(VAC_CTRL_IOWR|
239 VAC_CTRL_DELAY_IOWR(3)|
240 VAC_CTRL_DELAY_IORD(3)|
241 VAC_CTRL_RECOVERY_IOSELI(1)|
242 VAC_CTRL_DSACK0|VAC_CTRL_DSACK1|
243 VAC_CTRL_DELAY_DSACKI(8),VAC_EPROMCS_CTRL);
244 vac_outw(VAC_CTRL_IOWR|
245 VAC_CTRL_DELAY_IOWR(3)|
246 VAC_CTRL_DELAY_IORD(3)|
247 VAC_CTRL_RECOVERY_IOSELI(2)|
248 VAC_CTRL_DSACK0|VAC_CTRL_DSACK1|
249 VAC_CTRL_DELAY_DSACKI(8),VAC_IOSEL0_CTRL);
250 vac_outw(VAC_CTRL_IOWR|
251 VAC_CTRL_DELAY_IOWR(3)|
252 VAC_CTRL_DELAY_IORD(3)|
253 VAC_CTRL_RECOVERY_IOSELI(2)|
254 VAC_CTRL_DSACK0|VAC_CTRL_DSACK1|
255 VAC_CTRL_DELAY_DSACKI(8),VAC_IOSEL1_CTRL);
256 vac_outw(VAC_CTRL_IOWR|
257 VAC_CTRL_DELAY_IOWR(3)|
258 VAC_CTRL_DELAY_IORD(3)|
259 VAC_CTRL_RECOVERY_IOSELI(2)|
260 VAC_CTRL_DSACK0|VAC_CTRL_DSACK1|
261 VAC_CTRL_DELAY_DSACKI(8),VAC_IOSEL2_CTRL);
262 vac_outw(VAC_CTRL_IOWR|
263 VAC_CTRL_DELAY_IOWR(3)|
264 VAC_CTRL_DELAY_IORD(3)|
265 VAC_CTRL_RECOVERY_IOSELI(2)|
266 VAC_CTRL_DSACK0|VAC_CTRL_DSACK1|
267 VAC_CTRL_DELAY_DSACKI(8),VAC_IOSEL3_CTRL);
268 vac_outw(VAC_CTRL_IOWR|
269 VAC_CTRL_DELAY_IOWR(3)|
270 VAC_CTRL_DELAY_IORD(3)|
271 VAC_CTRL_RECOVERY_IOSELI(2)|
272 VAC_CTRL_DELAY_DSACKI(8),VAC_IOSEL4_CTRL);
273 vac_outw(VAC_CTRL_IOWR|
274 VAC_CTRL_DELAY_IOWR(3)|
275 VAC_CTRL_DELAY_IORD(3)|
276 VAC_CTRL_RECOVERY_IOSELI(2)|
277 VAC_CTRL_DELAY_DSACKI(8),VAC_IOSEL5_CTRL);
278
279 vac_show();
280 }
281
vac_start(void)282 static void __init vac_start(void)
283 {
284 vac_outw(0, VAC_ID);
285 vac_outw(VAC_INT_CTRL_TIMER_DISABLE|
286 VAC_INT_CTRL_UART_B_DISABLE|
287 VAC_INT_CTRL_UART_A_DISABLE|
288 VAC_INT_CTRL_MBOX_DISABLE|
289 VAC_INT_CTRL_PIO4_DISABLE|
290 VAC_INT_CTRL_PIO7_DISABLE|
291 VAC_INT_CTRL_PIO8_DISABLE|
292 VAC_INT_CTRL_PIO9_DISABLE,VAC_INT_CTRL);
293 vac_outw(VAC_INT_CTRL_TIMER_PIO10|
294 VAC_INT_CTRL_UART_B_PIO7|
295 VAC_INT_CTRL_UART_A_PIO7,VAC_INT_CTRL);
296 /*
297 * Set quadro speed for both UARTs.
298 * To do it we need use formulae from VIC/VAC manual,
299 * keeping in mind Baget's 50MHz frequency...
300 */
301 vac_outw((500000/(384*16))<<8,VAC_CPU_CLK_DIV);
302 }
303
vic_show(void)304 static void __init vic_show(void)
305 {
306 unsigned char val;
307 char *timeout[] = { "4", "16", "32", "64", "128", "256", "disabled" };
308 char *deadlock[] = { "[dedlk only]", "[dedlk only]",
309 "[dedlk], [halt w/ rmc], [lberr]",
310 "[dedlk], [halt w/o rmc], [lberr]" };
311
312 val = vic_inb(VIC_IFACE_CFG);
313 if (val & VIC_IFACE_CFG_VME)
314 printk("VMEbus controller ");
315 if (val & VIC_IFACE_CFG_TURBO)
316 printk("turbo ");
317 if (val & VIC_IFACE_CFG_MSTAB)
318 printk("metastability delay ");
319 printk("%s ",
320 deadlock[VIC_IFACE_CFG_DEADLOCK_VAL(val)]);
321
322
323 printk("interrupts: ");
324 val = vic_inb(VIC_ERR_INT);
325 if (!(val & VIC_ERR_INT_SYSFAIL))
326 printk("[sysfail]");
327 if (!(val & VIC_ERR_INT_TIMO))
328 printk("[timeout]");
329 if (!(val & VIC_ERR_INT_WRPOST))
330 printk("[write post]");
331 if (!(val & VIC_ERR_INT_ACFAIL))
332 printk("[acfail] ");
333 printk("\n");
334
335 printk("timeouts: ");
336 val = vic_inb(VIC_XFER_TIMO);
337 printk("local %s, vme %s ",
338 timeout[VIC_XFER_TIMO_LOCAL_PERIOD_VAL(val)],
339 timeout[VIC_XFER_TIMO_VME_PERIOD_VAL(val)]);
340 if (val & VIC_XFER_TIMO_VME)
341 printk("acquisition ");
342 if (val & VIC_XFER_TIMO_ARB)
343 printk("arbitration ");
344 printk("\n");
345
346 val = vic_inb(VIC_LOCAL_TIM);
347 printk("pas time: (%d,%d), ds time: %d\n",
348 VIC_LOCAL_TIM_PAS_ASSERT_VAL(val),
349 VIC_LOCAL_TIM_PAS_DEASSERT_VAL(val),
350 VIC_LOCAT_TIM_DS_DEASSERT_VAL(val));
351
352 val = vic_inb(VIC_BXFER_DEF);
353 printk("dma: ");
354 if (val & VIC_BXFER_DEF_DUAL)
355 printk("[dual path]");
356 if (val & VIC_BXFER_DEF_LOCAL_CROSS)
357 printk("[local boundary cross]");
358 if (val & VIC_BXFER_DEF_VME_CROSS)
359 printk("[vme boundary cross]");
360
361 }
362
vic_init(void)363 static void __init vic_init(void)
364 {
365 unsigned char id = vic_inb(VIC_ID);
366 if ((id & 0xf0) != 0xf0)
367 panic("VIC not found");
368 printk(" VIC068A Rev. %X: ", id & 0x0f);
369
370 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_II);
371 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_INT1);
372 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_INT2);
373 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_INT3);
374 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE,VIC_VME_INT4);
375 /*
376 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE, VIC_VME_INT5);
377 */
378 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE, VIC_VME_INT6);
379
380 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE, VIC_VME_INT7);
381 vic_outb(VIC_INT_IPL(3)|VIC_INT_DISABLE, VIC_DMA_INT);
382 vic_outb(VIC_INT_IPL(3)|VIC_INT_NOAUTO|VIC_INT_EDGE|
383 VIC_INT_LOW|VIC_INT_DISABLE, VIC_LINT1);
384 vic_outb(VIC_INT_IPL(3)|VIC_INT_NOAUTO|VIC_INT_EDGE|
385 VIC_INT_HIGH|VIC_INT_DISABLE, VIC_LINT2);
386 vic_outb(VIC_INT_IPL(3)|VIC_INT_NOAUTO|VIC_INT_EDGE|
387 VIC_INT_HIGH|VIC_INT_DISABLE, VIC_LINT3);
388 vic_outb(VIC_INT_IPL(3)|VIC_INT_NOAUTO|VIC_INT_EDGE|
389 VIC_INT_LOW|VIC_INT_DISABLE, VIC_LINT4);
390 /*
391 vic_outb(VIC_INT_IPL(3)|VIC_INT_NOAUTO|VIC_INT_LEVEL|
392 VIC_INT_LOW|VIC_INT_DISABLE, VIC_LINT5);
393 */
394 vic_outb(VIC_INT_IPL(6)|VIC_INT_NOAUTO|VIC_INT_EDGE|
395 VIC_INT_LOW|VIC_INT_DISABLE, VIC_LINT6);
396 vic_outb(VIC_INT_IPL(6)|VIC_INT_NOAUTO|VIC_INT_EDGE|
397 VIC_INT_LOW|VIC_INT_DISABLE, VIC_LINT7);
398
399 vic_outb(VIC_INT_IPL(3)|
400 VIC_INT_SWITCH(0)|
401 VIC_INT_SWITCH(1)|
402 VIC_INT_SWITCH(2)|
403 VIC_INT_SWITCH(3), VIC_ICGS_INT);
404 vic_outb(VIC_INT_IPL(3)|
405 VIC_INT_SWITCH(0)|
406 VIC_INT_SWITCH(1)|
407 VIC_INT_SWITCH(2)|
408 VIC_INT_SWITCH(3), VIC_ICMS_INT);
409 vic_outb(VIC_INT_IPL(6)|
410 VIC_ERR_INT_SYSFAIL|
411 VIC_ERR_INT_TIMO|
412 VIC_ERR_INT_WRPOST|
413 VIC_ERR_INT_ACFAIL, VIC_ERR_INT);
414 vic_outb(VIC_ICxS_BASE_ID(0xf), VIC_ICGS_BASE);
415 vic_outb(VIC_ICxS_BASE_ID(0xe), VIC_ICMS_BASE);
416 vic_outb(VIC_LOCAL_BASE_ID(0x6), VIC_LOCAL_BASE);
417 vic_outb(VIC_ERR_BASE_ID(0x3), VIC_ERR_BASE);
418 vic_outb(VIC_XFER_TIMO_VME_PERIOD_32|
419 VIC_XFER_TIMO_LOCAL_PERIOD_32, VIC_XFER_TIMO);
420 vic_outb(VIC_LOCAL_TIM_PAS_ASSERT(2)|
421 VIC_LOCAT_TIM_DS_DEASSERT(1)|
422 VIC_LOCAL_TIM_PAS_DEASSERT(1), VIC_LOCAL_TIM);
423 vic_outb(VIC_BXFER_DEF_VME_CROSS|
424 VIC_BXFER_DEF_LOCAL_CROSS|
425 VIC_BXFER_DEF_AMSR|
426 VIC_BXFER_DEF_DUAL, VIC_BXFER_DEF);
427 vic_outb(VIC_SSxCR0_LOCAL_XFER_SINGLE|
428 VIC_SSxCR0_A32|VIC_SSxCR0_D32|
429 VIC_SS0CR0_TIMER_FREQ_NONE, VIC_SS0CR0);
430 vic_outb(VIC_SSxCR1_TF1(0xf)|
431 VIC_SSxCR1_TF2(0xf), VIC_SS0CR1);
432 vic_outb(VIC_SSxCR0_LOCAL_XFER_SINGLE|
433 VIC_SSxCR0_A24|VIC_SSxCR0_D32, VIC_SS1CR0);
434 vic_outb(VIC_SSxCR1_TF1(0xf)|
435 VIC_SSxCR1_TF2(0xf), VIC_SS1CR1);
436 vic_outb(VIC_IFACE_CFG_NOHALT|
437 VIC_IFACE_CFG_NOTURBO, VIC_IFACE_CFG);
438 vic_outb(VIC_AMS_CODE(0), VIC_AMS);
439 vic_outb(VIC_BXFER_CTRL_INTERLEAVE(0), VIC_BXFER_CTRL);
440 vic_outb(0, VIC_BXFER_LEN_LO);
441 vic_outb(0, VIC_BXFER_LEN_HI);
442 vic_outb(VIC_REQ_CFG_FAIRNESS_DISABLED|
443 VIC_REQ_CFG_LEVEL(3)|
444 VIC_REQ_CFG_RR_ARBITRATION, VIC_REQ_CFG);
445 vic_outb(VIC_RELEASE_BLKXFER_BLEN(0)|
446 VIC_RELEASE_RWD, VIC_RELEASE);
447 vic_outb(VIC_IC6_RUN, VIC_IC6);
448 vic_outb(0, VIC_IC7);
449
450 vic_show();
451 }
452
vic_start(void)453 static void vic_start(void)
454 {
455 vic_outb(VIC_INT_IPL(3)|
456 VIC_INT_NOAUTO|
457 VIC_INT_EDGE|
458 VIC_INT_HIGH|
459 VIC_INT_ENABLE, VIC_LINT7);
460 }
461
baget_irq_setup(void)462 void __init baget_irq_setup(void)
463 {
464 extern void bagetIRQ(void);
465
466 /* Now, it's safe to set the exception vector. */
467 set_except_vector(0, bagetIRQ);
468 }
469
470 extern void baget_machine_restart(char *command);
471 extern void baget_machine_halt(void);
472 extern void baget_machine_power_off(void);
473
baget_setup(void)474 void __init baget_setup(void)
475 {
476 printk("BT23/63-201n found.\n");
477 *BAGET_WRERR_ACK = 0;
478 irq_setup = baget_irq_setup;
479
480 _machine_restart = baget_machine_restart;
481 _machine_halt = baget_machine_halt;
482 _machine_power_off = baget_machine_power_off;
483
484 vac_init();
485 vic_init();
486 vac_start();
487 vic_start();
488 }
489