1 /*
2     NetWinder Floating Point Emulator
3     (c) Rebel.COM, 1998,1999
4     (c) Philip Blundell, 2001
5 
6     Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
7 
8     This program is free software; you can redistribute it and/or modify
9     it under the terms of the GNU General Public License as published by
10     the Free Software Foundation; either version 2 of the License, or
11     (at your option) any later version.
12 
13     This program is distributed in the hope that it will be useful,
14     but WITHOUT ANY WARRANTY; without even the implied warranty of
15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16     GNU General Public License for more details.
17 
18     You should have received a copy of the GNU General Public License
19     along with this program; if not, write to the Free Software
20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22 
23 #ifndef __FPOPCODE_H__
24 #define __FPOPCODE_H__
25 
26 /*
27 ARM Floating Point Instruction Classes
28 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
29 |c o n d|1 1 0 P|U|u|W|L|   Rn  |v|  Fd |0|0|0|1|  o f f s e t  | CPDT
30 |c o n d|1 1 0 P|U|w|W|L|   Rn  |x|  Fd |0|0|1|0|  o f f s e t  | CPDT (copro 2)
31 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
32 |c o n d|1 1 1 0|a|b|c|d|e|  Fn |j|  Fd |0|0|0|1|f|g|h|0|i|  Fm | CPDO
33 |c o n d|1 1 1 0|a|b|c|L|e|  Fn |   Rd  |0|0|0|1|f|g|h|1|i|  Fm | CPRT
34 |c o n d|1 1 1 0|a|b|c|1|e|  Fn |1|1|1|1|0|0|0|1|f|g|h|1|i|  Fm | comparisons
35 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
36 
37 CPDT		data transfer instructions
38 		LDF, STF, LFM (copro 2), SFM (copro 2)
39 
40 CPDO		dyadic arithmetic instructions
41 		ADF, MUF, SUF, RSF, DVF, RDF,
42 		POW, RPW, RMF, FML, FDV, FRD, POL
43 
44 CPDO		monadic arithmetic instructions
45 		MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
46 		SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
47 
48 CPRT		joint arithmetic/data transfer instructions
49 		FIX (arithmetic followed by load/store)
50 		FLT (load/store followed by arithmetic)
51 		CMF, CNF CMFE, CNFE (comparisons)
52 		WFS, RFS (write/read floating point status register)
53 		WFC, RFC (write/read floating point control register)
54 
55 cond		condition codes
56 P		pre/post index bit: 0 = postindex, 1 = preindex
57 U		up/down bit: 0 = stack grows down, 1 = stack grows up
58 W		write back bit: 1 = update base register (Rn)
59 L		load/store bit: 0 = store, 1 = load
60 Rn		base register
61 Rd		destination/source register
62 Fd		floating point destination register
63 Fn		floating point source register
64 Fm		floating point source register or floating point constant
65 
66 uv		transfer length (TABLE 1)
67 wx		register count (TABLE 2)
68 abcd		arithmetic opcode (TABLES 3 & 4)
69 ef		destination size (rounding precision) (TABLE 5)
70 gh		rounding mode (TABLE 6)
71 j		dyadic/monadic bit: 0 = dyadic, 1 = monadic
72 i 		constant bit: 1 = constant (TABLE 6)
73 */
74 
75 /*
76 TABLE 1
77 +-------------------------+---+---+---------+---------+
78 |  Precision              | u | v | FPSR.EP | length  |
79 +-------------------------+---+---+---------+---------+
80 | Single                  | 0 � 0 |    x    | 1 words |
81 | Double                  | 1 � 1 |    x    | 2 words |
82 | Extended                | 1 � 1 |    x    | 3 words |
83 | Packed decimal          | 1 � 1 |    0    | 3 words |
84 | Expanded packed decimal | 1 � 1 |    1    | 4 words |
85 +-------------------------+---+---+---------+---------+
86 Note: x = don't care
87 */
88 
89 /*
90 TABLE 2
91 +---+---+---------------------------------+
92 | w | x | Number of registers to transfer |
93 +---+---+---------------------------------+
94 | 0 � 1 |  1                              |
95 | 1 � 0 |  2                              |
96 | 1 � 1 |  3                              |
97 | 0 � 0 |  4                              |
98 +---+---+---------------------------------+
99 */
100 
101 /*
102 TABLE 3: Dyadic Floating Point Opcodes
103 +---+---+---+---+----------+-----------------------+-----------------------+
104 | a | b | c | d | Mnemonic | Description           | Operation             |
105 +---+---+---+---+----------+-----------------------+-----------------------+
106 | 0 | 0 | 0 | 0 | ADF      | Add                   | Fd := Fn + Fm         |
107 | 0 | 0 | 0 | 1 | MUF      | Multiply              | Fd := Fn * Fm         |
108 | 0 | 0 | 1 | 0 | SUF      | Subtract              | Fd := Fn - Fm         |
109 | 0 | 0 | 1 | 1 | RSF      | Reverse subtract      | Fd := Fm - Fn         |
110 | 0 | 1 | 0 | 0 | DVF      | Divide                | Fd := Fn / Fm         |
111 | 0 | 1 | 0 | 1 | RDF      | Reverse divide        | Fd := Fm / Fn         |
112 | 0 | 1 | 1 | 0 | POW      | Power                 | Fd := Fn ^ Fm         |
113 | 0 | 1 | 1 | 1 | RPW      | Reverse power         | Fd := Fm ^ Fn         |
114 | 1 | 0 | 0 | 0 | RMF      | Remainder             | Fd := IEEE rem(Fn/Fm) |
115 | 1 | 0 | 0 | 1 | FML      | Fast Multiply         | Fd := Fn * Fm         |
116 | 1 | 0 | 1 | 0 | FDV      | Fast Divide           | Fd := Fn / Fm         |
117 | 1 | 0 | 1 | 1 | FRD      | Fast reverse divide   | Fd := Fm / Fn         |
118 | 1 | 1 | 0 | 0 | POL      | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm)  |
119 | 1 | 1 | 0 | 1 |          | undefined instruction | trap                  |
120 | 1 | 1 | 1 | 0 |          | undefined instruction | trap                  |
121 | 1 | 1 | 1 | 1 |          | undefined instruction | trap                  |
122 +---+---+---+---+----------+-----------------------+-----------------------+
123 Note: POW, RPW, POL are deprecated, and are available for backwards
124       compatibility only.
125 */
126 
127 /*
128 TABLE 4: Monadic Floating Point Opcodes
129 +---+---+---+---+----------+-----------------------+-----------------------+
130 | a | b | c | d | Mnemonic | Description           | Operation             |
131 +---+---+---+---+----------+-----------------------+-----------------------+
132 | 0 | 0 | 0 | 0 | MVF      | Move                  | Fd := Fm              |
133 | 0 | 0 | 0 | 1 | MNF      | Move negated          | Fd := - Fm            |
134 | 0 | 0 | 1 | 0 | ABS      | Absolute value        | Fd := abs(Fm)         |
135 | 0 | 0 | 1 | 1 | RND      | Round to integer      | Fd := int(Fm)         |
136 | 0 | 1 | 0 | 0 | SQT      | Square root           | Fd := sqrt(Fm)        |
137 | 0 | 1 | 0 | 1 | LOG      | Log base 10           | Fd := log10(Fm)       |
138 | 0 | 1 | 1 | 0 | LGN      | Log base e            | Fd := ln(Fm)          |
139 | 0 | 1 | 1 | 1 | EXP      | Exponent              | Fd := e ^ Fm          |
140 | 1 | 0 | 0 | 0 | SIN      | Sine                  | Fd := sin(Fm)         |
141 | 1 | 0 | 0 | 1 | COS      | Cosine                | Fd := cos(Fm)         |
142 | 1 | 0 | 1 | 0 | TAN      | Tangent               | Fd := tan(Fm)         |
143 | 1 | 0 | 1 | 1 | ASN      | Arc Sine              | Fd := arcsin(Fm)      |
144 | 1 | 1 | 0 | 0 | ACS      | Arc Cosine            | Fd := arccos(Fm)      |
145 | 1 | 1 | 0 | 1 | ATN      | Arc Tangent           | Fd := arctan(Fm)      |
146 | 1 | 1 | 1 | 0 | URD      | Unnormalized round    | Fd := int(Fm)         |
147 | 1 | 1 | 1 | 1 | NRM      | Normalize             | Fd := norm(Fm)        |
148 +---+---+---+---+----------+-----------------------+-----------------------+
149 Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
150       available for backwards compatibility only.
151 */
152 
153 /*
154 TABLE 5
155 +-------------------------+---+---+
156 |  Rounding Precision     | e | f |
157 +-------------------------+---+---+
158 | IEEE Single precision   | 0 � 0 |
159 | IEEE Double precision   | 0 � 1 |
160 | IEEE Extended precision | 1 � 0 |
161 | undefined (trap)        | 1 � 1 |
162 +-------------------------+---+---+
163 */
164 
165 /*
166 TABLE 5
167 +---------------------------------+---+---+
168 |  Rounding Mode                  | g | h |
169 +---------------------------------+---+---+
170 | Round to nearest (default)      | 0 � 0 |
171 | Round toward plus infinity      | 0 � 1 |
172 | Round toward negative infinity  | 1 � 0 |
173 | Round toward zero               | 1 � 1 |
174 +---------------------------------+---+---+
175 */
176 
177 /*
178 ===
179 === Definitions for load and store instructions
180 ===
181 */
182 
183 /* bit masks */
184 #define BIT_PREINDEX	0x01000000
185 #define BIT_UP		0x00800000
186 #define BIT_WRITE_BACK	0x00200000
187 #define BIT_LOAD	0x00100000
188 
189 /* masks for load/store */
190 #define MASK_CPDT		0x0c000000	/* data processing opcode */
191 #define MASK_OFFSET		0x000000ff
192 #define MASK_TRANSFER_LENGTH	0x00408000
193 #define MASK_REGISTER_COUNT	MASK_TRANSFER_LENGTH
194 #define MASK_COPROCESSOR	0x00000f00
195 
196 /* Tests for transfer length */
197 #define TRANSFER_SINGLE		0x00000000
198 #define TRANSFER_DOUBLE		0x00008000
199 #define TRANSFER_EXTENDED	0x00400000
200 #define TRANSFER_PACKED		MASK_TRANSFER_LENGTH
201 
202 /* Get the coprocessor number from the opcode. */
203 #define getCoprocessorNumber(opcode)	((opcode & MASK_COPROCESSOR) >> 8)
204 
205 /* Get the offset from the opcode. */
206 #define getOffset(opcode)		(opcode & MASK_OFFSET)
207 
208 /* Tests for specific data transfer load/store opcodes. */
209 #define TEST_OPCODE(opcode,mask)	(((opcode) & (mask)) == (mask))
210 
211 #define LOAD_OP(opcode)   TEST_OPCODE((opcode),MASK_CPDT | BIT_LOAD)
212 #define STORE_OP(opcode)  ((opcode & (MASK_CPDT | BIT_LOAD)) == MASK_CPDT)
213 
214 #define LDF_OP(opcode)	(LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
215 #define LFM_OP(opcode)	(LOAD_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
216 #define STF_OP(opcode)	(STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 1))
217 #define SFM_OP(opcode)	(STORE_OP(opcode) && (getCoprocessorNumber(opcode) == 2))
218 
219 #define PREINDEXED(opcode)		((opcode & BIT_PREINDEX) != 0)
220 #define POSTINDEXED(opcode)		((opcode & BIT_PREINDEX) == 0)
221 #define BIT_UP_SET(opcode)		((opcode & BIT_UP) != 0)
222 #define BIT_UP_CLEAR(opcode)		((opcode & BIT_DOWN) == 0)
223 #define WRITE_BACK(opcode)		((opcode & BIT_WRITE_BACK) != 0)
224 #define LOAD(opcode)			((opcode & BIT_LOAD) != 0)
225 #define STORE(opcode)			((opcode & BIT_LOAD) == 0)
226 
227 /*
228 ===
229 === Definitions for arithmetic instructions
230 ===
231 */
232 /* bit masks */
233 #define BIT_MONADIC	0x00008000
234 #define BIT_CONSTANT	0x00000008
235 
236 #define CONSTANT_FM(opcode)		((opcode & BIT_CONSTANT) != 0)
237 #define MONADIC_INSTRUCTION(opcode)	((opcode & BIT_MONADIC) != 0)
238 
239 /* instruction identification masks */
240 #define MASK_CPDO		0x0e000000	/* arithmetic opcode */
241 #define MASK_ARITHMETIC_OPCODE	0x00f08000
242 #define MASK_DESTINATION_SIZE	0x00080080
243 
244 /* dyadic arithmetic opcodes. */
245 #define ADF_CODE	0x00000000
246 #define MUF_CODE	0x00100000
247 #define SUF_CODE	0x00200000
248 #define RSF_CODE	0x00300000
249 #define DVF_CODE	0x00400000
250 #define RDF_CODE	0x00500000
251 #define POW_CODE	0x00600000
252 #define RPW_CODE	0x00700000
253 #define RMF_CODE	0x00800000
254 #define FML_CODE	0x00900000
255 #define FDV_CODE	0x00a00000
256 #define FRD_CODE	0x00b00000
257 #define POL_CODE	0x00c00000
258 /* 0x00d00000 is an invalid dyadic arithmetic opcode */
259 /* 0x00e00000 is an invalid dyadic arithmetic opcode */
260 /* 0x00f00000 is an invalid dyadic arithmetic opcode */
261 
262 /* monadic arithmetic opcodes. */
263 #define MVF_CODE	0x00008000
264 #define MNF_CODE	0x00108000
265 #define ABS_CODE	0x00208000
266 #define RND_CODE	0x00308000
267 #define SQT_CODE	0x00408000
268 #define LOG_CODE	0x00508000
269 #define LGN_CODE	0x00608000
270 #define EXP_CODE	0x00708000
271 #define SIN_CODE	0x00808000
272 #define COS_CODE	0x00908000
273 #define TAN_CODE	0x00a08000
274 #define ASN_CODE	0x00b08000
275 #define ACS_CODE	0x00c08000
276 #define ATN_CODE	0x00d08000
277 #define URD_CODE	0x00e08000
278 #define NRM_CODE	0x00f08000
279 
280 /*
281 ===
282 === Definitions for register transfer and comparison instructions
283 ===
284 */
285 
286 #define MASK_CPRT		0x0e000010	/* register transfer opcode */
287 #define MASK_CPRT_CODE		0x00f00000
288 #define FLT_CODE		0x00000000
289 #define FIX_CODE		0x00100000
290 #define WFS_CODE		0x00200000
291 #define RFS_CODE		0x00300000
292 #define WFC_CODE		0x00400000
293 #define RFC_CODE		0x00500000
294 #define CMF_CODE		0x00900000
295 #define CNF_CODE		0x00b00000
296 #define CMFE_CODE		0x00d00000
297 #define CNFE_CODE		0x00f00000
298 
299 /*
300 ===
301 === Common definitions
302 ===
303 */
304 
305 /* register masks */
306 #define MASK_Rd		0x0000f000
307 #define MASK_Rn		0x000f0000
308 #define MASK_Fd		0x00007000
309 #define MASK_Fm		0x00000007
310 #define MASK_Fn		0x00070000
311 
312 /* condition code masks */
313 #define CC_MASK		0xf0000000
314 #define CC_NEGATIVE	0x80000000
315 #define CC_ZERO		0x40000000
316 #define CC_CARRY	0x20000000
317 #define CC_OVERFLOW	0x10000000
318 #define CC_EQ		0x00000000
319 #define CC_NE		0x10000000
320 #define CC_CS		0x20000000
321 #define CC_HS		CC_CS
322 #define CC_CC		0x30000000
323 #define CC_LO		CC_CC
324 #define CC_MI		0x40000000
325 #define CC_PL		0x50000000
326 #define CC_VS		0x60000000
327 #define CC_VC		0x70000000
328 #define CC_HI		0x80000000
329 #define CC_LS		0x90000000
330 #define CC_GE		0xa0000000
331 #define CC_LT		0xb0000000
332 #define CC_GT		0xc0000000
333 #define CC_LE		0xd0000000
334 #define CC_AL		0xe0000000
335 #define CC_NV		0xf0000000
336 
337 /* rounding masks/values */
338 #define MASK_ROUNDING_MODE	0x00000060
339 #define ROUND_TO_NEAREST	0x00000000
340 #define ROUND_TO_PLUS_INFINITY	0x00000020
341 #define ROUND_TO_MINUS_INFINITY	0x00000040
342 #define ROUND_TO_ZERO		0x00000060
343 
344 #define MASK_ROUNDING_PRECISION	0x00080080
345 #define ROUND_SINGLE		0x00000000
346 #define ROUND_DOUBLE		0x00000080
347 #define ROUND_EXTENDED		0x00080000
348 
349 /* Get the condition code from the opcode. */
350 #define getCondition(opcode)		(opcode >> 28)
351 
352 /* Get the source register from the opcode. */
353 #define getRn(opcode)			((opcode & MASK_Rn) >> 16)
354 
355 /* Get the destination floating point register from the opcode. */
356 #define getFd(opcode)			((opcode & MASK_Fd) >> 12)
357 
358 /* Get the first source floating point register from the opcode. */
359 #define getFn(opcode)		((opcode & MASK_Fn) >> 16)
360 
361 /* Get the second source floating point register from the opcode. */
362 #define getFm(opcode)		(opcode & MASK_Fm)
363 
364 /* Get the destination register from the opcode. */
365 #define getRd(opcode)		((opcode & MASK_Rd) >> 12)
366 
367 /* Get the rounding mode from the opcode. */
368 #define getRoundingMode(opcode)		((opcode & MASK_ROUNDING_MODE) >> 5)
369 
370 #ifdef CONFIG_FPE_NWFPE_XP
getExtendedConstant(const unsigned int nIndex)371 static inline const floatx80 getExtendedConstant(const unsigned int nIndex)
372 {
373 	extern const floatx80 floatx80Constant[];
374 	return floatx80Constant[nIndex];
375 }
376 #endif
377 
getDoubleConstant(const unsigned int nIndex)378 static inline const float64 getDoubleConstant(const unsigned int nIndex)
379 {
380 	extern const float64 float64Constant[];
381 	return float64Constant[nIndex];
382 }
383 
getSingleConstant(const unsigned int nIndex)384 static inline const float32 getSingleConstant(const unsigned int nIndex)
385 {
386 	extern const float32 float32Constant[];
387 	return float32Constant[nIndex];
388 }
389 
getTransferLength(const unsigned int opcode)390 static inline unsigned int getTransferLength(const unsigned int opcode)
391 {
392 	unsigned int nRc;
393 
394 	switch (opcode & MASK_TRANSFER_LENGTH) {
395 	case 0x00000000:
396 		nRc = 1;
397 		break;		/* single precision */
398 	case 0x00008000:
399 		nRc = 2;
400 		break;		/* double precision */
401 	case 0x00400000:
402 		nRc = 3;
403 		break;		/* extended precision */
404 	default:
405 		nRc = 0;
406 	}
407 
408 	return (nRc);
409 }
410 
getRegisterCount(const unsigned int opcode)411 static inline unsigned int getRegisterCount(const unsigned int opcode)
412 {
413 	unsigned int nRc;
414 
415 	switch (opcode & MASK_REGISTER_COUNT) {
416 	case 0x00000000:
417 		nRc = 4;
418 		break;
419 	case 0x00008000:
420 		nRc = 1;
421 		break;
422 	case 0x00400000:
423 		nRc = 2;
424 		break;
425 	case 0x00408000:
426 		nRc = 3;
427 		break;
428 	default:
429 		nRc = 0;
430 	}
431 
432 	return (nRc);
433 }
434 
getRoundingPrecision(const unsigned int opcode)435 static inline unsigned int getRoundingPrecision(const unsigned int opcode)
436 {
437 	unsigned int nRc;
438 
439 	switch (opcode & MASK_ROUNDING_PRECISION) {
440 	case 0x00000000:
441 		nRc = 1;
442 		break;
443 	case 0x00000080:
444 		nRc = 2;
445 		break;
446 	case 0x00080000:
447 		nRc = 3;
448 		break;
449 	default:
450 		nRc = 0;
451 	}
452 
453 	return (nRc);
454 }
455 
getDestinationSize(const unsigned int opcode)456 static inline unsigned int getDestinationSize(const unsigned int opcode)
457 {
458 	unsigned int nRc;
459 
460 	switch (opcode & MASK_DESTINATION_SIZE) {
461 	case 0x00000000:
462 		nRc = typeSingle;
463 		break;
464 	case 0x00000080:
465 		nRc = typeDouble;
466 		break;
467 	case 0x00080000:
468 		nRc = typeExtended;
469 		break;
470 	default:
471 		nRc = typeNone;
472 	}
473 
474 	return (nRc);
475 }
476 
477 #endif
478