xref: /DragonStub/inc/efipart.h (revision 530d68ba191850edafc6da22cb2df55bec0c5fa5)
1*530d68baSNigel Croxon #ifndef _EFI_PART_H
2*530d68baSNigel Croxon #define _EFI_PART_H
3*530d68baSNigel Croxon 
4*530d68baSNigel Croxon /*++
5*530d68baSNigel Croxon 
6*530d68baSNigel Croxon Copyright (c) 1998  Intel Corporation
7*530d68baSNigel Croxon 
8*530d68baSNigel Croxon Module Name:
9*530d68baSNigel Croxon 
10*530d68baSNigel Croxon     efipart.h
11*530d68baSNigel Croxon 
12*530d68baSNigel Croxon Abstract:
13*530d68baSNigel Croxon     Info about disk partitions and Master Boot Records
14*530d68baSNigel Croxon 
15*530d68baSNigel Croxon 
16*530d68baSNigel Croxon 
17*530d68baSNigel Croxon 
18*530d68baSNigel Croxon Revision History
19*530d68baSNigel Croxon 
20*530d68baSNigel Croxon --*/
21*530d68baSNigel Croxon 
22*530d68baSNigel Croxon //
23*530d68baSNigel Croxon //
24*530d68baSNigel Croxon //
25*530d68baSNigel Croxon 
26*530d68baSNigel Croxon #define EFI_PARTITION   0xef
27*530d68baSNigel Croxon #define MBR_SIZE        512
28*530d68baSNigel Croxon 
29*530d68baSNigel Croxon #pragma pack(1)
30*530d68baSNigel Croxon 
31*530d68baSNigel Croxon typedef struct {
32*530d68baSNigel Croxon     UINT8       BootIndicator;
33*530d68baSNigel Croxon     UINT8       StartHead;
34*530d68baSNigel Croxon     UINT8       StartSector;
35*530d68baSNigel Croxon     UINT8       StartTrack;
36*530d68baSNigel Croxon     UINT8       OSIndicator;
37*530d68baSNigel Croxon     UINT8       EndHead;
38*530d68baSNigel Croxon     UINT8       EndSector;
39*530d68baSNigel Croxon     UINT8       EndTrack;
40*530d68baSNigel Croxon     UINT8       StartingLBA[4];
41*530d68baSNigel Croxon     UINT8       SizeInLBA[4];
42*530d68baSNigel Croxon } MBR_PARTITION_RECORD;
43*530d68baSNigel Croxon 
44*530d68baSNigel Croxon #define EXTRACT_UINT32(D) (UINT32)(D[0] | (D[1] << 8) | (D[2] << 16) | (D[3] << 24))
45*530d68baSNigel Croxon 
46*530d68baSNigel Croxon #define MBR_SIGNATURE           0xaa55
47*530d68baSNigel Croxon #define MIN_MBR_DEVICE_SIZE     0x80000
48*530d68baSNigel Croxon #define MBR_ERRATA_PAD          0x40000 // 128 MB
49*530d68baSNigel Croxon 
50*530d68baSNigel Croxon #define MAX_MBR_PARTITIONS  4
51*530d68baSNigel Croxon typedef struct {
52*530d68baSNigel Croxon     UINT8                   BootStrapCode[440];
53*530d68baSNigel Croxon     UINT8                   UniqueMbrSignature[4];
54*530d68baSNigel Croxon     UINT8                   Unknown[2];
55*530d68baSNigel Croxon     MBR_PARTITION_RECORD    Partition[MAX_MBR_PARTITIONS];
56*530d68baSNigel Croxon     UINT16                  Signature;
57*530d68baSNigel Croxon } MASTER_BOOT_RECORD;
58*530d68baSNigel Croxon #pragma pack()
59*530d68baSNigel Croxon 
60*530d68baSNigel Croxon 
61*530d68baSNigel Croxon #endif
62