1 #ifndef _EFI_PXE_H 2 #define _EFI_PXE_H 3 4 5 /*++ 6 Copyright (c) Intel 1999 7 8 Module name: 9 efi_pxe.h 10 11 32/64-bit PXE specification: 12 alpha-4, 99-Dec-17 13 14 Abstract: 15 This header file contains all of the PXE type definitions, 16 structure prototypes, global variables and constants that 17 are needed for porting PXE to EFI. 18 --*/ 19 20 #pragma pack(1) 21 22 #define PXE_INTEL_ORDER 1 // Intel order 23 //#define PXE_NETWORK_ORDER 1 // network order 24 25 #define PXE_UINT64_SUPPORT 1 // UINT64 supported 26 //#define PXE_NO_UINT64_SUPPORT 1 // UINT64 not supported 27 28 #define PXE_BUSTYPE(a,b,c,d) \ 29 ((((PXE_UINT32)(d) & 0xFF) << 24) | \ 30 (((PXE_UINT32)(c) & 0xFF) << 16) | \ 31 (((PXE_UINT32)(b) & 0xFF) << 8) | \ 32 ((PXE_UINT32)(a) & 0xFF)) 33 34 // 35 // UNDI ROM ID and devive ID signature 36 // 37 #define PXE_BUSTYPE_PXE PXE_BUSTYPE('!', 'P', 'X', 'E') 38 39 // 40 // BUS ROM ID signatures 41 // 42 #define PXE_BUSTYPE_PCI PXE_BUSTYPE('P', 'C', 'I', 'R') 43 #define PXE_BUSTYPE_PC_CARD PXE_BUSTYPE('P', 'C', 'C', 'R') 44 #define PXE_BUSTYPE_USB PXE_BUSTYPE('U', 'S', 'B', 'R') 45 #define PXE_BUSTYPE_1394 PXE_BUSTYPE('1', '3', '9', '4') 46 47 #define PXE_SWAP_UINT16(n) \ 48 ((((PXE_UINT16)(n) & 0x00FF) << 8) | \ 49 (((PXE_UINT16)(n) & 0xFF00) >> 8)) 50 51 #define PXE_SWAP_UINT32(n) \ 52 ((((PXE_UINT32)(n) & 0x000000FF) << 24) | \ 53 (((PXE_UINT32)(n) & 0x0000FF00) << 8) | \ 54 (((PXE_UINT32)(n) & 0x00FF0000) >> 8) | \ 55 (((PXE_UINT32)(n) & 0xFF000000) >> 24)) 56 57 #if PXE_UINT64_SUPPORT != 0 58 #define PXE_SWAP_UINT64(n) \ 59 ((((PXE_UINT64)(n) & 0x00000000000000FF) << 56) | \ 60 (((PXE_UINT64)(n) & 0x000000000000FF00) << 40) | \ 61 (((PXE_UINT64)(n) & 0x0000000000FF0000) << 24) | \ 62 (((PXE_UINT64)(n) & 0x00000000FF000000) << 8) | \ 63 (((PXE_UINT64)(n) & 0x000000FF00000000) >> 8) | \ 64 (((PXE_UINT64)(n) & 0x0000FF0000000000) >> 24) | \ 65 (((PXE_UINT64)(n) & 0x00FF000000000000) >> 40) | \ 66 (((PXE_UINT64)(n) & 0xFF00000000000000) >> 56)) 67 #endif // PXE_UINT64_SUPPORT 68 69 #if PXE_NO_UINT64_SUPPORT != 0 70 #define PXE_SWAP_UINT64(n) \ 71 { \ 72 PXE_UINT32 tmp = (PXE_UINT64)(n)[1]; \ 73 (PXE_UINT64)(n)[1] = PXE_SWAP_UINT32((PXE_UINT64)(n)[0]); \ 74 (PXE_UINT64)(n)[0] = tmp; \ 75 } 76 #endif // PXE_NO_UINT64_SUPPORT 77 78 #define PXE_CPBSIZE_NOT_USED 0 // zero 79 #define PXE_DBSIZE_NOT_USED 0 // zero 80 #define PXE_CPBADDR_NOT_USED (PXE_UINT64)0 // zero 81 #define PXE_DBADDR_NOT_USED (PXE_UINT64)0 // zero 82 83 #define PXE_CONST const 84 85 #define PXE_VOLATILE volatile 86 87 typedef void PXE_VOID; 88 89 typedef unsigned char PXE_UINT8; 90 91 typedef unsigned short PXE_UINT16; 92 93 typedef unsigned PXE_UINT32; 94 95 #if PXE_UINT64_SUPPORT != 0 96 // typedef unsigned long PXE_UINT64; 97 typedef UINT64 PXE_UINT64; 98 #endif // PXE_UINT64_SUPPORT 99 100 #if PXE_NO_UINT64_SUPPORT != 0 101 typedef PXE_UINT32 PXE_UINT64[2]; 102 #endif // PXE_NO_UINT64_SUPPORT 103 104 typedef unsigned PXE_UINTN; 105 106 typedef PXE_UINT8 PXE_BOOL; 107 108 #define PXE_FALSE 0 // zero 109 #define PXE_TRUE (!PXE_FALSE) 110 111 typedef PXE_UINT16 PXE_OPCODE; 112 113 // 114 // Return UNDI operational state. 115 // 116 #define PXE_OPCODE_GET_STATE 0x0000 117 118 // 119 // Change UNDI operational state from Stopped to Started. 120 // 121 #define PXE_OPCODE_START 0x0001 122 123 // 124 // Change UNDI operational state from Started to Stopped. 125 // 126 #define PXE_OPCODE_STOP 0x0002 127 128 // 129 // Get UNDI initialization information. 130 // 131 #define PXE_OPCODE_GET_INIT_INFO 0x0003 132 133 // 134 // Get NIC configuration information. 135 // 136 #define PXE_OPCODE_GET_CONFIG_INFO 0x0004 137 138 // 139 // Changed UNDI operational state from Started to Initialized. 140 // 141 #define PXE_OPCODE_INITIALIZE 0x0005 142 143 // 144 // Re-initialize the NIC H/W. 145 // 146 #define PXE_OPCODE_RESET 0x0006 147 148 // 149 // Change the UNDI operational state from Initialized to Started. 150 // 151 #define PXE_OPCODE_SHUTDOWN 0x0007 152 153 // 154 // Read & change state of external interrupt enables. 155 // 156 #define PXE_OPCODE_INTERRUPT_ENABLES 0x0008 157 158 // 159 // Read & change state of packet receive filters. 160 // 161 #define PXE_OPCODE_RECEIVE_FILTERS 0x0009 162 163 // 164 // Read & change station MAC address. 165 // 166 #define PXE_OPCODE_STATION_ADDRESS 0x000A 167 168 // 169 // Read traffic statistics. 170 // 171 #define PXE_OPCODE_STATISTICS 0x000B 172 173 // 174 // Convert multicast IP address to multicast MAC address. 175 // 176 #define PXE_OPCODE_MCAST_IP_TO_MAC 0x000C 177 178 // 179 // Read or change non-volatile storage on the NIC. 180 // 181 #define PXE_OPCODE_NVDATA 0x000D 182 183 // 184 // Get & clear interrupt status. 185 // 186 #define PXE_OPCODE_GET_STATUS 0x000E 187 188 // 189 // Fill media header in packet for transmit. 190 // 191 #define PXE_OPCODE_FILL_HEADER 0x000F 192 193 // 194 // Transmit packet(s). 195 // 196 #define PXE_OPCODE_TRANSMIT 0x0010 197 198 // 199 // Receive packet. 200 // 201 #define PXE_OPCODE_RECEIVE 0x0011 202 203 // last valid opcode: 204 #define PXE_OPCODE_VALID_MAX 0x0011 205 206 // 207 // Last valid PXE UNDI OpCode number. 208 // 209 #define PXE_OPCODE_LAST_VALID 0x0011 210 211 typedef PXE_UINT16 PXE_OPFLAGS; 212 213 #define PXE_OPFLAGS_NOT_USED 0x0000 214 215 //////////////////////////////////////// 216 // UNDI Get State 217 // 218 219 // No OpFlags 220 221 //////////////////////////////////////// 222 // UNDI Start 223 // 224 225 // No OpFlags 226 227 //////////////////////////////////////// 228 // UNDI Stop 229 // 230 231 // No OpFlags 232 233 //////////////////////////////////////// 234 // UNDI Get Init Info 235 // 236 237 // No Opflags 238 239 //////////////////////////////////////// 240 // UNDI Get Config Info 241 // 242 243 // No Opflags 244 245 //////////////////////////////////////// 246 // UNDI Initialize 247 // 248 249 #define PXE_OPFLAGS_INITIALIZE_CABLE_DETECT_MASK 0x0001 250 #define PXE_OPFLAGS_INITIALIZE_DETECT_CABLE 0x0000 251 #define PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE 0x0001 252 253 //////////////////////////////////////// 254 // UNDI Reset 255 // 256 257 #define PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS 0x0001 258 #define PXE_OPFLAGS_RESET_DISABLE_FILTERS 0x0002 259 260 //////////////////////////////////////// 261 // UNDI Shutdown 262 // 263 264 // No OpFlags 265 266 //////////////////////////////////////// 267 // UNDI Interrupt Enables 268 // 269 270 // 271 // Select whether to enable or disable external interrupt signals. 272 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPFLAGS. 273 // 274 #define PXE_OPFLAGS_INTERRUPT_OPMASK 0xC000 275 #define PXE_OPFLAGS_INTERRUPT_ENABLE 0x8000 276 #define PXE_OPFLAGS_INTERRUPT_DISABLE 0x4000 277 #define PXE_OPFLAGS_INTERRUPT_READ 0x0000 278 279 // 280 // Enable receive interrupts. An external interrupt will be generated 281 // after a complete non-error packet has been received. 282 // 283 #define PXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001 284 285 // 286 // Enable transmit interrupts. An external interrupt will be generated 287 // after a complete non-error packet has been transmitted. 288 // 289 #define PXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002 290 291 // 292 // Enable command interrupts. An external interrupt will be generated 293 // when command execution stops. 294 // 295 #define PXE_OPFLAGS_INTERRUPT_COMMAND 0x0004 296 297 // 298 // Generate software interrupt. Setting this bit generates an external 299 // interrupt, if it is supported by the hardware. 300 // 301 #define PXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008 302 303 //////////////////////////////////////// 304 // UNDI Receive Filters 305 // 306 307 // 308 // Select whether to enable or disable receive filters. 309 // Setting both enable and disable will return PXE_STATCODE_INVALID_OPCODE. 310 // 311 #define PXE_OPFLAGS_RECEIVE_FILTER_OPMASK 0xC000 312 #define PXE_OPFLAGS_RECEIVE_FILTER_ENABLE 0x8000 313 #define PXE_OPFLAGS_RECEIVE_FILTER_DISABLE 0x4000 314 #define PXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000 315 316 // 317 // To reset the contents of the multicast MAC address filter list, 318 // set this OpFlag: 319 // 320 #define PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST 0x2000 321 322 // 323 // Enable unicast packet receiving. Packets sent to the current station 324 // MAC address will be received. 325 // 326 #define PXE_OPFLAGS_RECEIVE_FILTER_UNICAST 0x0001 327 328 // 329 // Enable broadcast packet receiving. Packets sent to the broadcast 330 // MAC address will be received. 331 // 332 #define PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST 0x0002 333 334 // 335 // Enable filtered multicast packet receiving. Packets sent to any 336 // of the multicast MAC addresses in the multicast MAC address filter 337 // list will be received. If the filter list is empty, no multicast 338 // 339 #define PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004 340 341 // 342 // Enable promiscuous packet receiving. All packets will be received. 343 // 344 #define PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008 345 346 // 347 // Enable promiscuous multicast packet receiving. All multicast 348 // packets will be received. 349 // 350 #define PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010 351 352 //////////////////////////////////////// 353 // UNDI Station Address 354 // 355 356 #define PXE_OPFLAGS_STATION_ADDRESS_READ 0x0000 357 #define PXE_OPFLAGS_STATION_ADDRESS_RESET 0x0001 358 359 //////////////////////////////////////// 360 // UNDI Statistics 361 // 362 363 #define PXE_OPFLAGS_STATISTICS_READ 0x0000 364 #define PXE_OPFLAGS_STATISTICS_RESET 0x0001 365 366 //////////////////////////////////////// 367 // UNDI MCast IP to MAC 368 // 369 370 // 371 // Identify the type of IP address in the CPB. 372 // 373 #define PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMASK 0x0003 374 #define PXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000 375 #define PXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001 376 377 //////////////////////////////////////// 378 // UNDI NvData 379 // 380 381 // 382 // Select the type of non-volatile data operation. 383 // 384 #define PXE_OPFLAGS_NVDATA_OPMASK 0x0001 385 #define PXE_OPFLAGS_NVDATA_READ 0x0000 386 #define PXE_OPFLAGS_NVDATA_WRITE 0x0001 387 388 //////////////////////////////////////// 389 // UNDI Get Status 390 // 391 392 // 393 // Return current interrupt status. This will also clear any interrupts 394 // that are currently set. This can be used in a polling routine. The 395 // interrupt flags are still set and cleared even when the interrupts 396 // are disabled. 397 // 398 #define PXE_OPFLAGS_GET_INTERRUPT_STATUS 0x0001 399 400 // 401 // Return list of transmitted buffers for recycling. Transmit buffers 402 // must not be changed or unallocated until they have recycled. After 403 // issuing a transmit command, wait for a transmit complete interrupt. 404 // When a transmit complete interrupt is received, read the transmitted 405 // buffers. Do not plan on getting one buffer per interrupt. Some 406 // NICs and UNDIs may transmit multiple buffers per interrupt. 407 // 408 #define PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS 0x0002 409 410 //////////////////////////////////////// 411 // UNDI Fill Header 412 // 413 414 #define PXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001 415 #define PXE_OPFLAGS_FILL_HEADER_FRAGMENTED 0x0001 416 #define PXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000 417 418 //////////////////////////////////////// 419 // UNDI Transmit 420 // 421 422 // 423 // S/W UNDI only. Return after the packet has been transmitted. A 424 // transmit complete interrupt will still be generated and the transmit 425 // buffer will have to be recycled. 426 // 427 #define PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMASK 0x0001 428 #define PXE_OPFLAGS_TRANSMIT_BLOCK 0x0001 429 #define PXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000 430 431 // 432 // 433 // 434 #define PXE_OPFLAGS_TRANSMIT_OPMASK 0x0002 435 #define PXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002 436 #define PXE_OPFLAGS_TRANSMIT_WHOLE 0x0000 437 438 //////////////////////////////////////// 439 // UNDI Receive 440 // 441 442 // No OpFlags 443 444 typedef PXE_UINT16 PXE_STATFLAGS; 445 446 #define PXE_STATFLAGS_INITIALIZE 0x0000 447 448 //////////////////////////////////////// 449 // Common StatFlags that can be returned by all commands. 450 // 451 452 // 453 // The COMMAND_COMPLETE and COMMAND_FAILED status flags must be 454 // implemented by all UNDIs. COMMAND_QUEUED is only needed by UNDIs 455 // that support command queuing. 456 // 457 #define PXE_STATFLAGS_STATUS_MASK 0xC000 458 #define PXE_STATFLAGS_COMMAND_COMPLETE 0xC000 459 #define PXE_STATFLAGS_COMMAND_FAILED 0x8000 460 #define PXE_STATFLAGS_COMMAND_QUEUED 0x4000 461 //#define PXE_STATFLAGS_INITIALIZE 0x0000 462 463 #define PXE_STATFLAGS_DB_WRITE_TRUNCATED 0x2000 464 465 //////////////////////////////////////// 466 // UNDI Get State 467 // 468 469 #define PXE_STATFLAGS_GET_STATE_MASK 0x0003 470 #define PXE_STATFLAGS_GET_STATE_INITIALIZED 0x0002 471 #define PXE_STATFLAGS_GET_STATE_STARTED 0x0001 472 #define PXE_STATFLAGS_GET_STATE_STOPPED 0x0000 473 474 //////////////////////////////////////// 475 // UNDI Start 476 // 477 478 // No additional StatFlags 479 480 //////////////////////////////////////// 481 // UNDI Get Init Info 482 // 483 484 #define PXE_STATFLAGS_CABLE_DETECT_MASK 0x0001 485 #define PXE_STATFLAGS_CABLE_DETECT_NOT_SUPPORTED 0x0000 486 #define PXE_STATFLAGS_CABLE_DETECT_SUPPORTED 0x0001 487 488 489 //////////////////////////////////////// 490 // UNDI Initialize 491 // 492 493 #define PXE_STATFLAGS_INITIALIZED_NO_MEDIA 0x0001 494 495 //////////////////////////////////////// 496 // UNDI Reset 497 // 498 499 #define PXE_STATFLAGS_RESET_NO_MEDIA 0x0001 500 501 //////////////////////////////////////// 502 // UNDI Shutdown 503 // 504 505 // No additional StatFlags 506 507 //////////////////////////////////////// 508 // UNDI Interrupt Enables 509 // 510 511 // 512 // If set, receive interrupts are enabled. 513 // 514 #define PXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001 515 516 // 517 // If set, transmit interrupts are enabled. 518 // 519 #define PXE_STATFLAGS_INTERRUPT_TRANSMIT 0x0002 520 521 // 522 // If set, command interrupts are enabled. 523 // 524 #define PXE_STATFLAGS_INTERRUPT_COMMAND 0x0004 525 526 527 //////////////////////////////////////// 528 // UNDI Receive Filters 529 // 530 531 // 532 // If set, unicast packets will be received. 533 // 534 #define PXE_STATFLAGS_RECEIVE_FILTER_UNICAST 0x0001 535 536 // 537 // If set, broadcast packets will be received. 538 // 539 #define PXE_STATFLAGS_RECEIVE_FILTER_BROADCAST 0x0002 540 541 // 542 // If set, multicast packets that match up with the multicast address 543 // filter list will be received. 544 // 545 #define PXE_STATFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST 0x0004 546 547 // 548 // If set, all packets will be received. 549 // 550 #define PXE_STATFLAGS_RECEIVE_FILTER_PROMISCUOUS 0x0008 551 552 // 553 // If set, all multicast packets will be received. 554 // 555 #define PXE_STATFLAGS_RECEIVE_FILTER_ALL_MULTICAST 0x0010 556 557 //////////////////////////////////////// 558 // UNDI Station Address 559 // 560 561 // No additional StatFlags 562 563 //////////////////////////////////////// 564 // UNDI Statistics 565 // 566 567 // No additional StatFlags 568 569 //////////////////////////////////////// 570 // UNDI MCast IP to MAC 571 // 572 573 // No additional StatFlags 574 575 //////////////////////////////////////// 576 // UNDI NvData 577 // 578 579 // No additional StatFlags 580 581 582 //////////////////////////////////////// 583 // UNDI Get Status 584 // 585 586 // 587 // Use to determine if an interrupt has occurred. 588 // 589 #define PXE_STATFLAGS_GET_STATUS_INTERRUPT_MASK 0x000F 590 #define PXE_STATFLAGS_GET_STATUS_NO_INTERRUPTS 0x0000 591 592 // 593 // If set, at least one receive interrupt occurred. 594 // 595 #define PXE_STATFLAGS_GET_STATUS_RECEIVE 0x0001 596 597 // 598 // If set, at least one transmit interrupt occurred. 599 // 600 #define PXE_STATFLAGS_GET_STATUS_TRANSMIT 0x0002 601 602 // 603 // If set, at least one command interrupt occurred. 604 // 605 #define PXE_STATFLAGS_GET_STATUS_COMMAND 0x0004 606 607 // 608 // If set, at least one software interrupt occurred. 609 // 610 #define PXE_STATFLAGS_GET_STATUS_SOFTWARE 0x0008 611 612 // 613 // This flag is set if the transmitted buffer queue is empty. This flag 614 // will be set if all transmitted buffer addresses get written into the DB. 615 // 616 #define PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY 0x0010 617 618 // 619 // This flag is set if no transmitted buffer addresses were written 620 // into the DB. (This could be because DBsize was too small.) 621 // 622 #define PXE_STATFLAGS_GET_STATUS_NO_TXBUFS_WRITTEN 0x0020 623 624 //////////////////////////////////////// 625 // UNDI Fill Header 626 // 627 628 // No additional StatFlags 629 630 //////////////////////////////////////// 631 // UNDI Transmit 632 // 633 634 // No additional StatFlags. 635 636 //////////////////////////////////////// 637 // UNDI Receive 638 // 639 640 // No additional StatFlags. 641 642 typedef PXE_UINT16 PXE_STATCODE; 643 644 #define PXE_STATCODE_INITIALIZE 0x0000 645 646 //////////////////////////////////////// 647 // Common StatCodes returned by all UNDI commands, UNDI protocol functions 648 // and BC protocol functions. 649 // 650 651 #define PXE_STATCODE_SUCCESS 0x0000 652 653 #define PXE_STATCODE_INVALID_CDB 0x0001 654 #define PXE_STATCODE_INVALID_CPB 0x0002 655 #define PXE_STATCODE_BUSY 0x0003 656 #define PXE_STATCODE_QUEUE_FULL 0x0004 657 #define PXE_STATCODE_ALREADY_STARTED 0x0005 658 #define PXE_STATCODE_NOT_STARTED 0x0006 659 #define PXE_STATCODE_NOT_SHUTDOWN 0x0007 660 #define PXE_STATCODE_ALREADY_INITIALIZED 0x0008 661 #define PXE_STATCODE_NOT_INITIALIZED 0x0009 662 #define PXE_STATCODE_DEVICE_FAILURE 0x000A 663 #define PXE_STATCODE_NVDATA_FAILURE 0x000B 664 #define PXE_STATCODE_UNSUPPORTED 0x000C 665 #define PXE_STATCODE_BUFFER_FULL 0x000D 666 #define PXE_STATCODE_INVALID_PARAMETER 0x000E 667 #define PXE_STATCODE_INVALID_UNDI 0x000F 668 #define PXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010 669 #define PXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011 670 #define PXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012 671 #define PXE_STATCODE_NO_DATA 0x0013 672 673 674 typedef PXE_UINT16 PXE_IFNUM; 675 676 // 677 // This interface number must be passed to the S/W UNDI Start command. 678 // 679 #define PXE_IFNUM_START 0x0000 680 681 // 682 // This interface number is returned by the S/W UNDI Get State and 683 // Start commands if information in the CDB, CPB or DB is invalid. 684 // 685 #define PXE_IFNUM_INVALID 0x0000 686 687 typedef PXE_UINT16 PXE_CONTROL; 688 689 // 690 // Setting this flag directs the UNDI to queue this command for later 691 // execution if the UNDI is busy and it supports command queuing. 692 // If queuing is not supported, a PXE_STATCODE_INVALID_CONTROL error 693 // is returned. If the queue is full, a PXE_STATCODE_CDB_QUEUE_FULL 694 // error is returned. 695 // 696 #define PXE_CONTROL_QUEUE_IF_BUSY 0x0002 697 698 // 699 // These two bit values are used to determine if there are more UNDI 700 // CDB structures following this one. If the link bit is set, there 701 // must be a CDB structure following this one. Execution will start 702 // on the next CDB structure as soon as this one completes successfully. 703 // If an error is generated by this command, execution will stop. 704 // 705 #define PXE_CONTROL_LINK 0x0001 706 #define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000 707 708 typedef PXE_UINT8 PXE_FRAME_TYPE; 709 710 #define PXE_FRAME_TYPE_NONE 0x00 711 #define PXE_FRAME_TYPE_UNICAST 0x01 712 #define PXE_FRAME_TYPE_BROADCAST 0x02 713 #define PXE_FRAME_TYPE_MULTICAST 0x03 714 #define PXE_FRAME_TYPE_PROMISCUOUS 0x04 715 716 typedef PXE_UINT32 PXE_IPV4; 717 718 typedef PXE_UINT32 PXE_IPV6[4]; 719 #define PXE_MAC_LENGTH 32 720 721 typedef PXE_UINT8 PXE_MAC_ADDR[PXE_MAC_LENGTH]; 722 723 typedef PXE_UINT8 PXE_IFTYPE; 724 typedef PXE_UINT16 PXE_MEDIA_PROTOCOL; 725 726 // 727 // This information is from the ARP section of RFC 1700. 728 // 729 // 1 Ethernet (10Mb) [JBP] 730 // 2 Experimental Ethernet (3Mb) [JBP] 731 // 3 Amateur Radio AX.25 [PXK] 732 // 4 Proteon ProNET Token Ring [JBP] 733 // 5 Chaos [GXP] 734 // 6 IEEE 802 Networks [JBP] 735 // 7 ARCNET [JBP] 736 // 8 Hyperchannel [JBP] 737 // 9 Lanstar [TU] 738 // 10 Autonet Short Address [MXB1] 739 // 11 LocalTalk [JKR1] 740 // 12 LocalNet (IBM PCNet or SYTEK LocalNET) [JXM] 741 // 13 Ultra link [RXD2] 742 // 14 SMDS [GXC1] 743 // 15 Frame Relay [AGM] 744 // 16 Asynchronous Transmission Mode (ATM) [JXB2] 745 // 17 HDLC [JBP] 746 // 18 Fibre Channel [Yakov Rekhter] 747 // 19 Asynchronous Transmission Mode (ATM) [Mark Laubach] 748 // 20 Serial Line [JBP] 749 // 21 Asynchronous Transmission Mode (ATM) [MXB1] 750 // 751 752 #define PXE_IFTYPE_ETHERNET 0x01 753 #define PXE_IFTYPE_TOKENRING 0x04 754 #define PXE_IFTYPE_FIBRE_CHANNEL 0x12 755 756 typedef struct s_pxe_hw_undi { 757 PXE_UINT32 Signature; // PXE_ROMID_SIGNATURE 758 PXE_UINT8 Len; // sizeof(PXE_HW_UNDI) 759 PXE_UINT8 Fudge; // makes 8-bit cksum equal zero 760 PXE_UINT8 Rev; // PXE_ROMID_REV 761 PXE_UINT8 IFcnt; // physical connector count 762 PXE_UINT8 MajorVer; // PXE_ROMID_MAJORVER 763 PXE_UINT8 MinorVer; // PXE_ROMID_MINORVER 764 PXE_UINT16 reserved; // zero, not used 765 PXE_UINT32 Implementation; // implementation flags 766 // reserved // vendor use 767 // PXE_UINT32 Status; // status port 768 // PXE_UINT32 Command; // command port 769 // PXE_UINT64 CDBaddr; // CDB address port 770 } PXE_HW_UNDI; 771 772 // 773 // Status port bit definitions 774 // 775 776 // 777 // UNDI operation state 778 // 779 #define PXE_HWSTAT_STATE_MASK 0xC0000000 780 #define PXE_HWSTAT_BUSY 0xC0000000 781 #define PXE_HWSTAT_INITIALIZED 0x80000000 782 #define PXE_HWSTAT_STARTED 0x40000000 783 #define PXE_HWSTAT_STOPPED 0x00000000 784 785 // 786 // If set, last command failed 787 // 788 #define PXE_HWSTAT_COMMAND_FAILED 0x20000000 789 790 // 791 // If set, identifies enabled receive filters 792 // 793 #define PXE_HWSTAT_PROMISCUOUS_MULTICAST_RX_ENABLED 0x00001000 794 #define PXE_HWSTAT_PROMISCUOUS_RX_ENABLED 0x00000800 795 #define PXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400 796 #define PXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200 797 #define PXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100 798 799 // 800 // If set, identifies enabled external interrupts 801 // 802 #define PXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080 803 #define PXE_HWSTAT_TX_COMPLETE_INT_ENABLED 0x00000040 804 #define PXE_HWSTAT_PACKET_RX_INT_ENABLED 0x00000020 805 #define PXE_HWSTAT_CMD_COMPLETE_INT_ENABLED 0x00000010 806 807 // 808 // If set, identifies pending interrupts 809 // 810 #define PXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008 811 #define PXE_HWSTAT_TX_COMPLETE_INT_PENDING 0x00000004 812 #define PXE_HWSTAT_PACKET_RX_INT_PENDING 0x00000002 813 #define PXE_HWSTAT_CMD_COMPLETE_INT_PENDING 0x00000001 814 815 // 816 // Command port definitions 817 // 818 819 // 820 // If set, CDB identified in CDBaddr port is given to UNDI. 821 // If not set, other bits in this word will be processed. 822 // 823 #define PXE_HWCMD_ISSUE_COMMAND 0x80000000 824 #define PXE_HWCMD_INTS_AND_FILTS 0x00000000 825 826 // 827 // Use these to enable/disable receive filters. 828 // 829 #define PXE_HWCMD_PROMISCUOUS_MULTICAST_RX_ENABLE 0x00001000 830 #define PXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800 831 #define PXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400 832 #define PXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200 833 #define PXE_HWCMD_UNICAST_RX_ENABLE 0x00000100 834 835 // 836 // Use these to enable/disable external interrupts 837 // 838 #define PXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080 839 #define PXE_HWCMD_TX_COMPLETE_INT_ENABLE 0x00000040 840 #define PXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020 841 #define PXE_HWCMD_CMD_COMPLETE_INT_ENABLE 0x00000010 842 843 // 844 // Use these to clear pending external interrupts 845 // 846 #define PXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008 847 #define PXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004 848 #define PXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002 849 #define PXE_HWCMD_CLEAR_CMD_COMPLETE_INT 0x00000001 850 851 typedef struct s_pxe_sw_undi { 852 PXE_UINT32 Signature; // PXE_ROMID_SIGNATURE 853 PXE_UINT8 Len; // sizeof(PXE_SW_UNDI) 854 PXE_UINT8 Fudge; // makes 8-bit cksum zero 855 PXE_UINT8 Rev; // PXE_ROMID_REV 856 PXE_UINT8 IFcnt; // physical connector count 857 PXE_UINT8 MajorVer; // PXE_ROMID_MAJORVER 858 PXE_UINT8 MinorVer; // PXE_ROMID_MINORVER 859 PXE_UINT16 reserved1; // zero, not used 860 PXE_UINT32 Implementation; // Implementation flags 861 PXE_UINT64 EntryPoint; // API entry point 862 PXE_UINT8 reserved2[3]; // zero, not used 863 PXE_UINT8 BusCnt; // number of bustypes supported 864 PXE_UINT32 BusType[1]; // list of supported bustypes 865 } PXE_SW_UNDI; 866 867 typedef union u_pxe_undi { 868 PXE_HW_UNDI hw; 869 PXE_SW_UNDI sw; 870 } PXE_UNDI; 871 872 // 873 // Signature of !PXE structure 874 // 875 #define PXE_ROMID_SIGNATURE PXE_BUSTYPE('!', 'P', 'X', 'E') 876 877 // 878 // !PXE structure format revision 879 // 880 #define PXE_ROMID_REV 0x02 881 882 // 883 // UNDI command interface revision. These are the values that get sent 884 // in option 94 (Client Network Interface Identifier) in the DHCP Discover 885 // and PXE Boot Server Request packets. 886 // 887 #define PXE_ROMID_MAJORVER 0x03 888 #define PXE_ROMID_MINORVER 0x00 889 890 // 891 // Implementation flags 892 // 893 #define PXE_ROMID_IMP_HW_UNDI 0x80000000 894 #define PXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000 895 #define PXE_ROMID_IMP_64BIT_DEVICE 0x00010000 896 #define PXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000 897 #define PXE_ROMID_IMP_CMD_LINK_SUPPORTED 0x00004000 898 #define PXE_ROMID_IMP_CMD_QUEUE_SUPPORTED 0x00002000 899 #define PXE_ROMID_IMP_MULTI_FRAME_SUPPORTED 0x00001000 900 #define PXE_ROMID_IMP_NVDATA_SUPPORT_MASK 0x00000C00 901 #define PXE_ROMID_IMP_NVDATA_BULK_WRITABLE 0x00000C00 902 #define PXE_ROMID_IMP_NVDATA_SPARSE_WRITABLE 0x00000800 903 #define PXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400 904 #define PXE_ROMID_IMP_NVDATA_NOT_AVAILABLE 0x00000000 905 #define PXE_ROMID_IMP_STATISTICS_SUPPORTED 0x00000200 906 #define PXE_ROMID_IMP_STATION_ADDR_SETTABLE 0x00000100 907 #define PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED 0x00000080 908 #define PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED 0x00000040 909 #define PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED 0x00000020 910 #define PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED 0x00000010 911 #define PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED 0x00000008 912 #define PXE_ROMID_IMP_TX_COMPLETE_INT_SUPPORTED 0x00000004 913 #define PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED 0x00000002 914 #define PXE_ROMID_IMP_CMD_COMPLETE_INT_SUPPORTED 0x00000001 915 916 917 typedef struct s_pxe_cdb { 918 PXE_OPCODE OpCode; 919 PXE_OPFLAGS OpFlags; 920 PXE_UINT16 CPBsize; 921 PXE_UINT16 DBsize; 922 UINT64 CPBaddr; 923 UINT64 DBaddr; 924 PXE_STATCODE StatCode; 925 PXE_STATFLAGS StatFlags; 926 PXE_UINT16 IFnum; 927 PXE_CONTROL Control; 928 } PXE_CDB; 929 930 931 typedef union u_pxe_ip_addr { 932 PXE_IPV6 IPv6; 933 PXE_IPV4 IPv4; 934 } PXE_IP_ADDR; 935 936 typedef union pxe_device { 937 // 938 // PCI and PC Card NICs are both identified using bus, device 939 // and function numbers. For PC Card, this may require PC 940 // Card services to be loaded in the BIOS or preboot 941 // environment. 942 // 943 struct { 944 // 945 // See S/W UNDI ROMID structure definition for PCI and 946 // PCC BusType definitions. 947 // 948 PXE_UINT32 BusType; 949 950 // 951 // Bus, device & function numbers that locate this device. 952 // 953 PXE_UINT16 Bus; 954 PXE_UINT8 Device; 955 PXE_UINT8 Function; 956 } PCI, PCC; 957 958 // 959 // %%TBD - More information is needed about enumerating 960 // USB and 1394 devices. 961 // 962 struct { 963 PXE_UINT32 BusType; 964 PXE_UINT32 tdb; 965 } USB, _1394; 966 } PXE_DEVICE; 967 968 // cpb and db definitions 969 970 #define MAX_PCI_CONFIG_LEN 64 // # of dwords 971 #define MAX_EEPROM_LEN 128 // #of dwords 972 #define MAX_XMIT_BUFFERS 32 // recycling Q length for xmit_done 973 #define MAX_MCAST_ADDRESS_CNT 8 974 975 typedef struct s_pxe_cpb_start { 976 // 977 // PXE_VOID Delay(PXE_UINT64 microseconds); 978 // 979 // UNDI will never request a delay smaller than 10 microseconds 980 // and will always request delays in increments of 10 microseconds. 981 // The Delay() CallBack routine must delay between n and n + 10 982 // microseconds before returning control to the UNDI. 983 // 984 // This field cannot be set to zero. 985 // 986 PXE_UINT64 Delay; 987 988 // 989 // PXE_VOID Block(PXE_UINT32 enable); 990 // 991 // UNDI may need to block multi-threaded/multi-processor access to 992 // critical code sections when programming or accessing the network 993 // device. To this end, a blocking service is needed by the UNDI. 994 // When UNDI needs a block, it will call Block() passing a non-zero 995 // value. When UNDI no longer needs a block, it will call Block() 996 // with a zero value. When called, if the Block() is already enabled, 997 // do not return control to the UNDI until the previous Block() is 998 // disabled. 999 // 1000 // This field cannot be set to zero. 1001 // 1002 PXE_UINT64 Block; 1003 1004 // 1005 // PXE_VOID Virt2Phys(PXE_UINT64 virtual, PXE_UINT64 physical_ptr); 1006 // 1007 // UNDI will pass the virtual address of a buffer and the virtual 1008 // address of a 64-bit physical buffer. Convert the virtual address 1009 // to a physical address and write the result to the physical address 1010 // buffer. If virtual and physical addresses are the same, just 1011 // copy the virtual address to the physical address buffer. 1012 // 1013 // This field can be set to zero if virtual and physical addresses 1014 // are equal. 1015 // 1016 PXE_UINT64 Virt2Phys; 1017 // 1018 // PXE_VOID Mem_IO(PXE_UINT8 read_write, PXE_UINT8 len, PXE_UINT64 port, 1019 // PXE_UINT64 buf_addr); 1020 // 1021 // UNDI will read or write the device io space using this call back 1022 // function. It passes the number of bytes as the len parameter and it 1023 // will be either 1,2,4 or 8. 1024 // 1025 // This field can not be set to zero. 1026 // 1027 PXE_UINT64 Mem_IO; 1028 } PXE_CPB_START; 1029 1030 #define PXE_DELAY_MILLISECOND 1000 1031 #define PXE_DELAY_SECOND 1000000 1032 #define PXE_IO_READ 0 1033 #define PXE_IO_WRITE 1 1034 #define PXE_MEM_READ 2 1035 #define PXE_MEM_WRITE 4 1036 1037 1038 typedef struct s_pxe_db_get_init_info { 1039 // 1040 // Minimum length of locked memory buffer that must be given to 1041 // the Initialize command. Giving UNDI more memory will generally 1042 // give better performance. 1043 // 1044 // If MemoryRequired is zero, the UNDI does not need and will not 1045 // use system memory to receive and transmit packets. 1046 // 1047 PXE_UINT32 MemoryRequired; 1048 1049 // 1050 // Maximum frame data length for Tx/Rx excluding the media header. 1051 // 1052 PXE_UINT32 FrameDataLen; 1053 1054 // 1055 // Supported link speeds are in units of mega bits. Common ethernet 1056 // values are 10, 100 and 1000. Unused LinkSpeeds[] entries are zero 1057 // filled. 1058 // 1059 PXE_UINT32 LinkSpeeds[4]; 1060 1061 // 1062 // Number of non-volatile storage items. 1063 // 1064 PXE_UINT32 NvCount; 1065 1066 // 1067 // Width of non-volatile storage item in bytes. 0, 1, 2 or 4 1068 // 1069 PXE_UINT16 NvWidth; 1070 1071 // 1072 // Media header length. This is the typical media header length for 1073 // this UNDI. This information is needed when allocating receive 1074 // and transmit buffers. 1075 // 1076 PXE_UINT16 MediaHeaderLen; 1077 1078 // 1079 // Number of bytes in the NIC hardware (MAC) address. 1080 // 1081 PXE_UINT16 HWaddrLen; 1082 1083 // 1084 // Maximum number of multicast MAC addresses in the multicast 1085 // MAC address filter list. 1086 // 1087 PXE_UINT16 MCastFilterCnt; 1088 1089 // 1090 // Default number and size of transmit and receive buffers that will 1091 // be allocated by the UNDI. If MemoryRequired is non-zero, this 1092 // allocation will come out of the memory buffer given to the Initialize 1093 // command. If MemoryRequired is zero, this allocation will come out of 1094 // memory on the NIC. 1095 // 1096 PXE_UINT16 TxBufCnt; 1097 PXE_UINT16 TxBufSize; 1098 PXE_UINT16 RxBufCnt; 1099 PXE_UINT16 RxBufSize; 1100 1101 // 1102 // Hardware interface types defined in the Assigned Numbers RFC 1103 // and used in DHCP and ARP packets. 1104 // See the PXE_IFTYPE typedef and PXE_IFTYPE_xxx macros. 1105 // 1106 PXE_UINT8 IFtype; 1107 1108 // 1109 // Supported duplex. See PXE_DUPLEX_xxxxx #defines below. 1110 // 1111 PXE_UINT8 Duplex; 1112 1113 // 1114 // Supported loopback options. See PXE_LOOPBACK_xxxxx #defines below. 1115 // 1116 PXE_UINT8 LoopBack; 1117 } PXE_DB_GET_INIT_INFO; 1118 1119 #define PXE_MAX_TXRX_UNIT_ETHER 1500 1120 1121 #define PXE_HWADDR_LEN_ETHER 0x0006 1122 #define PXE_MAC_HEADER_LEN_ETHER 0x000E 1123 1124 #define PXE_DUPLEX_ENABLE_FULL_SUPPORTED 1 1125 #define PXE_DUPLEX_FORCE_FULL_SUPPORTED 2 1126 1127 #define PXE_LOOPBACK_INTERNAL_SUPPORTED 1 1128 #define PXE_LOOPBACK_EXTERNAL_SUPPORTED 2 1129 1130 1131 typedef struct s_pxe_pci_config_info { 1132 // 1133 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union. 1134 // For PCI bus devices, this field is set to PXE_BUSTYPE_PCI. 1135 // 1136 PXE_UINT32 BusType; 1137 1138 // 1139 // This identifies the PCI network device that this UNDI interface 1140 // is bound to. 1141 // 1142 PXE_UINT16 Bus; 1143 PXE_UINT8 Device; 1144 PXE_UINT8 Function; 1145 1146 // 1147 // This is a copy of the PCI configuration space for this 1148 // network device. 1149 // 1150 union { 1151 PXE_UINT8 Byte[256]; 1152 PXE_UINT16 Word[128]; 1153 PXE_UINT32 Dword[64]; 1154 } Config; 1155 } PXE_PCI_CONFIG_INFO; 1156 1157 1158 typedef struct s_pxe_pcc_config_info { 1159 // 1160 // This is the flag field for the PXE_DB_GET_CONFIG_INFO union. 1161 // For PCC bus devices, this field is set to PXE_BUSTYPE_PCC. 1162 // 1163 PXE_UINT32 BusType; 1164 1165 // 1166 // This identifies the PCC network device that this UNDI interface 1167 // is bound to. 1168 // 1169 PXE_UINT16 Bus; 1170 PXE_UINT8 Device; 1171 PXE_UINT8 Function; 1172 1173 // 1174 // This is a copy of the PCC configuration space for this 1175 // network device. 1176 // 1177 union { 1178 PXE_UINT8 Byte[256]; 1179 PXE_UINT16 Word[128]; 1180 PXE_UINT32 Dword[64]; 1181 } Config; 1182 } PXE_PCC_CONFIG_INFO; 1183 1184 1185 typedef struct s_pxe_usb_config_info { 1186 PXE_UINT32 BusType; 1187 // %%TBD What should we return here... 1188 } PXE_USB_CONFIG_INFO; 1189 1190 1191 typedef struct s_pxe_1394_config_info { 1192 PXE_UINT32 BusType; 1193 // %%TBD What should we return here... 1194 } PXE_1394_CONFIG_INFO; 1195 1196 1197 typedef union u_pxe_db_get_config_info { 1198 PXE_PCI_CONFIG_INFO pci; 1199 PXE_PCC_CONFIG_INFO pcc; 1200 PXE_USB_CONFIG_INFO usb; 1201 PXE_1394_CONFIG_INFO _1394; 1202 } PXE_DB_GET_CONFIG_INFO; 1203 1204 1205 typedef struct s_pxe_cpb_initialize { 1206 // 1207 // Address of first (lowest) byte of the memory buffer. This buffer must 1208 // be in contiguous physical memory and cannot be swapped out. The UNDI 1209 // will be using this for transmit and receive buffering. 1210 // 1211 PXE_UINT64 MemoryAddr; 1212 1213 // 1214 // MemoryLength must be greater than or equal to MemoryRequired 1215 // returned by the Get Init Info command. 1216 // 1217 PXE_UINT32 MemoryLength; 1218 1219 // 1220 // Desired link speed in Mbit/sec. Common ethernet values are 10, 100 1221 // and 1000. Setting a value of zero will auto-detect and/or use the 1222 // default link speed (operation depends on UNDI/NIC functionality). 1223 // 1224 PXE_UINT32 LinkSpeed; 1225 1226 // 1227 // Suggested number and size of receive and transmit buffers to 1228 // allocate. If MemoryAddr and MemoryLength are non-zero, this 1229 // allocation comes out of the supplied memory buffer. If MemoryAddr 1230 // and MemoryLength are zero, this allocation comes out of memory 1231 // on the NIC. 1232 // 1233 // If these fields are set to zero, the UNDI will allocate buffer 1234 // counts and sizes as it sees fit. 1235 // 1236 PXE_UINT16 TxBufCnt; 1237 PXE_UINT16 TxBufSize; 1238 PXE_UINT16 RxBufCnt; 1239 PXE_UINT16 RxBufSize; 1240 1241 // 1242 // The following configuration parameters are optional and must be zero 1243 // to use the default values. 1244 // 1245 PXE_UINT8 Duplex; 1246 1247 PXE_UINT8 LoopBack; 1248 } PXE_CPB_INITIALIZE; 1249 1250 1251 #define PXE_DUPLEX_DEFAULT 0x00 1252 #define PXE_FORCE_FULL_DUPLEX 0x01 1253 #define PXE_ENABLE_FULL_DUPLEX 0x02 1254 1255 #define LOOPBACK_NORMAL 0 1256 #define LOOPBACK_INTERNAL 1 1257 #define LOOPBACK_EXTERNAL 2 1258 1259 1260 typedef struct s_pxe_db_initialize { 1261 // 1262 // Actual amount of memory used from the supplied memory buffer. This 1263 // may be less that the amount of memory suppllied and may be zero if 1264 // the UNDI and network device do not use external memory buffers. 1265 // 1266 // Memory used by the UNDI and network device is allocated from the 1267 // lowest memory buffer address. 1268 // 1269 PXE_UINT32 MemoryUsed; 1270 1271 // 1272 // Actual number and size of receive and transmit buffers that were 1273 // allocated. 1274 // 1275 PXE_UINT16 TxBufCnt; 1276 PXE_UINT16 TxBufSize; 1277 PXE_UINT16 RxBufCnt; 1278 PXE_UINT16 RxBufSize; 1279 } PXE_DB_INITIALIZE; 1280 1281 1282 typedef struct s_pxe_cpb_receive_filters { 1283 // 1284 // List of multicast MAC addresses. This list, if present, will 1285 // replace the existing multicast MAC address filter list. 1286 // 1287 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]; 1288 } PXE_CPB_RECEIVE_FILTERS; 1289 1290 1291 typedef struct s_pxe_db_receive_filters { 1292 // 1293 // Filtered multicast MAC address list. 1294 // 1295 PXE_MAC_ADDR MCastList[MAX_MCAST_ADDRESS_CNT]; 1296 } PXE_DB_RECEIVE_FILTERS; 1297 1298 1299 typedef struct s_pxe_cpb_station_address { 1300 // 1301 // If supplied and supported, the current station MAC address 1302 // will be changed. 1303 // 1304 PXE_MAC_ADDR StationAddr; 1305 } PXE_CPB_STATION_ADDRESS; 1306 1307 1308 typedef struct s_pxe_dpb_station_address { 1309 // 1310 // Current station MAC address. 1311 // 1312 PXE_MAC_ADDR StationAddr; 1313 1314 // 1315 // Station broadcast MAC address. 1316 // 1317 PXE_MAC_ADDR BroadcastAddr; 1318 1319 // 1320 // Permanent station MAC address. 1321 // 1322 PXE_MAC_ADDR PermanentAddr; 1323 } PXE_DB_STATION_ADDRESS; 1324 1325 1326 typedef struct s_pxe_db_statistics { 1327 // 1328 // Bit field identifying what statistic data is collected by the 1329 // UNDI/NIC. 1330 // If bit 0x00 is set, Data[0x00] is collected. 1331 // If bit 0x01 is set, Data[0x01] is collected. 1332 // If bit 0x20 is set, Data[0x20] is collected. 1333 // If bit 0x21 is set, Data[0x21] is collected. 1334 // Etc. 1335 // 1336 PXE_UINT64 Supported; 1337 1338 // 1339 // Statistic data. 1340 // 1341 PXE_UINT64 Data[64]; 1342 } PXE_DB_STATISTICS; 1343 1344 // 1345 // Total number of frames received. Includes frames with errors and 1346 // dropped frames. 1347 // 1348 #define PXE_STATISTICS_RX_TOTAL_FRAMES 0x00 1349 1350 // 1351 // Number of valid frames received and copied into receive buffers. 1352 // 1353 #define PXE_STATISTICS_RX_GOOD_FRAMES 0x01 1354 1355 // 1356 // Number of frames below the minimum length for the media. 1357 // This would be <64 for ethernet. 1358 // 1359 #define PXE_STATISTICS_RX_UNDERSIZE_FRAMES 0x02 1360 1361 // 1362 // Number of frames longer than the maxminum length for the 1363 // media. This would be >1500 for ethernet. 1364 // 1365 #define PXE_STATISTICS_RX_OVERSIZE_FRAMES 0x03 1366 1367 // 1368 // Valid frames that were dropped because receive buffers were full. 1369 // 1370 #define PXE_STATISTICS_RX_DROPPED_FRAMES 0x04 1371 1372 // 1373 // Number of valid unicast frames received and not dropped. 1374 // 1375 #define PXE_STATISTICS_RX_UNICAST_FRAMES 0x05 1376 1377 // 1378 // Number of valid broadcast frames received and not dropped. 1379 // 1380 #define PXE_STATISTICS_RX_BROADCAST_FRAMES 0x06 1381 1382 // 1383 // Number of valid mutlicast frames received and not dropped. 1384 // 1385 #define PXE_STATISTICS_RX_MULTICAST_FRAMES 0x07 1386 1387 // 1388 // Number of frames w/ CRC or alignment errors. 1389 // 1390 #define PXE_STATISTICS_RX_CRC_ERROR_FRAMES 0x08 1391 1392 // 1393 // Total number of bytes received. Includes frames with errors 1394 // and dropped frames. 1395 // 1396 #define PXE_STATISTICS_RX_TOTAL_BYTES 0x09 1397 1398 // 1399 // Transmit statistics. 1400 // 1401 #define PXE_STATISTICS_TX_TOTAL_FRAMES 0x0A 1402 #define PXE_STATISTICS_TX_GOOD_FRAMES 0x0B 1403 #define PXE_STATISTICS_TX_UNDERSIZE_FRAMES 0x0C 1404 #define PXE_STATISTICS_TX_OVERSIZE_FRAMES 0x0D 1405 #define PXE_STATISTICS_TX_DROPPED_FRAMES 0x0E 1406 #define PXE_STATISTICS_TX_UNICAST_FRAMES 0x0F 1407 #define PXE_STATISTICS_TX_BROADCAST_FRAMES 0x10 1408 #define PXE_STATISTICS_TX_MULTICAST_FRAMES 0x11 1409 #define PXE_STATISTICS_TX_CRC_ERROR_FRAMES 0x12 1410 #define PXE_STATISTICS_TX_TOTAL_BYTES 0x13 1411 1412 // 1413 // Number of collisions detection on this subnet. 1414 // 1415 #define PXE_STATISTICS_COLLISIONS 0x14 1416 1417 // 1418 // Number of frames destined for unsupported protocol. 1419 // 1420 #define PXE_STATISTICS_UNSUPPORTED_PROTOCOL 0x15 1421 1422 1423 typedef struct s_pxe_cpb_mcast_ip_to_mac { 1424 // 1425 // Multicast IP address to be converted to multicast MAC address. 1426 // 1427 PXE_IP_ADDR IP; 1428 } PXE_CPB_MCAST_IP_TO_MAC; 1429 1430 1431 typedef struct s_pxe_db_mcast_ip_to_mac { 1432 // 1433 // Multicast MAC address. 1434 // 1435 PXE_MAC_ADDR MAC; 1436 } PXE_DB_MCAST_IP_TO_MAC; 1437 1438 1439 typedef struct s_pxe_cpb_nvdata_sparse { 1440 // 1441 // NvData item list. Only items in this list will be updated. 1442 // 1443 struct { 1444 // Non-volatile storage address to be changed. 1445 PXE_UINT32 Addr; 1446 1447 // Data item to write into above storage address. 1448 1449 union { 1450 PXE_UINT8 Byte; 1451 PXE_UINT16 Word; 1452 PXE_UINT32 Dword; 1453 } Data; 1454 } Item[MAX_EEPROM_LEN]; 1455 } PXE_CPB_NVDATA_SPARSE; 1456 1457 1458 // 1459 // When using bulk update, the size of the CPB structure must be 1460 // the same size as the non-volatile NIC storage. 1461 // 1462 typedef union u_pxe_cpb_nvdata_bulk { 1463 // 1464 // Array of byte-wide data items. 1465 // 1466 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2]; 1467 1468 // 1469 // Array of word-wide data items. 1470 // 1471 PXE_UINT16 Word[MAX_EEPROM_LEN << 1]; 1472 1473 // 1474 // Array of dword-wide data items. 1475 // 1476 PXE_UINT32 Dword[MAX_EEPROM_LEN]; 1477 } PXE_CPB_NVDATA_BULK; 1478 1479 typedef struct s_pxe_db_nvdata { 1480 1481 // Arrays of data items from non-volatile storage. 1482 1483 union { 1484 // 1485 // Array of byte-wide data items. 1486 // 1487 PXE_UINT8 Byte[MAX_EEPROM_LEN << 2]; 1488 1489 // 1490 // Array of word-wide data items. 1491 // 1492 PXE_UINT16 Word[MAX_EEPROM_LEN << 1]; 1493 1494 // Array of dword-wide data items. 1495 1496 PXE_UINT32 Dword[MAX_EEPROM_LEN]; 1497 } Data; 1498 } PXE_DB_NVDATA; 1499 1500 1501 typedef struct s_pxe_db_get_status { 1502 // 1503 // Length of next receive frame (header + data). If this is zero, 1504 // there is no next receive frame available. 1505 // 1506 PXE_UINT32 RxFrameLen; 1507 1508 // 1509 // Reserved, set to zero. 1510 // 1511 PXE_UINT32 reserved; 1512 1513 // 1514 // Addresses of transmitted buffers that need to be recycled. 1515 // 1516 PXE_UINT64 TxBuffer[MAX_XMIT_BUFFERS]; 1517 } PXE_DB_GET_STATUS; 1518 1519 1520 1521 typedef struct s_pxe_cpb_fill_header { 1522 // 1523 // Source and destination MAC addresses. These will be copied into 1524 // the media header without doing byte swapping. 1525 // 1526 PXE_MAC_ADDR SrcAddr; 1527 PXE_MAC_ADDR DestAddr; 1528 1529 // 1530 // Address of first byte of media header. The first byte of packet data 1531 // follows the last byte of the media header. 1532 // 1533 PXE_UINT64 MediaHeader; 1534 1535 // 1536 // Length of packet data in bytes (not including the media header). 1537 // 1538 PXE_UINT32 PacketLen; 1539 1540 // 1541 // Protocol type. This will be copied into the media header without 1542 // doing byte swapping. Protocol type numbers can be obtained from 1543 // the Assigned Numbers RFC 1700. 1544 // 1545 PXE_UINT16 Protocol; 1546 1547 // 1548 // Length of the media header in bytes. 1549 // 1550 PXE_UINT16 MediaHeaderLen; 1551 } PXE_CPB_FILL_HEADER; 1552 1553 1554 #define PXE_PROTOCOL_ETHERNET_IP 0x0800 1555 #define PXE_PROTOCOL_ETHERNET_ARP 0x0806 1556 #define MAX_XMIT_FRAGMENTS 16 1557 1558 typedef struct s_pxe_cpb_fill_header_fragmented { 1559 // 1560 // Source and destination MAC addresses. These will be copied into 1561 // the media header without doing byte swapping. 1562 // 1563 PXE_MAC_ADDR SrcAddr; 1564 PXE_MAC_ADDR DestAddr; 1565 1566 // 1567 // Length of packet data in bytes (not including the media header). 1568 // 1569 PXE_UINT32 PacketLen; 1570 1571 // 1572 // Protocol type. This will be copied into the media header without 1573 // doing byte swapping. Protocol type numbers can be obtained from 1574 // the Assigned Numbers RFC 1700. 1575 // 1576 PXE_MEDIA_PROTOCOL Protocol; 1577 1578 // 1579 // Length of the media header in bytes. 1580 // 1581 PXE_UINT16 MediaHeaderLen; 1582 1583 // 1584 // Number of packet fragment descriptors. 1585 // 1586 PXE_UINT16 FragCnt; 1587 1588 // 1589 // Reserved, must be set to zero. 1590 // 1591 PXE_UINT16 reserved; 1592 1593 // 1594 // Array of packet fragment descriptors. The first byte of the media 1595 // header is the first byte of the first fragment. 1596 // 1597 struct { 1598 // 1599 // Address of this packet fragment. 1600 // 1601 PXE_UINT64 FragAddr; 1602 1603 // 1604 // Length of this packet fragment. 1605 // 1606 PXE_UINT32 FragLen; 1607 1608 // 1609 // Reserved, must be set to zero. 1610 // 1611 PXE_UINT32 reserved; 1612 } FragDesc[MAX_XMIT_FRAGMENTS]; 1613 } PXE_CPB_FILL_HEADER_FRAGMENTED; 1614 1615 1616 1617 typedef struct s_pxe_cpb_transmit { 1618 // 1619 // Address of first byte of frame buffer. This is also the first byte 1620 // of the media header. 1621 // 1622 PXE_UINT64 FrameAddr; 1623 1624 // 1625 // Length of the data portion of the frame buffer in bytes. Do not 1626 // include the length of the media header. 1627 // 1628 PXE_UINT32 DataLen; 1629 1630 // 1631 // Length of the media header in bytes. 1632 // 1633 PXE_UINT16 MediaheaderLen; 1634 1635 // 1636 // Reserved, must be zero. 1637 // 1638 PXE_UINT16 reserved; 1639 } PXE_CPB_TRANSMIT; 1640 1641 1642 1643 typedef struct s_pxe_cpb_transmit_fragments { 1644 // 1645 // Length of packet data in bytes (not including the media header). 1646 // 1647 PXE_UINT32 FrameLen; 1648 1649 // 1650 // Length of the media header in bytes. 1651 // 1652 PXE_UINT16 MediaheaderLen; 1653 1654 // 1655 // Number of packet fragment descriptors. 1656 // 1657 PXE_UINT16 FragCnt; 1658 1659 // 1660 // Array of frame fragment descriptors. The first byte of the first 1661 // fragment is also the first byte of the media header. 1662 // 1663 struct { 1664 // 1665 // Address of this frame fragment. 1666 // 1667 PXE_UINT64 FragAddr; 1668 1669 // 1670 // Length of this frame fragment. 1671 // 1672 PXE_UINT32 FragLen; 1673 1674 // 1675 // Reserved, must be set to zero. 1676 // 1677 PXE_UINT32 reserved; 1678 } FragDesc[MAX_XMIT_FRAGMENTS]; 1679 } PXE_CPB_TRANSMIT_FRAGMENTS; 1680 1681 1682 typedef struct s_pxe_cpb_receive { 1683 // 1684 // Address of first byte of receive buffer. This is also the first byte 1685 // of the frame header. 1686 // 1687 PXE_UINT64 BufferAddr; 1688 1689 // 1690 // Length of receive buffer. This must be large enough to hold the 1691 // received frame (media header + data). If the length of smaller than 1692 // the received frame, data will be lost. 1693 // 1694 PXE_UINT32 BufferLen; 1695 1696 // 1697 // Reserved, must be set to zero. 1698 // 1699 PXE_UINT32 reserved; 1700 } PXE_CPB_RECEIVE; 1701 1702 1703 typedef struct s_pxe_db_receive { 1704 // 1705 // Source and destination MAC addresses from media header. 1706 // 1707 PXE_MAC_ADDR SrcAddr; 1708 PXE_MAC_ADDR DestAddr; 1709 1710 // 1711 // Length of received frame. May be larger than receive buffer size. 1712 // The receive buffer will not be overwritten. This is how to tell 1713 // if data was lost because the receive buffer was too small. 1714 // 1715 PXE_UINT32 FrameLen; 1716 1717 // 1718 // Protocol type from media header. 1719 // 1720 PXE_MEDIA_PROTOCOL Protocol; 1721 1722 // 1723 // Length of media header in received frame. 1724 // 1725 PXE_UINT16 MediaHeaderLen; 1726 1727 // 1728 // Type of receive frame. 1729 // 1730 PXE_FRAME_TYPE Type; 1731 1732 // 1733 // Reserved, must be zero. 1734 // 1735 PXE_UINT8 reserved[7]; 1736 1737 } PXE_DB_RECEIVE; 1738 1739 #pragma pack() 1740 1741 /* EOF - efi_pxe.h */ 1742 #endif /* _EFI_PXE_H */ 1743 1744