1*823f0493SLoGin /* SPDX-License-Identifier: GPL-2.0-only */ 2*823f0493SLoGin /* 3*823f0493SLoGin * Copyright (C) 2015 Regents of the University of California 4*823f0493SLoGin */ 5*823f0493SLoGin 6*823f0493SLoGin #ifndef _ASM_RISCV_ASM_H 7*823f0493SLoGin #define _ASM_RISCV_ASM_H 8*823f0493SLoGin 9*823f0493SLoGin #ifdef __ASSEMBLY__ 10*823f0493SLoGin #define __ASM_STR(x) x 11*823f0493SLoGin #else 12*823f0493SLoGin #define __ASM_STR(x) #x 13*823f0493SLoGin #endif 14*823f0493SLoGin 15*823f0493SLoGin #if __riscv_xlen == 64 16*823f0493SLoGin #define __REG_SEL(a, b) __ASM_STR(a) 17*823f0493SLoGin #elif __riscv_xlen == 32 18*823f0493SLoGin #define __REG_SEL(a, b) __ASM_STR(b) 19*823f0493SLoGin #else 20*823f0493SLoGin #error "Unexpected __riscv_xlen" 21*823f0493SLoGin #endif 22*823f0493SLoGin 23*823f0493SLoGin #define REG_L __REG_SEL(ld, lw) 24*823f0493SLoGin #define REG_S __REG_SEL(sd, sw) 25*823f0493SLoGin #define REG_SC __REG_SEL(sc.d, sc.w) 26*823f0493SLoGin #define REG_AMOSWAP_AQ __REG_SEL(amoswap.d.aq, amoswap.w.aq) 27*823f0493SLoGin #define REG_ASM __REG_SEL(.dword, .word) 28*823f0493SLoGin #define SZREG __REG_SEL(8, 4) 29*823f0493SLoGin #define LGREG __REG_SEL(3, 2) 30*823f0493SLoGin 31*823f0493SLoGin #if __SIZEOF_POINTER__ == 8 32*823f0493SLoGin #ifdef __ASSEMBLY__ 33*823f0493SLoGin #define RISCV_PTR .dword 34*823f0493SLoGin #define RISCV_SZPTR 8 35*823f0493SLoGin #define RISCV_LGPTR 3 36*823f0493SLoGin #else 37*823f0493SLoGin #define RISCV_PTR ".dword" 38*823f0493SLoGin #define RISCV_SZPTR "8" 39*823f0493SLoGin #define RISCV_LGPTR "3" 40*823f0493SLoGin #endif 41*823f0493SLoGin #elif __SIZEOF_POINTER__ == 4 42*823f0493SLoGin #ifdef __ASSEMBLY__ 43*823f0493SLoGin #define RISCV_PTR .word 44*823f0493SLoGin #define RISCV_SZPTR 4 45*823f0493SLoGin #define RISCV_LGPTR 2 46*823f0493SLoGin #else 47*823f0493SLoGin #define RISCV_PTR ".word" 48*823f0493SLoGin #define RISCV_SZPTR "4" 49*823f0493SLoGin #define RISCV_LGPTR "2" 50*823f0493SLoGin #endif 51*823f0493SLoGin #else 52*823f0493SLoGin #error "Unexpected __SIZEOF_POINTER__" 53*823f0493SLoGin #endif 54*823f0493SLoGin 55*823f0493SLoGin #if (__SIZEOF_INT__ == 4) 56*823f0493SLoGin #define RISCV_INT __ASM_STR(.word) 57*823f0493SLoGin #define RISCV_SZINT __ASM_STR(4) 58*823f0493SLoGin #define RISCV_LGINT __ASM_STR(2) 59*823f0493SLoGin #else 60*823f0493SLoGin #error "Unexpected __SIZEOF_INT__" 61*823f0493SLoGin #endif 62*823f0493SLoGin 63*823f0493SLoGin #if (__SIZEOF_SHORT__ == 2) 64*823f0493SLoGin #define RISCV_SHORT __ASM_STR(.half) 65*823f0493SLoGin #define RISCV_SZSHORT __ASM_STR(2) 66*823f0493SLoGin #define RISCV_LGSHORT __ASM_STR(1) 67*823f0493SLoGin #else 68*823f0493SLoGin #error "Unexpected __SIZEOF_SHORT__" 69*823f0493SLoGin #endif 70*823f0493SLoGin 71*823f0493SLoGin #ifdef __ASSEMBLY__ 72*823f0493SLoGin #include <asm/asm-offsets.h> 73*823f0493SLoGin 74*823f0493SLoGin /* Common assembly source macros */ 75*823f0493SLoGin 76*823f0493SLoGin /* 77*823f0493SLoGin * NOP sequence 78*823f0493SLoGin */ 79*823f0493SLoGin .macro nops, num 80*823f0493SLoGin .rept \num 81*823f0493SLoGin nop 82*823f0493SLoGin .endr 83*823f0493SLoGin .endm 84*823f0493SLoGin 85*823f0493SLoGin /* save all GPs except x1 ~ x5 */ 86*823f0493SLoGin .macro save_from_x6_to_x31 87*823f0493SLoGin REG_S x6, PT_T1(sp) 88*823f0493SLoGin REG_S x7, PT_T2(sp) 89*823f0493SLoGin REG_S x8, PT_S0(sp) 90*823f0493SLoGin REG_S x9, PT_S1(sp) 91*823f0493SLoGin REG_S x10, PT_A0(sp) 92*823f0493SLoGin REG_S x11, PT_A1(sp) 93*823f0493SLoGin REG_S x12, PT_A2(sp) 94*823f0493SLoGin REG_S x13, PT_A3(sp) 95*823f0493SLoGin REG_S x14, PT_A4(sp) 96*823f0493SLoGin REG_S x15, PT_A5(sp) 97*823f0493SLoGin REG_S x16, PT_A6(sp) 98*823f0493SLoGin REG_S x17, PT_A7(sp) 99*823f0493SLoGin REG_S x18, PT_S2(sp) 100*823f0493SLoGin REG_S x19, PT_S3(sp) 101*823f0493SLoGin REG_S x20, PT_S4(sp) 102*823f0493SLoGin REG_S x21, PT_S5(sp) 103*823f0493SLoGin REG_S x22, PT_S6(sp) 104*823f0493SLoGin REG_S x23, PT_S7(sp) 105*823f0493SLoGin REG_S x24, PT_S8(sp) 106*823f0493SLoGin REG_S x25, PT_S9(sp) 107*823f0493SLoGin REG_S x26, PT_S10(sp) 108*823f0493SLoGin REG_S x27, PT_S11(sp) 109*823f0493SLoGin REG_S x28, PT_T3(sp) 110*823f0493SLoGin REG_S x29, PT_T4(sp) 111*823f0493SLoGin REG_S x30, PT_T5(sp) 112*823f0493SLoGin REG_S x31, PT_T6(sp) 113*823f0493SLoGin .endm 114*823f0493SLoGin 115*823f0493SLoGin /* restore all GPs except x1 ~ x5 */ 116*823f0493SLoGin .macro restore_from_x6_to_x31 117*823f0493SLoGin REG_L x6, PT_T1(sp) 118*823f0493SLoGin REG_L x7, PT_T2(sp) 119*823f0493SLoGin REG_L x8, PT_S0(sp) 120*823f0493SLoGin REG_L x9, PT_S1(sp) 121*823f0493SLoGin REG_L x10, PT_A0(sp) 122*823f0493SLoGin REG_L x11, PT_A1(sp) 123*823f0493SLoGin REG_L x12, PT_A2(sp) 124*823f0493SLoGin REG_L x13, PT_A3(sp) 125*823f0493SLoGin REG_L x14, PT_A4(sp) 126*823f0493SLoGin REG_L x15, PT_A5(sp) 127*823f0493SLoGin REG_L x16, PT_A6(sp) 128*823f0493SLoGin REG_L x17, PT_A7(sp) 129*823f0493SLoGin REG_L x18, PT_S2(sp) 130*823f0493SLoGin REG_L x19, PT_S3(sp) 131*823f0493SLoGin REG_L x20, PT_S4(sp) 132*823f0493SLoGin REG_L x21, PT_S5(sp) 133*823f0493SLoGin REG_L x22, PT_S6(sp) 134*823f0493SLoGin REG_L x23, PT_S7(sp) 135*823f0493SLoGin REG_L x24, PT_S8(sp) 136*823f0493SLoGin REG_L x25, PT_S9(sp) 137*823f0493SLoGin REG_L x26, PT_S10(sp) 138*823f0493SLoGin REG_L x27, PT_S11(sp) 139*823f0493SLoGin REG_L x28, PT_T3(sp) 140*823f0493SLoGin REG_L x29, PT_T4(sp) 141*823f0493SLoGin REG_L x30, PT_T5(sp) 142*823f0493SLoGin REG_L x31, PT_T6(sp) 143*823f0493SLoGin .endm 144*823f0493SLoGin 145*823f0493SLoGin #endif /* __ASSEMBLY__ */ 146*823f0493SLoGin 147*823f0493SLoGin #endif /* _ASM_RISCV_ASM_H */ 148