1338f6903SLoGin use core::{any::Any, fmt::Debug, intrinsics::unlikely}; 2ce5850adSLoGin 3ce5850adSLoGin use alloc::{ 4338f6903SLoGin string::{String, ToString}, 5ce5850adSLoGin sync::{Arc, Weak}, 6ce5850adSLoGin vec::Vec, 7ce5850adSLoGin }; 8*2eab6dd7S曾俊 use log::warn; 9ce5850adSLoGin use system_error::SystemError; 10ce5850adSLoGin 11e2841179SLoGin use crate::{ 12338f6903SLoGin exception::{ 13338f6903SLoGin dummychip::no_irq_chip, 14338f6903SLoGin handle::{bad_irq_handler, mask_ack_irq}, 15338f6903SLoGin irqdata::IrqStatus, 16338f6903SLoGin irqdesc::irq_desc_manager, 17338f6903SLoGin manage::irq_manager, 18338f6903SLoGin }, 19338f6903SLoGin libs::{ 20338f6903SLoGin cpumask::CpuMask, 21338f6903SLoGin once::Once, 22338f6903SLoGin spinlock::{SpinLock, SpinLockGuard}, 23338f6903SLoGin }, 24e2841179SLoGin mm::VirtAddr, 25338f6903SLoGin smp::cpu::ProcessorId, 26e2841179SLoGin }; 27ce5850adSLoGin 28ce5850adSLoGin use super::{ 29338f6903SLoGin irqdata::{IrqData, IrqHandlerData, IrqLineStatus}, 30338f6903SLoGin irqdesc::{InnerIrqDesc, IrqAction, IrqDesc, IrqFlowHandler, IrqHandler, IrqReturn}, 31ce5850adSLoGin irqdomain::IrqDomain, 32e2841179SLoGin manage::IrqManager, 33ce5850adSLoGin msi::MsiMsg, 34338f6903SLoGin IrqNumber, 35ce5850adSLoGin }; 36ce5850adSLoGin 37ce5850adSLoGin /// 参考 https://code.dragonos.org.cn/xref/linux-6.1.9/include/linux/irq.h#506 38ce5850adSLoGin pub trait IrqChip: Sync + Send + Any + Debug { 39ce5850adSLoGin fn name(&self) -> &'static str; 40ce5850adSLoGin /// start up the interrupt (defaults to ->enable if ENOSYS) 410102d69fSLoGin fn irq_startup(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 42ce5850adSLoGin Err(SystemError::ENOSYS) 43ce5850adSLoGin } 44ce5850adSLoGin 45ce5850adSLoGin /// shut down the interrupt (defaults to ->disable if ENOSYS) 460102d69fSLoGin fn irq_shutdown(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 47ce5850adSLoGin Err(SystemError::ENOSYS) 48ce5850adSLoGin } 49ce5850adSLoGin 50ce5850adSLoGin /// enable the interrupt 51ce5850adSLoGin /// 52ce5850adSLoGin /// (defaults to ->unmask if ENOSYS) 530102d69fSLoGin fn irq_enable(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 54ce5850adSLoGin Err(SystemError::ENOSYS) 55ce5850adSLoGin } 56ce5850adSLoGin 57ce5850adSLoGin /// disable the interrupt 580102d69fSLoGin fn irq_disable(&self, irq_data: &Arc<IrqData>); 59ce5850adSLoGin 60ce5850adSLoGin /// start of a new interrupt 610102d69fSLoGin fn irq_ack(&self, irq_data: &Arc<IrqData>); 62ce5850adSLoGin 63ce5850adSLoGin /// mask an interrupt source 64e2841179SLoGin /// 65e2841179SLoGin /// 用于屏蔽中断 66e2841179SLoGin /// 67338f6903SLoGin /// 如果返回ENOSYS,则表明irq_mask()不支持. 那么中断机制代码将调用irq_disable()。 68e2841179SLoGin /// 69e2841179SLoGin /// 如果返回错误,那么中断的屏蔽状态将不会改变。 700102d69fSLoGin fn irq_mask(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 71e2841179SLoGin Err(SystemError::ENOSYS) 72e2841179SLoGin } 73e2841179SLoGin 74e2841179SLoGin /// 指示当前芯片是否实现了`irq_mask_ack`函数 75e2841179SLoGin fn can_mask_ack(&self) -> bool; 76e2841179SLoGin 77ce5850adSLoGin /// ack and mask an interrupt source 780102d69fSLoGin fn irq_mask_ack(&self, _irq_data: &Arc<IrqData>) {} 79e2841179SLoGin 80ce5850adSLoGin /// unmask an interrupt source 81e2841179SLoGin /// 82e2841179SLoGin /// 用于取消屏蔽中断 83e2841179SLoGin /// 84e2841179SLoGin /// 如果返回ENOSYS,则表明irq_unmask()不支持. 850102d69fSLoGin fn irq_unmask(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 86e2841179SLoGin Err(SystemError::ENOSYS) 87e2841179SLoGin } 88ce5850adSLoGin /// end of interrupt 890102d69fSLoGin fn irq_eoi(&self, _irq_data: &Arc<IrqData>) {} 90ce5850adSLoGin 91e2841179SLoGin /// 指示当前芯片是否可以设置中断亲和性。 92e2841179SLoGin fn can_set_affinity(&self) -> bool; 93e2841179SLoGin 94e2841179SLoGin /// 在SMP机器上设置CPU亲和性。 95e2841179SLoGin /// 96e2841179SLoGin /// 如果force参数为真,它告诉驱动程序无条件地应用亲和性设置。 97e2841179SLoGin /// 不需要对提供的亲和性掩码进行完整性检查。这用于CPU热插拔,其中目标CPU尚未在cpu_online_mask中设置。 98e2841179SLoGin fn irq_set_affinity( 99e2841179SLoGin &self, 1000102d69fSLoGin _irq_data: &Arc<IrqData>, 101e2841179SLoGin _cpu: &CpuMask, 102e2841179SLoGin _force: bool, 103e2841179SLoGin ) -> Result<IrqChipSetMaskResult, SystemError> { 104e2841179SLoGin Err(SystemError::ENOSYS) 105e2841179SLoGin } 106ce5850adSLoGin 107ce5850adSLoGin /// retrigger an IRQ to the CPU 1080102d69fSLoGin fn retrigger(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 109e2841179SLoGin Err(SystemError::ENOSYS) 110e2841179SLoGin } 111e2841179SLoGin 112e2841179SLoGin /// 指示当前芯片是否可以设置中断流类型。 113e2841179SLoGin /// 114e2841179SLoGin /// 如果返回true,则可以调用irq_set_type()。 115e2841179SLoGin fn can_set_flow_type(&self) -> bool; 116ce5850adSLoGin 117ce5850adSLoGin /// set the flow type of an interrupt 118ce5850adSLoGin /// 119ce5850adSLoGin /// flow_type: the flow type to set 120ce5850adSLoGin /// 121ce5850adSLoGin fn irq_set_type( 122ce5850adSLoGin &self, 1230102d69fSLoGin _irq_data: &Arc<IrqData>, 124ce5850adSLoGin _flow_type: IrqLineStatus, 125e2841179SLoGin ) -> Result<IrqChipSetMaskResult, SystemError> { 126ce5850adSLoGin Err(SystemError::ENOSYS) 127ce5850adSLoGin } 128ce5850adSLoGin 129ce5850adSLoGin /// enable/disable power management wake-on of an interrupt 1300102d69fSLoGin fn irq_set_wake(&self, _irq_data: &Arc<IrqData>, _on: bool) -> Result<(), SystemError> { 131ce5850adSLoGin Err(SystemError::ENOSYS) 132ce5850adSLoGin } 133ce5850adSLoGin 134ce5850adSLoGin /// function to lock access to slow bus (i2c) chips 1350102d69fSLoGin fn irq_bus_lock(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 136ce5850adSLoGin Ok(()) 137ce5850adSLoGin } 138ce5850adSLoGin 139ce5850adSLoGin /// function to sync and unlock slow bus (i2c) chips 1400102d69fSLoGin fn irq_bus_sync_unlock(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 141ce5850adSLoGin Ok(()) 142ce5850adSLoGin } 143ce5850adSLoGin 144ce5850adSLoGin /// function called from core code on suspend once per 145ce5850adSLoGin /// chip, when one or more interrupts are installed 1460102d69fSLoGin fn irq_suspend(&self, _irq_data: &Arc<IrqData>) {} 147ce5850adSLoGin 148ce5850adSLoGin /// function called from core code on resume once per chip, 149ce5850adSLoGin /// when one ore more interrupts are installed 1500102d69fSLoGin fn irq_resume(&self, _irq_data: &Arc<IrqData>) {} 151ce5850adSLoGin 152ce5850adSLoGin /// function called from core code on shutdown once per chip 1530102d69fSLoGin fn irq_pm_shutdown(&self, _irq_data: &Arc<IrqData>) {} 154ce5850adSLoGin 155ce5850adSLoGin /// Optional function to set irq_data.mask for special cases 1560102d69fSLoGin fn irq_calc_mask(&self, _irq_data: &Arc<IrqData>) {} 157ce5850adSLoGin 158ce5850adSLoGin // todo: print chip 159ce5850adSLoGin 160ce5850adSLoGin /// optional to request resources before calling 161ce5850adSLoGin /// any other callback related to this irq 1620102d69fSLoGin fn irq_request_resources(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 163ce5850adSLoGin Ok(()) 164ce5850adSLoGin } 165ce5850adSLoGin 166ce5850adSLoGin /// optional to release resources acquired with 167ce5850adSLoGin /// irq_request_resources 1680102d69fSLoGin fn irq_release_resources(&self, _irq_data: &Arc<IrqData>) {} 169ce5850adSLoGin 170ce5850adSLoGin /// optional to compose message content for MSI 171e2841179SLoGin /// 172e2841179SLoGin /// 组装MSI消息并返回到msg中 1730102d69fSLoGin fn irq_compose_msi_msg(&self, _irq_data: &Arc<IrqData>, _msg: &mut MsiMsg) {} 174ce5850adSLoGin 175ce5850adSLoGin /// optional to write message content for MSI 1760102d69fSLoGin fn irq_write_msi_msg(&self, _irq_data: &Arc<IrqData>, _msg: &MsiMsg) {} 177ce5850adSLoGin 178ce5850adSLoGin /// return the internal state of an interrupt 179ce5850adSLoGin fn irqchip_state( 180ce5850adSLoGin &self, 1810102d69fSLoGin _irq_data: &Arc<IrqData>, 182ce5850adSLoGin _which: IrqChipState, 183ce5850adSLoGin ) -> Result<bool, SystemError> { 184ce5850adSLoGin Err(SystemError::ENOSYS) 185ce5850adSLoGin } 186ce5850adSLoGin 187ce5850adSLoGin /// set the internal state of an interrupt 188ce5850adSLoGin fn set_irqchip_state( 189ce5850adSLoGin &self, 1900102d69fSLoGin _irq_data: &Arc<IrqData>, 191ce5850adSLoGin _which: IrqChipState, 192ce5850adSLoGin _state: bool, 193ce5850adSLoGin ) -> Result<(), SystemError> { 194ce5850adSLoGin Err(SystemError::ENOSYS) 195ce5850adSLoGin } 196ce5850adSLoGin 197ce5850adSLoGin // todo: set vcpu affinity 198ce5850adSLoGin 199ce5850adSLoGin /// send a single IPI to destination cpus 2000102d69fSLoGin fn send_single_ipi(&self, _irq_data: &Arc<IrqData>, _cpu: u32) {} 201ce5850adSLoGin 202ce5850adSLoGin // todo: send ipi with cpu mask 203ce5850adSLoGin 204ce5850adSLoGin /// function called from core code before enabling an NMI 2050102d69fSLoGin fn irq_nmi_setup(&self, _irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 206ce5850adSLoGin Err(SystemError::ENOSYS) 207ce5850adSLoGin } 208ce5850adSLoGin 209ce5850adSLoGin /// function called from core code after disabling an NMI 2100102d69fSLoGin fn irq_nmi_teardown(&self, _irq_data: &Arc<IrqData>) {} 2113bc96fa4SLoGin 2123bc96fa4SLoGin fn flags(&self) -> IrqChipFlags; 213ce5850adSLoGin } 214ce5850adSLoGin 215ce5850adSLoGin #[allow(dead_code)] 216ce5850adSLoGin #[derive(Debug, Clone, Copy)] 217ce5850adSLoGin pub enum IrqChipState { 218ce5850adSLoGin /// Is the interrupt pending? 219ce5850adSLoGin Pending, 220ce5850adSLoGin /// Is the interrupt in progress? 221ce5850adSLoGin Active, 222ce5850adSLoGin /// Is the interrupt masked? 223ce5850adSLoGin Masked, 224ce5850adSLoGin /// Is Irq line high? 225ce5850adSLoGin LineLevel, 226ce5850adSLoGin } 227ce5850adSLoGin 228e2841179SLoGin /// 中断芯片的数据(per-irq的) 229e2841179SLoGin pub trait IrqChipData: Sync + Send + Any + Debug { 230e2841179SLoGin fn as_any_ref(&self) -> &dyn Any; 231e2841179SLoGin } 232ce5850adSLoGin 233ce5850adSLoGin bitflags! { 234ce5850adSLoGin /// 定义 IrqGcFlags 位标志 235ce5850adSLoGin pub struct IrqGcFlags: u32 { 236ce5850adSLoGin /// 通过读取mask reg来初始化mask_cache 237ce5850adSLoGin const IRQ_GC_INIT_MASK_CACHE = 1 << 0; 238ce5850adSLoGin /// 对于需要在父irq上调用irq_set_wake()的irq芯片, 将irqs的锁类设置为嵌套。Usually GPIO implementations 239ce5850adSLoGin const IRQ_GC_INIT_NESTED_LOCK = 1 << 1; 240ce5850adSLoGin /// Mask cache是芯片类型私有的 241ce5850adSLoGin const IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2; 242ce5850adSLoGin /// 不计算irqData->mask 243ce5850adSLoGin const IRQ_GC_NO_MASK = 1 << 3; 244ce5850adSLoGin /// 使用大端字节序的寄存器访问(默认:小端LE) 245ce5850adSLoGin const IRQ_GC_BE_IO = 1 << 4; 246ce5850adSLoGin } 247ce5850adSLoGin } 248ce5850adSLoGin 249ce5850adSLoGin #[allow(dead_code)] 250ce5850adSLoGin #[derive(Debug)] 251ce5850adSLoGin pub struct IrqChipGeneric { 252ce5850adSLoGin inner: SpinLock<InnerIrqChipGeneric>, 253ce5850adSLoGin } 254ce5850adSLoGin 255ce5850adSLoGin #[allow(dead_code)] 256ce5850adSLoGin #[derive(Debug)] 257ce5850adSLoGin struct InnerIrqChipGeneric { 258ce5850adSLoGin /// Register base address 259ce5850adSLoGin reg_base: VirtAddr, 260ce5850adSLoGin ops: &'static dyn IrqChipGenericOps, 261ce5850adSLoGin /// Interrupt base num for this chip 262ce5850adSLoGin irq_base: u32, 263ce5850adSLoGin /// Number of interrupts handled by this chip 264ce5850adSLoGin irq_cnt: u32, 265ce5850adSLoGin /// Cached mask register shared between all chip types 266ce5850adSLoGin mask_cache: u32, 267ce5850adSLoGin /// Cached type register 268ce5850adSLoGin type_cache: u32, 269ce5850adSLoGin /// Cached polarity register 270ce5850adSLoGin polarity_cache: u32, 271ce5850adSLoGin /// Interrupt can wakeup from suspend 272ce5850adSLoGin wake_enabled: bool, 273ce5850adSLoGin /// Interrupt is marked as an wakeup from suspend source 274ce5850adSLoGin wake_active: bool, 275ce5850adSLoGin /// Number of available irq_chip_type instances (usually 1) 276ce5850adSLoGin num_chip_type: u32, 277ce5850adSLoGin private_data: Option<Arc<dyn IrqChipGenericPrivateData>>, 278ce5850adSLoGin installed: u64, 279ce5850adSLoGin unused: u64, 280ce5850adSLoGin domain: Weak<IrqDomain>, 281ce5850adSLoGin chip_types: Vec<IrqChipType>, 282ce5850adSLoGin } 283ce5850adSLoGin 2843bc96fa4SLoGin pub trait IrqChipGenericOps: Debug + Send + Sync { 285ce5850adSLoGin /// Alternate I/O accessor (defaults to readl if NULL) 286ce5850adSLoGin unsafe fn reg_readl(&self, addr: VirtAddr) -> u32; 287ce5850adSLoGin 288ce5850adSLoGin /// Alternate I/O accessor (defaults to writel if NULL) 289ce5850adSLoGin unsafe fn reg_writel(&self, addr: VirtAddr, val: u32); 290ce5850adSLoGin 291ce5850adSLoGin /// Function called from core code on suspend once per 292ce5850adSLoGin /// chip; can be useful instead of irq_chip::suspend to 293ce5850adSLoGin /// handle chip details even when no interrupts are in use 294ce5850adSLoGin fn suspend(&self, gc: &Arc<IrqChipGeneric>); 295ce5850adSLoGin /// Function called from core code on resume once per chip; 296ce5850adSLoGin /// can be useful instead of irq_chip::resume to handle chip 297ce5850adSLoGin /// details even when no interrupts are in use 298ce5850adSLoGin fn resume(&self, gc: &Arc<IrqChipGeneric>); 299ce5850adSLoGin } 300ce5850adSLoGin 301ce5850adSLoGin pub trait IrqChipGenericPrivateData: Sync + Send + Any + Debug {} 302ce5850adSLoGin 303ce5850adSLoGin #[derive(Debug)] 304ce5850adSLoGin pub struct IrqChipType { 305ce5850adSLoGin // todo https://code.dragonos.org.cn/xref/linux-6.1.9/include/linux/irq.h#1024 306ce5850adSLoGin } 3073bc96fa4SLoGin 308e2841179SLoGin #[allow(dead_code)] 309e2841179SLoGin #[derive(Debug)] 310e2841179SLoGin pub enum IrqChipSetMaskResult { 311e2841179SLoGin /// core updates mask ok. 312b5b571e0SLoGin Success, 313e2841179SLoGin /// core updates mask ok. No change. 314b5b571e0SLoGin NoChange, 315e2841179SLoGin /// core updates mask ok. Done.(same as SetMaskOk) 316e2841179SLoGin /// 317e2841179SLoGin /// 支持堆叠irq芯片的特殊代码, 表示跳过所有子irq芯片。 318b5b571e0SLoGin Done, 319e2841179SLoGin } 320e2841179SLoGin 3213bc96fa4SLoGin bitflags! { 3223bc96fa4SLoGin /// IrqChip specific flags 3233bc96fa4SLoGin pub struct IrqChipFlags: u32 { 324e2841179SLoGin /// 在调用chip.irq_set_type()之前屏蔽中断 3253bc96fa4SLoGin const IRQCHIP_SET_TYPE_MASKED = 1 << 0; 3263bc96fa4SLoGin /// 只有在irq被处理时才发出irq_eoi() 3273bc96fa4SLoGin const IRQCHIP_EOI_IF_HANDLED = 1 << 1; 3283bc96fa4SLoGin /// 在挂起路径中屏蔽非唤醒irq 3293bc96fa4SLoGin const IRQCHIP_MASK_ON_SUSPEND = 1 << 2; 3303bc96fa4SLoGin /// 只有在irq启用时才调用irq_on/off_line回调 3313bc96fa4SLoGin const IRQCHIP_ONOFFLINE_ENABLED = 1 << 3; 3323bc96fa4SLoGin /// 跳过chip.irq_set_wake(),对于这个irq芯片 3333bc96fa4SLoGin const IRQCHIP_SKIP_SET_WAKE = 1 << 4; 3343bc96fa4SLoGin /// 单次触发不需要屏蔽/取消屏蔽 3353bc96fa4SLoGin const IRQCHIP_ONESHOT_SAFE = 1 << 5; 3363bc96fa4SLoGin /// 芯片在线程模式下需要在取消屏蔽时eoi() 3373bc96fa4SLoGin const IRQCHIP_EOI_THREADED = 1 << 6; 3383bc96fa4SLoGin /// 芯片可以为Level MSIs提供两个门铃 3393bc96fa4SLoGin const IRQCHIP_SUPPORTS_LEVEL_MSI = 1 << 7; 3403bc96fa4SLoGin /// 芯片可以传递NMIs,仅适用于根irqchips 3413bc96fa4SLoGin const IRQCHIP_SUPPORTS_NMI = 1 << 8; 3423bc96fa4SLoGin /// 在挂起路径中,如果它们处于禁用状态,则调用__enable_irq()/__disable_irq()以唤醒irq 3433bc96fa4SLoGin const IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = 1 << 9; 3443bc96fa4SLoGin /// 在启动前更新默认亲和性 3453bc96fa4SLoGin const IRQCHIP_AFFINITY_PRE_STARTUP = 1 << 10; 3463bc96fa4SLoGin /// 不要在这个芯片中改变任何东西 3473bc96fa4SLoGin const IRQCHIP_IMMUTABLE = 1 << 11; 3483bc96fa4SLoGin } 3493bc96fa4SLoGin } 350e2841179SLoGin 351e2841179SLoGin impl IrqManager { 352e2841179SLoGin /// Acknowledge the parent interrupt 353e2841179SLoGin #[allow(dead_code)] 354e2841179SLoGin pub fn irq_chip_ack_parent(&self, irq_data: &Arc<IrqData>) { 355b5b571e0SLoGin let parent_data = irq_data.parent_data().and_then(|p| p.upgrade()); 356e2841179SLoGin 357e2841179SLoGin if let Some(parent_data) = parent_data { 358e2841179SLoGin let parent_chip = parent_data.chip_info_read_irqsave().chip(); 359e2841179SLoGin parent_chip.irq_ack(&parent_data); 360e2841179SLoGin } 361e2841179SLoGin } 362e2841179SLoGin 363e2841179SLoGin /// 在硬件中重新触发中断 364e2841179SLoGin /// 365e2841179SLoGin /// 遍历中断域的层次结构,并检查是否存在一个硬件重新触发函数。如果存在则调用它 366e2841179SLoGin pub fn irq_chip_retrigger_hierarchy(&self, irq_data: &Arc<IrqData>) -> Result<(), SystemError> { 367e2841179SLoGin let mut data: Option<Arc<IrqData>> = Some(irq_data.clone()); 368b5b571e0SLoGin while let Some(d) = data { 369e2841179SLoGin if let Err(e) = d.chip_info_read_irqsave().chip().retrigger(&d) { 370e2841179SLoGin if e == SystemError::ENOSYS { 371b5b571e0SLoGin data = d.parent_data().and_then(|p| p.upgrade()); 372e2841179SLoGin } else { 373e2841179SLoGin return Err(e); 374e2841179SLoGin } 375e2841179SLoGin } else { 376e2841179SLoGin return Ok(()); 377e2841179SLoGin } 378e2841179SLoGin } 379e2841179SLoGin 380e2841179SLoGin return Ok(()); 381e2841179SLoGin } 382338f6903SLoGin 383338f6903SLoGin pub(super) fn __irq_set_handler( 384338f6903SLoGin &self, 385338f6903SLoGin irq: IrqNumber, 386338f6903SLoGin handler: &'static dyn IrqFlowHandler, 387338f6903SLoGin is_chained: bool, 388338f6903SLoGin name: Option<String>, 389338f6903SLoGin ) { 390338f6903SLoGin let r = irq_desc_manager().lookup_and_lock_bus(irq, false, false); 391338f6903SLoGin if r.is_none() { 392338f6903SLoGin return; 393338f6903SLoGin } 394338f6903SLoGin 395338f6903SLoGin let irq_desc = r.unwrap(); 396338f6903SLoGin 397338f6903SLoGin let mut desc_inner = irq_desc.inner(); 398338f6903SLoGin self.__irq_do_set_handler(&irq_desc, &mut desc_inner, Some(handler), is_chained, name); 399338f6903SLoGin 400338f6903SLoGin drop(desc_inner); 401338f6903SLoGin irq_desc.chip_bus_sync_unlock(); 402338f6903SLoGin } 403338f6903SLoGin 404338f6903SLoGin fn __irq_do_set_handler( 405338f6903SLoGin &self, 406338f6903SLoGin desc: &Arc<IrqDesc>, 407338f6903SLoGin desc_inner: &mut SpinLockGuard<'_, InnerIrqDesc>, 408338f6903SLoGin mut handler: Option<&'static dyn IrqFlowHandler>, 409338f6903SLoGin is_chained: bool, 410338f6903SLoGin name: Option<String>, 411338f6903SLoGin ) { 412338f6903SLoGin if handler.is_none() { 413338f6903SLoGin handler = Some(bad_irq_handler()); 414338f6903SLoGin } else { 415338f6903SLoGin let mut irq_data = Some(desc_inner.irq_data().clone()); 416338f6903SLoGin 417338f6903SLoGin /* 418338f6903SLoGin * 在具有中断域继承的domain中,我们可能会遇到这样的情况, 419338f6903SLoGin * 最外层的芯片还没有设置好,但是内部的芯片已经存在了。 420338f6903SLoGin * 我们选择安装处理程序,而不是退出, 421338f6903SLoGin * 但显然我们此时无法启用/启动中断。 422338f6903SLoGin */ 423338f6903SLoGin while irq_data.is_some() { 424338f6903SLoGin let dt = irq_data.as_ref().unwrap().clone(); 425338f6903SLoGin 426338f6903SLoGin let chip_info = dt.chip_info_read_irqsave(); 427338f6903SLoGin 428338f6903SLoGin if !Arc::ptr_eq(&chip_info.chip(), &no_irq_chip()) { 429338f6903SLoGin break; 430338f6903SLoGin } 431338f6903SLoGin 432338f6903SLoGin /* 433338f6903SLoGin * 如果最外层的芯片没有设置好,并且预期立即开始中断, 434338f6903SLoGin * 则放弃。 435338f6903SLoGin */ 436338f6903SLoGin if unlikely(is_chained) { 437*2eab6dd7S曾俊 warn!( 438338f6903SLoGin "Chained handler for irq {} is not supported", 439338f6903SLoGin dt.irq().data() 440338f6903SLoGin ); 441338f6903SLoGin return; 442338f6903SLoGin } 443338f6903SLoGin 444338f6903SLoGin // try the parent 445b5b571e0SLoGin let parent_data = dt.parent_data().and_then(|p| p.upgrade()); 446338f6903SLoGin 447338f6903SLoGin irq_data = parent_data; 448338f6903SLoGin } 449338f6903SLoGin 450338f6903SLoGin if unlikely( 451338f6903SLoGin irq_data.is_none() 452338f6903SLoGin || Arc::ptr_eq( 453338f6903SLoGin &irq_data.as_ref().unwrap().chip_info_read_irqsave().chip(), 454338f6903SLoGin &no_irq_chip(), 455338f6903SLoGin ), 456338f6903SLoGin ) { 457*2eab6dd7S曾俊 warn!("No irq chip for irq {}", desc_inner.irq_data().irq().data()); 458338f6903SLoGin return; 459338f6903SLoGin } 460338f6903SLoGin } 461338f6903SLoGin let handler = handler.unwrap(); 462b5b571e0SLoGin if handler.type_id() == bad_irq_handler().type_id() 463b5b571e0SLoGin && Arc::ptr_eq( 464338f6903SLoGin &desc_inner.irq_data().chip_info_read_irqsave().chip(), 465338f6903SLoGin &no_irq_chip(), 466b5b571e0SLoGin ) 467b5b571e0SLoGin { 468338f6903SLoGin let irq_data = desc_inner.irq_data(); 469338f6903SLoGin mask_ack_irq(irq_data); 470338f6903SLoGin 471338f6903SLoGin irq_data.irqd_set(IrqStatus::IRQD_IRQ_DISABLED); 472338f6903SLoGin 473338f6903SLoGin if is_chained { 474338f6903SLoGin desc_inner.clear_actions(); 475338f6903SLoGin } 476338f6903SLoGin desc_inner.set_depth(1); 477338f6903SLoGin } 478338f6903SLoGin let chip = desc_inner.irq_data().chip_info_read_irqsave().chip(); 479338f6903SLoGin desc.set_handler_no_lock_inner(handler, desc_inner.irq_data(), &chip); 480338f6903SLoGin desc_inner.set_name(name); 481338f6903SLoGin 482b5b571e0SLoGin if handler.type_id() != bad_irq_handler().type_id() && is_chained { 483338f6903SLoGin let trigger_type = desc_inner.common_data().trigger_type(); 484338f6903SLoGin 485338f6903SLoGin /* 486338f6903SLoGin * 我们即将立即启动这个中断, 487338f6903SLoGin * 因此需要设置触发配置。 488338f6903SLoGin * 但是 .irq_set_type 回调可能已经覆盖了 489338f6903SLoGin * irqflowhandler,忽略了我们正在处理的 490338f6903SLoGin * 是一个链式中断。立即重置它,因为我们 491338f6903SLoGin * 确实知道更好的处理方式。 492338f6903SLoGin */ 493338f6903SLoGin 494338f6903SLoGin if trigger_type != IrqLineStatus::IRQ_TYPE_NONE { 495338f6903SLoGin irq_manager() 496338f6903SLoGin .do_set_irq_trigger(desc.clone(), desc_inner, trigger_type) 497338f6903SLoGin .ok(); 498338f6903SLoGin desc.set_handler(handler); 499338f6903SLoGin } 500338f6903SLoGin 501338f6903SLoGin desc_inner.set_noprobe(); 502338f6903SLoGin desc_inner.set_norequest(); 503338f6903SLoGin desc_inner.set_nothread(); 504338f6903SLoGin 505338f6903SLoGin desc_inner.clear_actions(); 506338f6903SLoGin desc_inner.add_action(chained_action()); 507338f6903SLoGin 508338f6903SLoGin irq_manager() 509338f6903SLoGin .irq_activate_and_startup(desc, desc_inner, IrqManager::IRQ_RESEND) 510338f6903SLoGin .ok(); 511338f6903SLoGin } 512338f6903SLoGin 513338f6903SLoGin return; 514338f6903SLoGin } 515338f6903SLoGin 516338f6903SLoGin pub fn irq_set_handler_data( 517338f6903SLoGin &self, 518338f6903SLoGin irq: IrqNumber, 519338f6903SLoGin data: Option<Arc<dyn IrqHandlerData>>, 520338f6903SLoGin ) -> Result<(), SystemError> { 521338f6903SLoGin let desc = irq_desc_manager().lookup(irq).ok_or(SystemError::EINVAL)?; 522338f6903SLoGin desc.inner().common_data().inner().set_handler_data(data); 523338f6903SLoGin 524338f6903SLoGin return Ok(()); 525338f6903SLoGin } 526338f6903SLoGin 527338f6903SLoGin pub fn irq_percpu_disable( 528338f6903SLoGin &self, 529338f6903SLoGin desc: &Arc<IrqDesc>, 530338f6903SLoGin irq_data: &Arc<IrqData>, 531338f6903SLoGin irq_chip: &Arc<dyn IrqChip>, 532338f6903SLoGin cpu: ProcessorId, 533338f6903SLoGin ) { 534338f6903SLoGin if let Err(e) = irq_chip.irq_mask(irq_data) { 535338f6903SLoGin if e == SystemError::ENOSYS { 536338f6903SLoGin irq_chip.irq_disable(irq_data); 537338f6903SLoGin } 538338f6903SLoGin } 539338f6903SLoGin 540338f6903SLoGin desc.inner() 541338f6903SLoGin .percpu_enabled_mut() 542338f6903SLoGin .as_mut() 543338f6903SLoGin .unwrap() 544338f6903SLoGin .set(cpu, false); 545338f6903SLoGin } 546338f6903SLoGin } 547338f6903SLoGin 548338f6903SLoGin lazy_static! { 549338f6903SLoGin pub(super) static ref CHAINED_ACTION: Arc<IrqAction> = IrqAction::new( 550338f6903SLoGin IrqNumber::new(0), 551338f6903SLoGin "".to_string(), 552338f6903SLoGin Some(&ChainedActionHandler), 553338f6903SLoGin None, 554338f6903SLoGin ); 555338f6903SLoGin } 556338f6903SLoGin 557338f6903SLoGin #[allow(dead_code)] 558338f6903SLoGin pub(super) fn chained_action() -> Arc<IrqAction> { 559338f6903SLoGin CHAINED_ACTION.clone() 560338f6903SLoGin } 561338f6903SLoGin 562338f6903SLoGin /// Chained handlers 永远不应该在它们的IRQ上调用irqaction。如果发生这种情况, 563338f6903SLoGin /// 这个默认irqaction将发出警告。 564338f6903SLoGin #[derive(Debug)] 565338f6903SLoGin struct ChainedActionHandler; 566338f6903SLoGin 567338f6903SLoGin impl IrqHandler for ChainedActionHandler { 568338f6903SLoGin fn handle( 569338f6903SLoGin &self, 570338f6903SLoGin irq: IrqNumber, 571338f6903SLoGin _static_data: Option<&dyn IrqHandlerData>, 572338f6903SLoGin _dynamic_data: Option<Arc<dyn IrqHandlerData>>, 573338f6903SLoGin ) -> Result<IrqReturn, SystemError> { 574338f6903SLoGin static ONCE: Once = Once::new(); 575338f6903SLoGin ONCE.call_once(|| { 576*2eab6dd7S曾俊 warn!("Chained irq {} should not call an action.", irq.data()); 577338f6903SLoGin }); 578338f6903SLoGin 579338f6903SLoGin Ok(IrqReturn::NotHandled) 580338f6903SLoGin } 581e2841179SLoGin } 582