1 #![allow(dead_code)] 2 // 目前仅支持单主桥单Segment 3 4 use super::pci_irq::{IrqType, PciIrqError}; 5 use crate::arch::{PciArch, TraitPciArch}; 6 use crate::include::bindings::bindings::{ 7 initial_mm, mm_map, mm_struct, PAGE_2M_SIZE, VM_DONTCOPY, VM_IO, 8 }; 9 use crate::libs::rwlock::{RwLock, RwLockReadGuard, RwLockWriteGuard}; 10 use crate::mm::mmio_buddy::MMIO_POOL; 11 use crate::{kdebug, kerror, kinfo, kwarn}; 12 use alloc::vec::Vec; 13 use alloc::{boxed::Box, collections::LinkedList}; 14 use bitflags::bitflags; 15 use core::{ 16 convert::TryFrom, 17 fmt::{self, Debug, Display, Formatter}, 18 }; 19 // PCI_DEVICE_LINKEDLIST 添加了读写锁的全局链表，里面存储了检索到的PCI设备结构体 20 // PCI_ROOT_0 Segment为0的全局PciRoot 21 lazy_static! { 22 pub static ref PCI_DEVICE_LINKEDLIST: PciDeviceLinkedList = PciDeviceLinkedList::new(); 23 pub static ref PCI_ROOT_0: Option<PciRoot> = { 24 match PciRoot::new(0) { 25 Ok(root) => Some(root), 26 Err(err) => { 27 kerror!("Pci_root init failed because of error: {}", err); 28 None 29 } 30 } 31 }; 32 } 33 /// PCI域地址 34 #[derive(Clone, Copy, Eq, Ord, PartialEq, PartialOrd)] 35 #[repr(transparent)] 36 pub struct PciAddr(usize); 37 38 impl PciAddr { 39 #[inline(always)] 40 pub const fn new(address: usize) -> Self { 41 Self(address) 42 } 43 44 /// @brief 获取PCI域地址的值 45 #[inline(always)] 46 pub fn data(&self) -> usize { 47 self.0 48 } 49 50 /// @brief 将PCI域地址加上一个偏移量 51 #[inline(always)] 52 pub fn add(self, offset: usize) -> Self { 53 Self(self.0 + offset) 54 } 55 56 /// @brief 判断PCI域地址是否按照指定要求对齐 57 #[inline(always)] 58 pub fn check_aligned(&self, align: usize) -> bool { 59 return self.0 & (align - 1) == 0; 60 } 61 } 62 impl Debug for PciAddr { 63 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { 64 write!(f, "PciAddr({:#x})", self.0) 65 } 66 } 67 68 /// 添加了读写锁的链表，存储PCI设备结构体 69 pub struct PciDeviceLinkedList { 70 list: RwLock<LinkedList<Box<dyn PciDeviceStructure>>>, 71 } 72 73 impl PciDeviceLinkedList { 74 /// @brief 初始化结构体 75 fn new() -> Self { 76 PciDeviceLinkedList { 77 list: RwLock::new(LinkedList::new()), 78 } 79 } 80 /// @brief 获取可读的linkedlist(读锁守卫) 81 /// @return RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> 读锁守卫 82 pub fn read(&self) -> RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 83 self.list.read() 84 } 85 /// @brief 获取可写的linkedlist(写锁守卫) 86 /// @return RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> 写锁守卫 87 pub fn write(&self) -> RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 88 self.list.write() 89 } 90 /// @brief 获取链表中PCI结构体数目 91 /// @return usize 链表中PCI结构体数目 92 pub fn num(&self) -> usize { 93 let list = self.list.read(); 94 list.len() 95 } 96 /// @brief 添加Pci设备结构体到链表中 97 pub fn add(&self, device: Box<dyn PciDeviceStructure>) { 98 let mut list = self.list.write(); 99 list.push_back(device); 100 } 101 } 102 103 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其可变引用 104 /// @param list 链表的写锁守卫 105 /// @param class_code 寄存器值 106 /// @param subclass 寄存器值，与class_code一起确定设备类型 107 /// @return Vec<&'a mut Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的可变引用的容器 108 pub fn get_pci_device_structure_mut<'a>( 109 list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 110 class_code: u8, 111 subclass: u8, 112 ) -> Vec<&'a mut Box<(dyn PciDeviceStructure)>> { 113 let mut result = Vec::new(); 114 for box_pci_device_structure in list.iter_mut() { 115 let common_header = (*box_pci_device_structure).common_header(); 116 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 117 result.push(box_pci_device_structure); 118 } 119 } 120 result 121 } 122 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其不可变引用 123 /// @param list 链表的读锁守卫 124 /// @param class_code 寄存器值 125 /// @param subclass 寄存器值，与class_code一起确定设备类型 126 /// @return Vec<&'a Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的不可变引用的容器 127 pub fn get_pci_device_structure<'a>( 128 list: &'a mut RwLockReadGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 129 class_code: u8, 130 subclass: u8, 131 ) -> Vec<&'a Box<(dyn PciDeviceStructure)>> { 132 let mut result = Vec::new(); 133 for box_pci_device_structure in list.iter() { 134 let common_header = (*box_pci_device_structure).common_header(); 135 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 136 result.push(box_pci_device_structure); 137 } 138 } 139 result 140 } 141 142 //Bar0寄存器的offset 143 const BAR0_OFFSET: u8 = 0x10; 144 //Status、Command寄存器的offset 145 const STATUS_COMMAND_OFFSET: u8 = 0x04; 146 /// ID for vendor-specific PCI capabilities.(Virtio Capabilities) 147 pub const PCI_CAP_ID_VNDR: u8 = 0x09; 148 pub const PCI_CAP_ID_MSI: u8 = 0x05; 149 pub const PCI_CAP_ID_MSIX: u8 = 0x11; 150 pub const PORT_PCI_CONFIG_ADDRESS: u16 = 0xcf8; 151 pub const PORT_PCI_CONFIG_DATA: u16 = 0xcfc; 152 // pci设备分组的id 153 pub type SegmentGroupNumber = u16; //理论上最多支持65535个Segment_Group 154 155 bitflags! { 156 /// The status register in PCI configuration space. 157 pub struct Status: u16 { 158 // Bits 0-2 are reserved. 159 /// The state of the device's INTx# signal. 160 const INTERRUPT_STATUS = 1 << 3; 161 /// The device has a linked list of capabilities. 162 const CAPABILITIES_LIST = 1 << 4; 163 /// The device is capabile of running at 66 MHz rather than 33 MHz. 164 const MHZ_66_CAPABLE = 1 << 5; 165 // Bit 6 is reserved. 166 /// The device can accept fast back-to-back transactions not from the same agent. 167 const FAST_BACK_TO_BACK_CAPABLE = 1 << 7; 168 /// The bus agent observed a parity error (if parity error handling is enabled). 169 const MASTER_DATA_PARITY_ERROR = 1 << 8; 170 // Bits 9-10 are DEVSEL timing. 171 /// A target device terminated a transaction with target-abort. 172 const SIGNALED_TARGET_ABORT = 1 << 11; 173 /// A master device transaction was terminated with target-abort. 174 const RECEIVED_TARGET_ABORT = 1 << 12; 175 /// A master device transaction was terminated with master-abort. 176 const RECEIVED_MASTER_ABORT = 1 << 13; 177 /// A device asserts SERR#. 178 const SIGNALED_SYSTEM_ERROR = 1 << 14; 179 /// The device detects a parity error, even if parity error handling is disabled. 180 const DETECTED_PARITY_ERROR = 1 << 15; 181 } 182 } 183 184 bitflags! { 185 /// The command register in PCI configuration space. 186 pub struct Command: u16 { 187 /// The device can respond to I/O Space accesses. 188 const IO_SPACE = 1 << 0; 189 /// The device can respond to Memory Space accesses. 190 const MEMORY_SPACE = 1 << 1; 191 /// The device can behave as a bus master. 192 const BUS_MASTER = 1 << 2; 193 /// The device can monitor Special Cycle operations. 194 const SPECIAL_CYCLES = 1 << 3; 195 /// The device can generate the Memory Write and Invalidate command. 196 const MEMORY_WRITE_AND_INVALIDATE_ENABLE = 1 << 4; 197 /// The device will snoop palette register data. 198 const VGA_PALETTE_SNOOP = 1 << 5; 199 /// The device should take its normal action when a parity error is detected. 200 const PARITY_ERROR_RESPONSE = 1 << 6; 201 // Bit 7 is reserved. 202 /// The SERR# driver is enabled. 203 const SERR_ENABLE = 1 << 8; 204 /// The device is allowed to generate fast back-to-back transactions. 205 const FAST_BACK_TO_BACK_ENABLE = 1 << 9; 206 /// Assertion of the device's INTx# signal is disabled. 207 const INTERRUPT_DISABLE = 1 << 10; 208 } 209 } 210 211 /// The type of a PCI device function header. 212 /// 标头类型/设备类型 213 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 214 pub enum HeaderType { 215 /// A normal PCI device. 216 Standard, 217 /// A PCI to PCI bridge. 218 PciPciBridge, 219 /// A PCI to CardBus bridge. 220 PciCardbusBridge, 221 /// Unrecognised header type. 222 Unrecognised(u8), 223 } 224 /// u8到HeaderType的转换 225 impl From<u8> for HeaderType { 226 fn from(value: u8) -> Self { 227 match value { 228 0x00 => Self::Standard, 229 0x01 => Self::PciPciBridge, 230 0x02 => Self::PciCardbusBridge, 231 _ => Self::Unrecognised(value), 232 } 233 } 234 } 235 /// Pci可能触发的各种错误 236 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 237 pub enum PciError { 238 /// The device reported an invalid BAR type. 239 InvalidBarType, 240 CreateMmioError, 241 InvalidBusDeviceFunction, 242 SegmentNotFound, 243 McfgTableNotFound, 244 GetWrongHeader, 245 UnrecognisedHeaderType, 246 PciDeviceStructureTransformError, 247 PciIrqError(PciIrqError), 248 } 249 ///实现PciError的Display trait，使其可以直接输出 250 impl Display for PciError { 251 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 252 match self { 253 Self::InvalidBarType => write!(f, "Invalid PCI BAR type."), 254 Self::CreateMmioError => write!(f, "Error occurred while creating mmio."), 255 Self::InvalidBusDeviceFunction => write!(f, "Found invalid BusDeviceFunction."), 256 Self::SegmentNotFound => write!(f, "Target segment not found"), 257 Self::McfgTableNotFound => write!(f, "ACPI MCFG Table not found"), 258 Self::GetWrongHeader => write!(f, "GetWrongHeader with vendor id 0xffff"), 259 Self::UnrecognisedHeaderType => write!(f, "Found device with unrecognised header type"), 260 Self::PciDeviceStructureTransformError => { 261 write!(f, "Found None When transform Pci device structure") 262 } 263 Self::PciIrqError(err) => write!(f, "Error occurred while setting irq :{:?}.", err), 264 } 265 } 266 } 267 268 /// trait类型Pci_Device_Structure表示pci设备，动态绑定三种具体设备类型：Pci_Device_Structure_General_Device、Pci_Device_Structure_Pci_to_Pci_Bridge、Pci_Device_Structure_Pci_to_Cardbus_Bridge 269 pub trait PciDeviceStructure: Send + Sync { 270 /// @brief 获取设备类型 271 /// @return HeaderType 设备类型 272 fn header_type(&self) -> HeaderType; 273 /// @brief 当其为standard设备时返回&Pci_Device_Structure_General_Device，其余情况返回None 274 #[inline(always)] 275 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 276 None 277 } 278 /// @brief 当其为pci to pci bridge设备时返回&Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 279 #[inline(always)] 280 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 281 None 282 } 283 /// @brief 当其为pci to cardbus bridge设备时返回&Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 284 #[inline(always)] 285 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 286 None 287 } 288 /// @brief 获取Pci设备共有的common_header 289 /// @return 返回其不可变引用 290 fn common_header(&self) -> &PciDeviceStructureHeader; 291 /// @brief 当其为standard设备时返回&mut Pci_Device_Structure_General_Device，其余情况返回None 292 #[inline(always)] 293 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 294 None 295 } 296 /// @brief 当其为pci to pci bridge设备时返回&mut Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 297 #[inline(always)] 298 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 299 None 300 } 301 /// @brief 当其为pci to cardbus bridge设备时返回&mut Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 302 #[inline(always)] 303 fn as_pci_to_carbus_bridge_device_mut( 304 &mut self, 305 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 306 None 307 } 308 /// @brief 返回迭代器，遍历capabilities 309 fn capabilities(&self) -> Option<CapabilityIterator> { 310 None 311 } 312 /// @brief 获取Status、Command寄存器的值 313 fn status_command(&self) -> (Status, Command) { 314 let common_header = self.common_header(); 315 let status = Status::from_bits_truncate(common_header.status); 316 let command = Command::from_bits_truncate(common_header.command); 317 (status, command) 318 } 319 /// @brief 设置Command寄存器的值 320 fn set_command(&mut self, command: Command) { 321 let common_header = self.common_header_mut(); 322 let command = command.bits(); 323 common_header.command = command; 324 PciArch::write_config( 325 &common_header.bus_device_function, 326 STATUS_COMMAND_OFFSET, 327 command as u32, 328 ); 329 } 330 /// @brief 获取Pci设备共有的common_header 331 /// @return 返回其可变引用 332 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader; 333 334 /// @brief 读取standard设备的bar寄存器，映射后将结果加入结构体的standard_device_bar变量 335 /// @return 只有standard设备才返回成功或者错误，其余返回None 336 #[inline(always)] 337 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 338 None 339 } 340 /// @brief 获取PCI设备的bar寄存器的引用 341 /// @return 342 #[inline(always)] 343 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 344 None 345 } 346 /// @brief 通过设置该pci设备的command 347 fn enable_master(&mut self) { 348 self.set_command(Command::IO_SPACE | Command::MEMORY_SPACE | Command::BUS_MASTER); 349 } 350 /// @brief 寻找设备的msix空间的offset 351 fn msix_capability_offset(&self) -> Option<u8> { 352 for capability in self.capabilities()? { 353 if capability.id == PCI_CAP_ID_MSIX { 354 return Some(capability.offset); 355 } 356 } 357 None 358 } 359 /// @brief 寻找设备的msi空间的offset 360 fn msi_capability_offset(&self) -> Option<u8> { 361 for capability in self.capabilities()? { 362 if capability.id == PCI_CAP_ID_MSI { 363 return Some(capability.offset); 364 } 365 } 366 None 367 } 368 /// @brief 返回结构体中的irq_type的可变引用 369 fn irq_type_mut(&mut self) -> Option<&mut IrqType>; 370 /// @brief 返回结构体中的irq_vector的可变引用 371 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>>; 372 } 373 374 /// Pci_Device_Structure_Header PCI设备结构体共有的头部 375 #[derive(Clone, Debug)] 376 pub struct PciDeviceStructureHeader { 377 // ==== busdevicefunction变量表示该结构体所处的位置 378 pub bus_device_function: BusDeviceFunction, 379 pub vendor_id: u16, // 供应商ID 0xffff是一个无效值，在读取访问不存在的设备的配置空间寄存器时返回 380 pub device_id: u16, // 设备ID，标志特定设备 381 pub command: u16, // 提供对设备生成和响应pci周期的能力的控制 向该寄存器写入0时，设备与pci总线断开除配置空间访问以外的所有连接 382 pub status: u16, // 用于记录pci总线相关时间的状态信息寄存器 383 pub revision_id: u8, // 修订ID，指定特定设备的修订标志符 384 pub prog_if: u8, // 编程接口字节，一个只读寄存器，指定设备具有的寄存器级别的编程接口（如果有的话） 385 pub subclass: u8, // 子类。指定设备执行的特定功能的只读寄存器 386 pub class_code: u8, // 类代码，一个只读寄存器，指定设备执行的功能类型 387 pub cache_line_size: u8, // 缓存线大小：以 32 位为单位指定系统缓存线大小。设备可以限制它可以支持的缓存线大小的数量，如果不支持的值写入该字段，设备将表现得好像写入了 0 值 388 pub latency_timer: u8, // 延迟计时器：以 PCI 总线时钟为单位指定延迟计时器。 389 pub header_type: u8, // 标头类型 a value of 0x0 specifies a general device, a value of 0x1 specifies a PCI-to-PCI bridge, and a value of 0x2 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device. 390 pub bist: u8, // Represents that status and allows control of a devices BIST (built-in self test). 391 // Here is the layout of the BIST register: 392 // | bit7 | bit6 | Bits 5-4 | Bits 3-0 | 393 // | BIST Capable | Start BIST | Reserved | Completion Code | 394 // for more details, please visit https://wiki.osdev.org/PCI 395 } 396 397 /// Pci_Device_Structure_General_Device PCI标准设备结构体 398 #[derive(Clone, Debug)] 399 pub struct PciDeviceStructureGeneralDevice { 400 pub common_header: PciDeviceStructureHeader, 401 // 中断结构体，包括legacy,msi,msix三种情况 402 pub irq_type: IrqType, 403 // 使用的中断号的vec集合 404 pub irq_vector: Vec<u16>, 405 pub standard_device_bar: PciStandardDeviceBar, 406 pub cardbus_cis_pointer: u32, // 指向卡信息结构，供在 CardBus 和 PCI 之间共享芯片的设备使用。 407 pub subsystem_vendor_id: u16, 408 pub subsystem_id: u16, 409 pub expansion_rom_base_address: u32, 410 pub capabilities_pointer: u8, 411 pub reserved0: u8, 412 pub reserved1: u16, 413 pub reserved2: u32, 414 pub interrupt_line: u8, // 指定设备的中断引脚连接到系统中断控制器的哪个输入，并由任何使用中断引脚的设备实现。对于 x86 架构，此寄存器对应于 PIC IRQ 编号 0-15（而不是 I/O APIC IRQ 编号），并且值0xFF定义为无连接。 415 pub interrupt_pin: u8, // 指定设备使用的中断引脚。其中值为0x1INTA#、0x2INTB#、0x3INTC#、0x4INTD#，0x0表示设备不使用中断引脚。 416 pub min_grant: u8, // 一个只读寄存器，用于指定设备所需的突发周期长度（以 1/4 微秒为单位）（假设时钟速率为 33 MHz） 417 pub max_latency: u8, // 一个只读寄存器，指定设备需要多长时间访问一次 PCI 总线（以 1/4 微秒为单位）。 418 } 419 impl PciDeviceStructure for PciDeviceStructureGeneralDevice { 420 #[inline(always)] 421 fn header_type(&self) -> HeaderType { 422 HeaderType::Standard 423 } 424 #[inline(always)] 425 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 426 Some(self) 427 } 428 #[inline(always)] 429 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 430 Some(self) 431 } 432 #[inline(always)] 433 fn common_header(&self) -> &PciDeviceStructureHeader { 434 &self.common_header 435 } 436 #[inline(always)] 437 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 438 &mut self.common_header 439 } 440 fn capabilities(&self) -> Option<CapabilityIterator> { 441 Some(CapabilityIterator { 442 bus_device_function: self.common_header.bus_device_function, 443 next_capability_offset: Some(self.capabilities_pointer), 444 }) 445 } 446 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 447 let common_header = &self.common_header; 448 match pci_bar_init(common_header.bus_device_function) { 449 Ok(bar) => { 450 self.standard_device_bar = bar; 451 Some(Ok(0)) 452 } 453 Err(e) => Some(Err(e)), 454 } 455 } 456 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 457 Some(&self.standard_device_bar) 458 } 459 #[inline(always)] 460 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 461 Some(&mut self.irq_type) 462 } 463 #[inline(always)] 464 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>> { 465 Some(&mut self.irq_vector) 466 } 467 } 468 469 /// Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci桥设备结构体 470 #[derive(Clone, Debug)] 471 pub struct PciDeviceStructurePciToPciBridge { 472 pub common_header: PciDeviceStructureHeader, 473 // 中断结构体，包括legacy,msi,msix三种情况 474 pub irq_type: IrqType, 475 // 使用的中断号的vec集合 476 pub irq_vector: Vec<u16>, 477 pub bar0: u32, 478 pub bar1: u32, 479 pub primary_bus_number: u8, 480 pub secondary_bus_number: u8, 481 pub subordinate_bus_number: u8, 482 pub secondary_latency_timer: u8, 483 pub io_base: u8, 484 pub io_limit: u8, 485 pub secondary_status: u16, 486 pub memory_base: u16, 487 pub memory_limit: u16, 488 pub prefetchable_memory_base: u16, 489 pub prefetchable_memory_limit: u16, 490 pub prefetchable_base_upper_32_bits: u32, 491 pub prefetchable_limit_upper_32_bits: u32, 492 pub io_base_upper_16_bits: u16, 493 pub io_limit_upper_16_bits: u16, 494 pub capability_pointer: u8, 495 pub reserved0: u8, 496 pub reserved1: u16, 497 pub expansion_rom_base_address: u32, 498 pub interrupt_line: u8, 499 pub interrupt_pin: u8, 500 pub bridge_control: u16, 501 } 502 impl PciDeviceStructure for PciDeviceStructurePciToPciBridge { 503 #[inline(always)] 504 fn header_type(&self) -> HeaderType { 505 HeaderType::PciPciBridge 506 } 507 #[inline(always)] 508 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 509 Some(self) 510 } 511 #[inline(always)] 512 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 513 Some(self) 514 } 515 #[inline(always)] 516 fn common_header(&self) -> &PciDeviceStructureHeader { 517 &self.common_header 518 } 519 #[inline(always)] 520 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 521 &mut self.common_header 522 } 523 #[inline(always)] 524 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 525 Some(&mut self.irq_type) 526 } 527 #[inline(always)] 528 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>> { 529 Some(&mut self.irq_vector) 530 } 531 } 532 /// Pci_Device_Structure_Pci_to_Cardbus_Bridge Pci_to_Cardbus桥设备结构体 533 #[derive(Clone, Debug)] 534 pub struct PciDeviceStructurePciToCardbusBridge { 535 pub common_header: PciDeviceStructureHeader, 536 pub cardbus_socket_ex_ca_base_address: u32, 537 pub offset_of_capabilities_list: u8, 538 pub reserved: u8, 539 pub secondary_status: u16, 540 pub pci_bus_number: u8, 541 pub card_bus_bus_number: u8, 542 pub subordinate_bus_number: u8, 543 pub card_bus_latency_timer: u8, 544 pub memory_base_address0: u32, 545 pub memory_limit0: u32, 546 pub memory_base_address1: u32, 547 pub memory_limit1: u32, 548 pub io_base_address0: u32, 549 pub io_limit0: u32, 550 pub io_base_address1: u32, 551 pub io_limit1: u32, 552 pub interrupt_line: u8, 553 pub interrupt_pin: u8, 554 pub bridge_control: u16, 555 pub subsystem_device_id: u16, 556 pub subsystem_vendor_id: u16, 557 pub pc_card_legacy_mode_base_address_16_bit: u32, 558 } 559 impl PciDeviceStructure for PciDeviceStructurePciToCardbusBridge { 560 #[inline(always)] 561 fn header_type(&self) -> HeaderType { 562 HeaderType::PciCardbusBridge 563 } 564 #[inline(always)] 565 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 566 Some(&self) 567 } 568 #[inline(always)] 569 fn as_pci_to_carbus_bridge_device_mut( 570 &mut self, 571 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 572 Some(self) 573 } 574 #[inline(always)] 575 fn common_header(&self) -> &PciDeviceStructureHeader { 576 &self.common_header 577 } 578 #[inline(always)] 579 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 580 &mut self.common_header 581 } 582 #[inline(always)] 583 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 584 None 585 } 586 #[inline(always)] 587 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>> { 588 None 589 } 590 } 591 592 /// 代表一个PCI segement greoup. 593 #[derive(Copy, Clone, Debug, PartialEq)] 594 pub struct PciRoot { 595 pub physical_address_base: u64, //物理地址，acpi获取 596 pub mmio_base: Option<*mut u32>, //映射后的虚拟地址，为方便访问数据这里转化成指针 597 pub segement_group_number: SegmentGroupNumber, //segement greoup的id 598 pub bus_begin: u8, //该分组中的最小bus 599 pub bus_end: u8, //该分组中的最大bus 600 } 601 ///线程间共享需要，该结构体只需要在初始化时写入数据，无需读写锁保证线程安全 602 unsafe impl Send for PciRoot {} 603 unsafe impl Sync for PciRoot {} 604 ///实现PciRoot的Display trait，自定义输出 605 impl Display for PciRoot { 606 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 607 write!( 608 f, 609 "PCI Root with segement:{}, bus begin at {}, bus end at {}, physical address at {:#x},mapped at {:#x}", 610 self.segement_group_number, self.bus_begin, self.bus_end, self.physical_address_base, self.mmio_base.unwrap() as usize 611 ) 612 } 613 } 614 615 impl PciRoot { 616 /// @brief 初始化结构体，获取ecam root所在物理地址后map到虚拟地址，再将该虚拟地址加入mmio_base变量 617 /// @return 成功返回结果，错误返回错误类型 618 pub fn new(segment_group_number: SegmentGroupNumber) -> Result<Self, PciError> { 619 let mut pci_root = PciArch::ecam_root(segment_group_number)?; 620 pci_root.map()?; 621 Ok(pci_root) 622 } 623 /// @brief 完成物理地址到虚拟地址的映射，并将虚拟地址加入mmio_base变量 624 /// @return 返回错误或Ok(0) 625 fn map(&mut self) -> Result<u8, PciError> { 626 //kdebug!("bus_begin={},bus_end={}", self.bus_begin,self.bus_end); 627 let bus_number = (self.bus_end - self.bus_begin) as u32 + 1; 628 let bus_number_double = (bus_number - 1) / 2 + 1; //一个bus占据1MB空间，计算全部bus占据空间相对于2MB空间的个数 629 let mut virtaddress: u64 = 0; 630 let vaddr_ptr = &mut virtaddress as *mut u64; 631 let mut virtsize: u64 = 0; 632 let virtsize_ptr = &mut virtsize as *mut u64; 633 let size = bus_number_double * PAGE_2M_SIZE; 634 unsafe { 635 let initial_mm_ptr = &mut initial_mm as *mut mm_struct; 636 if let Err(_) = 637 MMIO_POOL.create_mmio(size, (VM_IO | VM_DONTCOPY) as u64, vaddr_ptr, virtsize_ptr) 638 { 639 kerror!("Create mmio failed when initing ecam"); 640 return Err(PciError::CreateMmioError); 641 }; 642 //kdebug!("virtaddress={:#x},virtsize={:#x}",virtaddress,virtsize); 643 mm_map( 644 initial_mm_ptr, 645 virtaddress, 646 size as u64, 647 self.physical_address_base, 648 ); 649 } 650 self.mmio_base = Some(virtaddress as *mut u32); 651 Ok(0) 652 } 653 /// @brief 获得要操作的寄存器相对于mmio_offset的偏移量 654 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 655 /// @param register_offset 寄存器在设备中的offset 656 /// @return u32 要操作的寄存器相对于mmio_offset的偏移量 657 fn cam_offset(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 658 assert!(bus_device_function.valid()); 659 let bdf = ((bus_device_function.bus - self.bus_begin) as u32) << 8 660 | (bus_device_function.device as u32) << 3 661 | bus_device_function.function as u32; 662 let address = bdf << 12 | register_offset as u32; 663 // Ensure that address is word-aligned. 664 assert!(address & 0x3 == 0); 665 address 666 } 667 /// @brief 通过bus_device_function和offset读取相应位置寄存器的值（32位） 668 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 669 /// @param register_offset 寄存器在设备中的offset 670 /// @return u32 寄存器读值结果 671 pub fn read_config(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 672 let address = self.cam_offset(bus_device_function, register_offset); 673 unsafe { 674 // Right shift to convert from byte offset to word offset. 675 (self.mmio_base.unwrap().add((address >> 2) as usize)).read_volatile() 676 } 677 } 678 679 /// @brief 通过bus_device_function和offset写入相应位置寄存器值（32位） 680 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 681 /// @param register_offset 寄存器在设备中的offset 682 /// @param data 要写入的值 683 pub fn write_config( 684 &mut self, 685 bus_device_function: BusDeviceFunction, 686 register_offset: u16, 687 data: u32, 688 ) { 689 let address = self.cam_offset(bus_device_function, register_offset); 690 // Safe because both the `mmio_base` and the address offset are properly aligned, and the 691 // resulting pointer is within the MMIO range of the CAM. 692 unsafe { 693 // Right shift to convert from byte offset to word offset. 694 (self.mmio_base.unwrap().add((address >> 2) as usize)).write_volatile(data) 695 } 696 } 697 /// @brief 返回迭代器，遍历pcie设备的external_capabilities 698 pub fn external_capabilities( 699 &self, 700 bus_device_function: BusDeviceFunction, 701 ) -> ExternalCapabilityIterator { 702 ExternalCapabilityIterator { 703 root: self, 704 bus_device_function, 705 next_capability_offset: Some(0x100), 706 } 707 } 708 } 709 /// Gets the capabilities 'pointer' for the device function, if any. 710 /// @brief 获取第一个capability 的offset 711 /// @param bus_device_function PCI设备的唯一标识 712 /// @return Option<u8> offset 713 pub fn capabilities_offset(bus_device_function: BusDeviceFunction) -> Option<u8> { 714 let result = PciArch::read_config(&bus_device_function, STATUS_COMMAND_OFFSET); 715 let status: Status = Status::from_bits_truncate((result >> 16) as u16); 716 if status.contains(Status::CAPABILITIES_LIST) { 717 let cap_pointer = PciArch::read_config(&bus_device_function, 0x34) as u8 & 0xFC; 718 Some(cap_pointer) 719 } else { 720 None 721 } 722 } 723 724 /// @brief 读取pci设备头部 725 /// @param bus_device_function PCI设备的唯一标识 726 /// @param add_to_list 是否添加到链表 727 /// @return 返回的header(trait 类型) 728 fn pci_read_header( 729 bus_device_function: BusDeviceFunction, 730 add_to_list: bool, 731 ) -> Result<Box<dyn PciDeviceStructure>, PciError> { 732 // 先读取公共header 733 let result = PciArch::read_config(&bus_device_function, 0x00); 734 let vendor_id = result as u16; 735 let device_id = (result >> 16) as u16; 736 737 let result = PciArch::read_config(&bus_device_function, 0x04); 738 let command = result as u16; 739 let status = (result >> 16) as u16; 740 741 let result = PciArch::read_config(&bus_device_function, 0x08); 742 let revision_id = result as u8; 743 let prog_if = (result >> 8) as u8; 744 let subclass = (result >> 16) as u8; 745 let class_code = (result >> 24) as u8; 746 747 let result = PciArch::read_config(&bus_device_function, 0x0c); 748 let cache_line_size = result as u8; 749 let latency_timer = (result >> 8) as u8; 750 let header_type = (result >> 16) as u8; 751 let bist = (result >> 24) as u8; 752 if vendor_id == 0xffff { 753 return Err(PciError::GetWrongHeader); 754 } 755 let header = PciDeviceStructureHeader { 756 bus_device_function, 757 vendor_id, 758 device_id, 759 command, 760 status, 761 revision_id, 762 prog_if, 763 subclass, 764 class_code, 765 cache_line_size, 766 latency_timer, 767 header_type, 768 bist, 769 }; 770 match HeaderType::from(header_type & 0x7f) { 771 HeaderType::Standard => { 772 let general_device = pci_read_general_device_header(header, &bus_device_function); 773 let box_general_device = Box::new(general_device); 774 let box_general_device_clone = box_general_device.clone(); 775 if add_to_list { 776 PCI_DEVICE_LINKEDLIST.add(box_general_device); 777 } 778 Ok(box_general_device_clone) 779 } 780 HeaderType::PciPciBridge => { 781 let pci_to_pci_bridge = pci_read_pci_to_pci_bridge_header(header, &bus_device_function); 782 let box_pci_to_pci_bridge = Box::new(pci_to_pci_bridge); 783 let box_pci_to_pci_bridge_clone = box_pci_to_pci_bridge.clone(); 784 if add_to_list { 785 PCI_DEVICE_LINKEDLIST.add(box_pci_to_pci_bridge); 786 } 787 Ok(box_pci_to_pci_bridge_clone) 788 } 789 HeaderType::PciCardbusBridge => { 790 let pci_cardbus_bridge = 791 pci_read_pci_to_cardbus_bridge_header(header, &bus_device_function); 792 let box_pci_cardbus_bridge = Box::new(pci_cardbus_bridge); 793 let box_pci_cardbus_bridge_clone = box_pci_cardbus_bridge.clone(); 794 if add_to_list { 795 PCI_DEVICE_LINKEDLIST.add(box_pci_cardbus_bridge); 796 } 797 Ok(box_pci_cardbus_bridge_clone) 798 } 799 HeaderType::Unrecognised(_) => Err(PciError::UnrecognisedHeaderType), 800 } 801 } 802 803 /// @brief 读取type为0x0的pci设备的header 804 /// 本函数只应被 pci_read_header()调用 805 /// @param common_header 共有头部 806 /// @param bus_device_function PCI设备的唯一标识 807 /// @return Pci_Device_Structure_General_Device 标准设备头部 808 fn pci_read_general_device_header( 809 common_header: PciDeviceStructureHeader, 810 bus_device_function: &BusDeviceFunction, 811 ) -> PciDeviceStructureGeneralDevice { 812 let standard_device_bar = PciStandardDeviceBar::default(); 813 let cardbus_cis_pointer = PciArch::read_config(bus_device_function, 0x28); 814 815 let result = PciArch::read_config(bus_device_function, 0x2c); 816 let subsystem_vendor_id = result as u16; 817 let subsystem_id = (result >> 16) as u16; 818 819 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x30); 820 821 let result = PciArch::read_config(bus_device_function, 0x34); 822 let capabilities_pointer = result as u8; 823 let reserved0 = (result >> 8) as u8; 824 let reserved1 = (result >> 16) as u16; 825 826 let reserved2 = PciArch::read_config(bus_device_function, 0x38); 827 828 let result = PciArch::read_config(bus_device_function, 0x3c); 829 let interrupt_line = result as u8; 830 let interrupt_pin = (result >> 8) as u8; 831 let min_grant = (result >> 16) as u8; 832 let max_latency = (result >> 24) as u8; 833 PciDeviceStructureGeneralDevice { 834 common_header, 835 irq_type: IrqType::Unused, 836 irq_vector: Vec::new(), 837 standard_device_bar, 838 cardbus_cis_pointer, 839 subsystem_vendor_id, 840 subsystem_id, 841 expansion_rom_base_address, 842 capabilities_pointer, 843 reserved0, 844 reserved1, 845 reserved2, 846 interrupt_line, 847 interrupt_pin, 848 min_grant, 849 max_latency, 850 } 851 } 852 853 /// @brief 读取type为0x1的pci设备的header 854 /// 本函数只应被 pci_read_header()调用 855 /// @param common_header 共有头部 856 /// @param bus_device_function PCI设备的唯一标识 857 /// @return Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci 桥设备头部 858 fn pci_read_pci_to_pci_bridge_header( 859 common_header: PciDeviceStructureHeader, 860 bus_device_function: &BusDeviceFunction, 861 ) -> PciDeviceStructurePciToPciBridge { 862 let bar0 = PciArch::read_config(bus_device_function, 0x10); 863 let bar1 = PciArch::read_config(bus_device_function, 0x14); 864 865 let result = PciArch::read_config(bus_device_function, 0x18); 866 867 let primary_bus_number = result as u8; 868 let secondary_bus_number = (result >> 8) as u8; 869 let subordinate_bus_number = (result >> 16) as u8; 870 let secondary_latency_timer = (result >> 24) as u8; 871 872 let result = PciArch::read_config(bus_device_function, 0x1c); 873 let io_base = result as u8; 874 let io_limit = (result >> 8) as u8; 875 let secondary_status = (result >> 16) as u16; 876 877 let result = PciArch::read_config(bus_device_function, 0x20); 878 let memory_base = result as u16; 879 let memory_limit = (result >> 16) as u16; 880 881 let result = PciArch::read_config(bus_device_function, 0x24); 882 let prefetchable_memory_base = result as u16; 883 let prefetchable_memory_limit = (result >> 16) as u16; 884 885 let prefetchable_base_upper_32_bits = PciArch::read_config(bus_device_function, 0x28); 886 let prefetchable_limit_upper_32_bits = PciArch::read_config(bus_device_function, 0x2c); 887 888 let result = PciArch::read_config(bus_device_function, 0x30); 889 let io_base_upper_16_bits = result as u16; 890 let io_limit_upper_16_bits = (result >> 16) as u16; 891 892 let result = PciArch::read_config(bus_device_function, 0x34); 893 let capability_pointer = result as u8; 894 let reserved0 = (result >> 8) as u8; 895 let reserved1 = (result >> 16) as u16; 896 897 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x38); 898 899 let result = PciArch::read_config(bus_device_function, 0x3c); 900 let interrupt_line = result as u8; 901 let interrupt_pin = (result >> 8) as u8; 902 let bridge_control = (result >> 16) as u16; 903 PciDeviceStructurePciToPciBridge { 904 common_header, 905 irq_type: IrqType::Unused, 906 irq_vector: Vec::new(), 907 bar0, 908 bar1, 909 primary_bus_number, 910 secondary_bus_number, 911 subordinate_bus_number, 912 secondary_latency_timer, 913 io_base, 914 io_limit, 915 secondary_status, 916 memory_base, 917 memory_limit, 918 prefetchable_memory_base, 919 prefetchable_memory_limit, 920 prefetchable_base_upper_32_bits, 921 prefetchable_limit_upper_32_bits, 922 io_base_upper_16_bits, 923 io_limit_upper_16_bits, 924 capability_pointer, 925 reserved0, 926 reserved1, 927 expansion_rom_base_address, 928 interrupt_line, 929 interrupt_pin, 930 bridge_control, 931 } 932 } 933 934 /// @brief 读取type为0x2的pci设备的header 935 /// 本函数只应被 pci_read_header()调用 936 /// @param common_header 共有头部 937 /// @param bus_device_function PCI设备的唯一标识 938 /// @return Pci_Device_Structure_Pci_to_Cardbus_Bridge pci-to-cardbus 桥设备头部 939 fn pci_read_pci_to_cardbus_bridge_header( 940 common_header: PciDeviceStructureHeader, 941 busdevicefunction: &BusDeviceFunction, 942 ) -> PciDeviceStructurePciToCardbusBridge { 943 let cardbus_socket_ex_ca_base_address = PciArch::read_config(busdevicefunction, 0x10); 944 945 let result = PciArch::read_config(busdevicefunction, 0x14); 946 let offset_of_capabilities_list = result as u8; 947 let reserved = (result >> 8) as u8; 948 let secondary_status = (result >> 16) as u16; 949 950 let result = PciArch::read_config(busdevicefunction, 0x18); 951 let pci_bus_number = result as u8; 952 let card_bus_bus_number = (result >> 8) as u8; 953 let subordinate_bus_number = (result >> 16) as u8; 954 let card_bus_latency_timer = (result >> 24) as u8; 955 956 let memory_base_address0 = PciArch::read_config(busdevicefunction, 0x1c); 957 let memory_limit0 = PciArch::read_config(busdevicefunction, 0x20); 958 let memory_base_address1 = PciArch::read_config(busdevicefunction, 0x24); 959 let memory_limit1 = PciArch::read_config(busdevicefunction, 0x28); 960 961 let io_base_address0 = PciArch::read_config(busdevicefunction, 0x2c); 962 let io_limit0 = PciArch::read_config(busdevicefunction, 0x30); 963 let io_base_address1 = PciArch::read_config(busdevicefunction, 0x34); 964 let io_limit1 = PciArch::read_config(busdevicefunction, 0x38); 965 let result = PciArch::read_config(busdevicefunction, 0x3c); 966 let interrupt_line = result as u8; 967 let interrupt_pin = (result >> 8) as u8; 968 let bridge_control = (result >> 16) as u16; 969 970 let result = PciArch::read_config(busdevicefunction, 0x40); 971 let subsystem_device_id = result as u16; 972 let subsystem_vendor_id = (result >> 16) as u16; 973 974 let pc_card_legacy_mode_base_address_16_bit = PciArch::read_config(busdevicefunction, 0x44); 975 PciDeviceStructurePciToCardbusBridge { 976 common_header, 977 cardbus_socket_ex_ca_base_address, 978 offset_of_capabilities_list, 979 reserved, 980 secondary_status, 981 pci_bus_number, 982 card_bus_bus_number, 983 subordinate_bus_number, 984 card_bus_latency_timer, 985 memory_base_address0, 986 memory_limit0, 987 memory_base_address1, 988 memory_limit1, 989 io_base_address0, 990 io_limit0, 991 io_base_address1, 992 io_limit1, 993 interrupt_line, 994 interrupt_pin, 995 bridge_control, 996 subsystem_device_id, 997 subsystem_vendor_id, 998 pc_card_legacy_mode_base_address_16_bit, 999 } 1000 } 1001 1002 /// @brief 检查所有bus上的设备并将其加入链表 1003 /// @return 成功返回ok(),失败返回失败原因 1004 fn pci_check_all_buses() -> Result<u8, PciError> { 1005 kinfo!("Checking all devices in PCI bus..."); 1006 let busdevicefunction = BusDeviceFunction { 1007 bus: 0, 1008 device: 0, 1009 function: 0, 1010 }; 1011 let header = pci_read_header(busdevicefunction, false)?; 1012 let common_header = header.common_header(); 1013 pci_check_bus(0)?; 1014 if common_header.header_type & 0x80 != 0 { 1015 for function in 1..8 { 1016 pci_check_bus(function)?; 1017 } 1018 } 1019 Ok(0) 1020 } 1021 /// @brief 检查特定设备并将其加入链表 1022 /// @return 成功返回ok(),失败返回失败原因 1023 fn pci_check_function(busdevicefunction: BusDeviceFunction) -> Result<u8, PciError> { 1024 //kdebug!("PCI check function {}", busdevicefunction.function); 1025 let header = match pci_read_header(busdevicefunction, true) { 1026 Ok(header) => header, 1027 Err(PciError::GetWrongHeader) => { 1028 return Ok(255); 1029 } 1030 Err(e) => { 1031 return Err(e); 1032 } 1033 }; 1034 let common_header = header.common_header(); 1035 if (common_header.class_code == 0x06) 1036 && (common_header.subclass == 0x04 || common_header.subclass == 0x09) 1037 { 1038 let pci_to_pci_bridge = header 1039 .as_pci_to_pci_bridge_device() 1040 .ok_or(PciError::PciDeviceStructureTransformError)?; 1041 let secondary_bus = pci_to_pci_bridge.secondary_bus_number; 1042 pci_check_bus(secondary_bus)?; 1043 } 1044 Ok(0) 1045 } 1046 1047 /// @brief 检查device上的设备并将其加入链表 1048 /// @return 成功返回ok(),失败返回失败原因 1049 fn pci_check_device(bus: u8, device: u8) -> Result<u8, PciError> { 1050 //kdebug!("PCI check device {}", device); 1051 let busdevicefunction = BusDeviceFunction { 1052 bus, 1053 device, 1054 function: 0, 1055 }; 1056 let header = match pci_read_header(busdevicefunction, false) { 1057 Ok(header) => header, 1058 Err(PciError::GetWrongHeader) => { 1059 //设备不存在，直接返回即可，不用终止遍历 1060 return Ok(255); 1061 } 1062 Err(e) => { 1063 return Err(e); 1064 } 1065 }; 1066 pci_check_function(busdevicefunction)?; 1067 let common_header = header.common_header(); 1068 if common_header.header_type & 0x80 != 0 { 1069 kdebug!( 1070 "Detected multi func device in bus{},device{}", 1071 busdevicefunction.bus, 1072 busdevicefunction.device 1073 ); 1074 // 这是一个多function的设备，因此查询剩余的function 1075 for function in 1..8 { 1076 let busdevicefunction = BusDeviceFunction { 1077 bus, 1078 device, 1079 function, 1080 }; 1081 pci_check_function(busdevicefunction)?; 1082 } 1083 } 1084 Ok(0) 1085 } 1086 /// @brief 检查该bus上的设备并将其加入链表 1087 /// @return 成功返回ok(),失败返回失败原因 1088 fn pci_check_bus(bus: u8) -> Result<u8, PciError> { 1089 //kdebug!("PCI check bus {}", bus); 1090 for device in 0..32 { 1091 pci_check_device(bus, device)?; 1092 } 1093 Ok(0) 1094 } 1095 /// @brief pci初始化函数(for c) 1096 #[no_mangle] 1097 pub extern "C" fn rs_pci_init() { 1098 pci_init(); 1099 if PCI_ROOT_0.is_some() { 1100 kdebug!("{}", PCI_ROOT_0.unwrap()); 1101 //以下为ecam的读取寄存器值测试，经测试可正常读取 1102 // let bus_device_function = BusDeviceFunction { 1103 // bus: 0, 1104 // device: 2, 1105 // function: 0, 1106 // }; 1107 // kdebug!( 1108 // "Ecam read virtio-net device status={:#x}", 1109 // (PCI_ROOT_0.unwrap().read_config(bus_device_function, 4)>>16) as u16 1110 // ); 1111 } 1112 } 1113 /// @brief pci初始化函数 1114 pub fn pci_init() { 1115 kinfo!("Initializing PCI bus..."); 1116 if let Err(e) = pci_check_all_buses() { 1117 kerror!("pci init failed when checking bus because of error: {}", e); 1118 return; 1119 } 1120 kinfo!( 1121 "Total pci device and function num = {}", 1122 PCI_DEVICE_LINKEDLIST.num() 1123 ); 1124 let list = PCI_DEVICE_LINKEDLIST.read(); 1125 for box_pci_device in list.iter() { 1126 let common_header = box_pci_device.common_header(); 1127 match box_pci_device.header_type() { 1128 HeaderType::Standard if common_header.status & 0x10 != 0 => { 1129 kinfo!("Found pci standard device with class code ={} subclass={} status={:#x} cap_pointer={:#x} vendor={:#x}, device id={:#x},bdf={}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer,common_header.vendor_id, common_header.device_id,common_header.bus_device_function); 1130 } 1131 HeaderType::Standard => { 1132 kinfo!( 1133 "Found pci standard device with class code ={} subclass={} status={:#x} ", 1134 common_header.class_code, 1135 common_header.subclass, 1136 common_header.status 1137 ); 1138 } 1139 HeaderType::PciPciBridge if common_header.status & 0x10 != 0 => { 1140 kinfo!("Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} cap_pointer={:#x}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer); 1141 } 1142 HeaderType::PciPciBridge => { 1143 kinfo!( 1144 "Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} ", 1145 common_header.class_code, 1146 common_header.subclass, 1147 common_header.status 1148 ); 1149 } 1150 HeaderType::PciCardbusBridge => { 1151 kinfo!( 1152 "Found pcicardbus bridge device with class code ={} subclass={} status={:#x} ", 1153 common_header.class_code, 1154 common_header.subclass, 1155 common_header.status 1156 ); 1157 } 1158 HeaderType::Unrecognised(_) => {} 1159 } 1160 } 1161 kinfo!("PCI bus initialized."); 1162 } 1163 1164 /// An identifier for a PCI bus, device and function. 1165 /// PCI设备的唯一标识 1166 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1167 pub struct BusDeviceFunction { 1168 /// The PCI bus number, between 0 and 255. 1169 pub bus: u8, 1170 /// The device number on the bus, between 0 and 31. 1171 pub device: u8, 1172 /// The function number of the device, between 0 and 7. 1173 pub function: u8, 1174 } 1175 impl BusDeviceFunction { 1176 /// Returns whether the device and function numbers are valid, i.e. the device is between 0 and 1177 ///@brief 检测BusDeviceFunction实例是否有效 1178 ///@param self 1179 ///@return bool 是否有效 1180 #[allow(dead_code)] 1181 pub fn valid(&self) -> bool { 1182 self.device < 32 && self.function < 8 1183 } 1184 } 1185 ///实现BusDeviceFunction的Display trait，使其可以直接输出 1186 impl Display for BusDeviceFunction { 1187 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 1188 write!( 1189 f, 1190 "bus {} device {} function{}", 1191 self.bus, self.device, self.function 1192 ) 1193 } 1194 } 1195 /// The location allowed for a memory BAR. 1196 /// memory BAR的三种情况 1197 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1198 pub enum MemoryBarType { 1199 /// The BAR has a 32-bit address and can be mapped anywhere in 32-bit address space. 1200 Width32, 1201 /// The BAR must be mapped below 1MiB. 1202 Below1MiB, 1203 /// The BAR has a 64-bit address and can be mapped anywhere in 64-bit address space. 1204 Width64, 1205 } 1206 ///实现MemoryBarType与u8的类型转换 1207 impl From<MemoryBarType> for u8 { 1208 fn from(bar_type: MemoryBarType) -> Self { 1209 match bar_type { 1210 MemoryBarType::Width32 => 0, 1211 MemoryBarType::Below1MiB => 1, 1212 MemoryBarType::Width64 => 2, 1213 } 1214 } 1215 } 1216 ///实现MemoryBarType与u8的类型转换 1217 impl TryFrom<u8> for MemoryBarType { 1218 type Error = PciError; 1219 fn try_from(value: u8) -> Result<Self, Self::Error> { 1220 match value { 1221 0 => Ok(Self::Width32), 1222 1 => Ok(Self::Below1MiB), 1223 2 => Ok(Self::Width64), 1224 _ => Err(PciError::InvalidBarType), 1225 } 1226 } 1227 } 1228 1229 /// Information about a PCI Base Address Register. 1230 /// BAR的三种类型 Memory/IO/Unused 1231 #[derive(Clone, Debug, Eq, PartialEq)] 1232 pub enum BarInfo { 1233 /// The BAR is for a memory region. 1234 Memory { 1235 /// The size of the BAR address and where it can be located. 1236 address_type: MemoryBarType, 1237 /// If true, then reading from the region doesn't have side effects. The CPU may cache reads 1238 /// and merge repeated stores. 1239 prefetchable: bool, 1240 /// The memory address, always 16-byte aligned. 1241 address: u64, 1242 /// The size of the BAR in bytes. 1243 size: u32, 1244 /// The virtaddress for a memory bar(mapped). 1245 virtaddress: u64, 1246 }, 1247 /// The BAR is for an I/O region. 1248 IO { 1249 /// The I/O address, always 4-byte aligned. 1250 address: u32, 1251 /// The size of the BAR in bytes. 1252 size: u32, 1253 }, 1254 Unused, 1255 } 1256 1257 impl BarInfo { 1258 /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO 1259 /// BAR. 1260 ///@brief 得到某个bar的memory_address与size(前提是他的类型为Memory Bar) 1261 ///@param self 1262 ///@return Option<(u64, u32) 是Memory Bar返回内存地址与大小，不是则返回None 1263 pub fn memory_address_size(&self) -> Option<(u64, u32)> { 1264 if let Self::Memory { address, size, .. } = self { 1265 Some((*address, *size)) 1266 } else { 1267 None 1268 } 1269 } 1270 ///@brief 得到某个bar的virtaddress(前提是他的类型为Memory Bar) 1271 ///@param self 1272 ///@return Option<(u64) 是Memory Bar返回映射的虚拟地址，不是则返回None 1273 pub fn virtual_address(&self) -> Option<u64> { 1274 if let Self::Memory { virtaddress, .. } = self { 1275 Some(*virtaddress) 1276 } else { 1277 None 1278 } 1279 } 1280 } 1281 ///实现BarInfo的Display trait，自定义输出 1282 impl Display for BarInfo { 1283 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1284 match self { 1285 Self::Memory { 1286 address_type, 1287 prefetchable, 1288 address, 1289 size, 1290 virtaddress, 1291 } => write!( 1292 f, 1293 "Memory space at {:#010x}, size {}, type {:?}, prefetchable {},mapped at {:#x}", 1294 address, size, address_type, prefetchable, virtaddress 1295 ), 1296 Self::IO { address, size } => { 1297 write!(f, "I/O space at {:#010x}, size {}", address, size) 1298 } 1299 Self::Unused => { 1300 write!(f, "Unused bar") 1301 } 1302 } 1303 } 1304 } 1305 //todo 增加对桥的bar的支持 1306 pub trait PciDeviceBar {} 1307 ///一个普通PCI设备（非桥）有6个BAR寄存器，PciStandardDeviceBar存储其全部信息 1308 #[derive(Clone, Debug, Eq, PartialEq)] 1309 pub struct PciStandardDeviceBar { 1310 bar0: BarInfo, 1311 bar1: BarInfo, 1312 bar2: BarInfo, 1313 bar3: BarInfo, 1314 bar4: BarInfo, 1315 bar5: BarInfo, 1316 } 1317 1318 impl PciStandardDeviceBar { 1319 ///@brief 得到某个bar的barinfo 1320 ///@param self ，bar_index(0-5) 1321 ///@return Result<&BarInfo, PciError> bar_index在0-5则返回对应的bar_info结构体，超出范围则返回错误 1322 pub fn get_bar(&self, bar_index: u8) -> Result<&BarInfo, PciError> { 1323 match bar_index { 1324 0 => Ok(&self.bar0), 1325 1 => Ok(&self.bar1), 1326 2 => Ok(&self.bar2), 1327 3 => Ok(&self.bar3), 1328 4 => Ok(&self.bar4), 1329 5 => Ok(&self.bar5), 1330 _ => Err(PciError::InvalidBarType), 1331 } 1332 } 1333 } 1334 ///实现PciStandardDeviceBar的Display trait，使其可以直接输出 1335 impl Display for PciStandardDeviceBar { 1336 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1337 write!( 1338 f, 1339 "\r\nBar0:{}\r\n Bar1:{}\r\n Bar2:{}\r\n Bar3:{}\r\nBar4:{}\r\nBar5:{}", 1340 self.bar0, self.bar1, self.bar2, self.bar3, self.bar4, self.bar5 1341 ) 1342 } 1343 } 1344 ///实现PciStandardDeviceBar的Default trait，使其可以简单初始化 1345 impl Default for PciStandardDeviceBar { 1346 fn default() -> Self { 1347 PciStandardDeviceBar { 1348 bar0: BarInfo::Unused, 1349 bar1: BarInfo::Unused, 1350 bar2: BarInfo::Unused, 1351 bar3: BarInfo::Unused, 1352 bar4: BarInfo::Unused, 1353 bar5: BarInfo::Unused, 1354 } 1355 } 1356 } 1357 1358 ///@brief 将某个pci设备的bar寄存器读取值后映射到虚拟地址 1359 ///@param self ，bus_device_function PCI设备的唯一标识符 1360 ///@return Result<PciStandardDeviceBar, PciError> 成功则返回对应的PciStandardDeviceBar结构体，失败则返回错误类型 1361 pub fn pci_bar_init( 1362 bus_device_function: BusDeviceFunction, 1363 ) -> Result<PciStandardDeviceBar, PciError> { 1364 let mut device_bar: PciStandardDeviceBar = PciStandardDeviceBar::default(); 1365 let mut bar_index_ignore: u8 = 255; 1366 for bar_index in 0..6 { 1367 if bar_index == bar_index_ignore { 1368 continue; 1369 } 1370 let bar_info; 1371 let mut virtaddress: u64 = 0; 1372 let bar_orig = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1373 PciArch::write_config( 1374 &bus_device_function, 1375 BAR0_OFFSET + 4 * bar_index, 1376 0xffffffff, 1377 ); 1378 let size_mask = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1379 // A wrapping add is necessary to correctly handle the case of unused BARs, which read back 1380 // as 0, and should be treated as size 0. 1381 let size = (!(size_mask & 0xfffffff0)).wrapping_add(1); 1382 //kdebug!("bar_orig:{:#x},size: {:#x}", bar_orig,size); 1383 // Restore the original value. 1384 PciArch::write_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index, bar_orig); 1385 if size == 0 { 1386 continue; 1387 } 1388 if bar_orig & 0x00000001 == 0x00000001 { 1389 // I/O space 1390 let address = bar_orig & 0xfffffffc; 1391 bar_info = BarInfo::IO { address, size }; 1392 } else { 1393 // Memory space 1394 let mut address = u64::from(bar_orig & 0xfffffff0); 1395 let prefetchable = bar_orig & 0x00000008 != 0; 1396 let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?; 1397 if address_type == MemoryBarType::Width64 { 1398 if bar_index >= 5 { 1399 return Err(PciError::InvalidBarType); 1400 } 1401 let address_top = 1402 PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * (bar_index + 1)); 1403 address |= u64::from(address_top) << 32; 1404 bar_index_ignore = bar_index + 1; //下个bar跳过，因为64位的memory bar覆盖了两个bar 1405 } 1406 let pci_address = PciAddr::new(address as usize); 1407 address = PciArch::address_pci_to_physical(pci_address) as u64; //PCI总线域物理地址转换为存储器域物理地址 1408 unsafe { 1409 let vaddr_ptr = &mut virtaddress as *mut u64; 1410 let mut virtsize: u64 = 0; 1411 let virtsize_ptr = &mut virtsize as *mut u64; 1412 let initial_mm_ptr = &mut initial_mm as *mut mm_struct; 1413 //kdebug!("size want={:#x}", size); 1414 if let Err(_) = MMIO_POOL.create_mmio( 1415 size, 1416 (VM_IO | VM_DONTCOPY) as u64, 1417 vaddr_ptr, 1418 virtsize_ptr, 1419 ) { 1420 kerror!("Create mmio failed when initing pci bar"); 1421 return Err(PciError::CreateMmioError); 1422 }; 1423 //kdebug!("virtaddress={:#x},virtsize={:#x}",virtaddress,virtsize); 1424 mm_map(initial_mm_ptr, virtaddress, size as u64, address); 1425 } 1426 bar_info = BarInfo::Memory { 1427 address_type, 1428 prefetchable, 1429 address, 1430 size, 1431 virtaddress, 1432 }; 1433 } 1434 match bar_index { 1435 0 => { 1436 device_bar.bar0 = bar_info; 1437 } 1438 1 => { 1439 device_bar.bar1 = bar_info; 1440 } 1441 2 => { 1442 device_bar.bar2 = bar_info; 1443 } 1444 3 => { 1445 device_bar.bar3 = bar_info; 1446 } 1447 4 => { 1448 device_bar.bar4 = bar_info; 1449 } 1450 5 => { 1451 device_bar.bar5 = bar_info; 1452 } 1453 _ => {} 1454 } 1455 } 1456 kdebug!("pci_device_bar:{}", device_bar); 1457 return Ok(device_bar); 1458 } 1459 1460 /// Information about a PCI device capability. 1461 /// PCI设备的capability的信息 1462 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1463 pub struct CapabilityInfo { 1464 /// The offset of the capability in the PCI configuration space of the device function. 1465 pub offset: u8, 1466 /// The ID of the capability. 1467 pub id: u8, 1468 /// The third and fourth bytes of the capability, to save reading them again. 1469 pub private_header: u16, 1470 } 1471 1472 /// Iterator over capabilities for a device. 1473 /// 创建迭代器以遍历PCI设备的capability 1474 #[derive(Debug)] 1475 pub struct CapabilityIterator { 1476 pub bus_device_function: BusDeviceFunction, 1477 pub next_capability_offset: Option<u8>, 1478 } 1479 1480 impl Iterator for CapabilityIterator { 1481 type Item = CapabilityInfo; 1482 fn next(&mut self) -> Option<Self::Item> { 1483 let offset = self.next_capability_offset?; 1484 1485 // Read the first 4 bytes of the capability. 1486 let capability_header = PciArch::read_config(&self.bus_device_function, offset); 1487 let id = capability_header as u8; 1488 let next_offset = (capability_header >> 8) as u8; 1489 let private_header = (capability_header >> 16) as u16; 1490 1491 self.next_capability_offset = if next_offset == 0 { 1492 None 1493 } else if next_offset < 64 || next_offset & 0x3 != 0 { 1494 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1495 None 1496 } else { 1497 Some(next_offset) 1498 }; 1499 1500 Some(CapabilityInfo { 1501 offset, 1502 id, 1503 private_header, 1504 }) 1505 } 1506 } 1507 1508 /// Information about a PCIe device capability. 1509 /// PCIe设备的external capability的信息 1510 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1511 pub struct ExternalCapabilityInfo { 1512 /// The offset of the capability in the PCI configuration space of the device function. 1513 pub offset: u16, 1514 /// The ID of the capability. 1515 pub id: u16, 1516 /// The third and fourth bytes of the capability, to save reading them again. 1517 pub capability_version: u8, 1518 } 1519 1520 /// Iterator over capabilities for a device. 1521 /// 创建迭代器以遍历PCIe设备的external capability 1522 #[derive(Debug)] 1523 pub struct ExternalCapabilityIterator<'a> { 1524 pub root: &'a PciRoot, 1525 pub bus_device_function: BusDeviceFunction, 1526 pub next_capability_offset: Option<u16>, 1527 } 1528 impl<'a> Iterator for ExternalCapabilityIterator<'a> { 1529 type Item = ExternalCapabilityInfo; 1530 fn next(&mut self) -> Option<Self::Item> { 1531 let offset = self.next_capability_offset?; 1532 1533 // Read the first 4 bytes of the capability. 1534 let capability_header = self.root.read_config(self.bus_device_function, offset); 1535 let id = capability_header as u16; 1536 let next_offset = (capability_header >> 20) as u16; 1537 let capability_version = ((capability_header >> 16) & 0xf) as u8; 1538 1539 self.next_capability_offset = if next_offset == 0 { 1540 None 1541 } else if next_offset < 0x100 || next_offset & 0x3 != 0 { 1542 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1543 None 1544 } else { 1545 Some(next_offset) 1546 }; 1547 1548 Some(ExternalCapabilityInfo { 1549 offset, 1550 id, 1551 capability_version, 1552 }) 1553 } 1554 } 1555