1 #![allow(dead_code)] 2 // 目前仅支持单主桥单Segment 3 4 use super::pci_irq::{IrqType, PciIrqError}; 5 use crate::arch::{PciArch, TraitPciArch}; 6 use crate::include::bindings::bindings::PAGE_2M_SIZE; 7 use crate::libs::rwlock::{RwLock, RwLockReadGuard, RwLockWriteGuard}; 8 9 use crate::mm::mmio_buddy::{mmio_pool, MMIOSpaceGuard}; 10 11 use crate::mm::{PhysAddr, VirtAddr}; 12 use crate::{kdebug, kerror, kinfo, kwarn}; 13 use alloc::sync::Arc; 14 use alloc::vec::Vec; 15 use alloc::{boxed::Box, collections::LinkedList}; 16 use bitflags::bitflags; 17 18 use core::{ 19 convert::TryFrom, 20 fmt::{self, Debug, Display, Formatter}, 21 }; 22 // PCI_DEVICE_LINKEDLIST 添加了读写锁的全局链表，里面存储了检索到的PCI设备结构体 23 // PCI_ROOT_0 Segment为0的全局PciRoot 24 lazy_static! { 25 pub static ref PCI_DEVICE_LINKEDLIST: PciDeviceLinkedList = PciDeviceLinkedList::new(); 26 pub static ref PCI_ROOT_0: Option<PciRoot> = { 27 match PciRoot::new(0) { 28 Ok(root) => Some(root), 29 Err(err) => { 30 kerror!("Pci_root init failed because of error: {}", err); 31 None 32 } 33 } 34 }; 35 } 36 /// PCI域地址 37 #[derive(Clone, Copy, Eq, Ord, PartialEq, PartialOrd)] 38 #[repr(transparent)] 39 pub struct PciAddr(usize); 40 41 impl PciAddr { 42 #[inline(always)] 43 pub const fn new(address: usize) -> Self { 44 Self(address) 45 } 46 47 /// @brief 获取PCI域地址的值 48 #[inline(always)] 49 pub fn data(&self) -> usize { 50 self.0 51 } 52 53 /// @brief 将PCI域地址加上一个偏移量 54 #[inline(always)] 55 pub fn add(self, offset: usize) -> Self { 56 Self(self.0 + offset) 57 } 58 59 /// @brief 判断PCI域地址是否按照指定要求对齐 60 #[inline(always)] 61 pub fn check_aligned(&self, align: usize) -> bool { 62 return self.0 & (align - 1) == 0; 63 } 64 } 65 impl Debug for PciAddr { 66 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { 67 write!(f, "PciAddr({:#x})", self.0) 68 } 69 } 70 71 /// 添加了读写锁的链表，存储PCI设备结构体 72 pub struct PciDeviceLinkedList { 73 list: RwLock<LinkedList<Box<dyn PciDeviceStructure>>>, 74 } 75 76 impl PciDeviceLinkedList { 77 /// @brief 初始化结构体 78 fn new() -> Self { 79 PciDeviceLinkedList { 80 list: RwLock::new(LinkedList::new()), 81 } 82 } 83 /// @brief 获取可读的linkedlist(读锁守卫) 84 /// @return RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> 读锁守卫 85 pub fn read(&self) -> RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 86 self.list.read() 87 } 88 /// @brief 获取可写的linkedlist(写锁守卫) 89 /// @return RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> 写锁守卫 90 pub fn write(&self) -> RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 91 self.list.write() 92 } 93 /// @brief 获取链表中PCI结构体数目 94 /// @return usize 链表中PCI结构体数目 95 pub fn num(&self) -> usize { 96 let list = self.list.read(); 97 list.len() 98 } 99 /// @brief 添加Pci设备结构体到链表中 100 pub fn add(&self, device: Box<dyn PciDeviceStructure>) { 101 let mut list = self.list.write(); 102 list.push_back(device); 103 } 104 } 105 106 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其可变引用 107 /// @param list 链表的写锁守卫 108 /// @param class_code 寄存器值 109 /// @param subclass 寄存器值，与class_code一起确定设备类型 110 /// @return Vec<&'a mut Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的可变引用的容器 111 pub fn get_pci_device_structure_mut<'a>( 112 list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 113 class_code: u8, 114 subclass: u8, 115 ) -> Vec<&'a mut Box<(dyn PciDeviceStructure)>> { 116 let mut result = Vec::new(); 117 for box_pci_device_structure in list.iter_mut() { 118 let common_header = (*box_pci_device_structure).common_header(); 119 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 120 result.push(box_pci_device_structure); 121 } 122 } 123 result 124 } 125 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其不可变引用 126 /// @param list 链表的读锁守卫 127 /// @param class_code 寄存器值 128 /// @param subclass 寄存器值，与class_code一起确定设备类型 129 /// @return Vec<&'a Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的不可变引用的容器 130 pub fn get_pci_device_structure<'a>( 131 list: &'a mut RwLockReadGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 132 class_code: u8, 133 subclass: u8, 134 ) -> Vec<&'a Box<(dyn PciDeviceStructure)>> { 135 let mut result = Vec::new(); 136 for box_pci_device_structure in list.iter() { 137 let common_header = (*box_pci_device_structure).common_header(); 138 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 139 result.push(box_pci_device_structure); 140 } 141 } 142 result 143 } 144 145 //Bar0寄存器的offset 146 const BAR0_OFFSET: u8 = 0x10; 147 //Status、Command寄存器的offset 148 const STATUS_COMMAND_OFFSET: u8 = 0x04; 149 /// ID for vendor-specific PCI capabilities.(Virtio Capabilities) 150 pub const PCI_CAP_ID_VNDR: u8 = 0x09; 151 pub const PCI_CAP_ID_MSI: u8 = 0x05; 152 pub const PCI_CAP_ID_MSIX: u8 = 0x11; 153 pub const PORT_PCI_CONFIG_ADDRESS: u16 = 0xcf8; 154 pub const PORT_PCI_CONFIG_DATA: u16 = 0xcfc; 155 // pci设备分组的id 156 pub type SegmentGroupNumber = u16; //理论上最多支持65535个Segment_Group 157 158 bitflags! { 159 /// The status register in PCI configuration space. 160 pub struct Status: u16 { 161 // Bits 0-2 are reserved. 162 /// The state of the device's INTx# signal. 163 const INTERRUPT_STATUS = 1 << 3; 164 /// The device has a linked list of capabilities. 165 const CAPABILITIES_LIST = 1 << 4; 166 /// The device is capabile of running at 66 MHz rather than 33 MHz. 167 const MHZ_66_CAPABLE = 1 << 5; 168 // Bit 6 is reserved. 169 /// The device can accept fast back-to-back transactions not from the same agent. 170 const FAST_BACK_TO_BACK_CAPABLE = 1 << 7; 171 /// The bus agent observed a parity error (if parity error handling is enabled). 172 const MASTER_DATA_PARITY_ERROR = 1 << 8; 173 // Bits 9-10 are DEVSEL timing. 174 /// A target device terminated a transaction with target-abort. 175 const SIGNALED_TARGET_ABORT = 1 << 11; 176 /// A master device transaction was terminated with target-abort. 177 const RECEIVED_TARGET_ABORT = 1 << 12; 178 /// A master device transaction was terminated with master-abort. 179 const RECEIVED_MASTER_ABORT = 1 << 13; 180 /// A device asserts SERR#. 181 const SIGNALED_SYSTEM_ERROR = 1 << 14; 182 /// The device detects a parity error, even if parity error handling is disabled. 183 const DETECTED_PARITY_ERROR = 1 << 15; 184 } 185 } 186 187 bitflags! { 188 /// The command register in PCI configuration space. 189 pub struct Command: u16 { 190 /// The device can respond to I/O Space accesses. 191 const IO_SPACE = 1 << 0; 192 /// The device can respond to Memory Space accesses. 193 const MEMORY_SPACE = 1 << 1; 194 /// The device can behave as a bus master. 195 const BUS_MASTER = 1 << 2; 196 /// The device can monitor Special Cycle operations. 197 const SPECIAL_CYCLES = 1 << 3; 198 /// The device can generate the Memory Write and Invalidate command. 199 const MEMORY_WRITE_AND_INVALIDATE_ENABLE = 1 << 4; 200 /// The device will snoop palette register data. 201 const VGA_PALETTE_SNOOP = 1 << 5; 202 /// The device should take its normal action when a parity error is detected. 203 const PARITY_ERROR_RESPONSE = 1 << 6; 204 // Bit 7 is reserved. 205 /// The SERR# driver is enabled. 206 const SERR_ENABLE = 1 << 8; 207 /// The device is allowed to generate fast back-to-back transactions. 208 const FAST_BACK_TO_BACK_ENABLE = 1 << 9; 209 /// Assertion of the device's INTx# signal is disabled. 210 const INTERRUPT_DISABLE = 1 << 10; 211 } 212 } 213 214 /// The type of a PCI device function header. 215 /// 标头类型/设备类型 216 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 217 pub enum HeaderType { 218 /// A normal PCI device. 219 Standard, 220 /// A PCI to PCI bridge. 221 PciPciBridge, 222 /// A PCI to CardBus bridge. 223 PciCardbusBridge, 224 /// Unrecognised header type. 225 Unrecognised(u8), 226 } 227 /// u8到HeaderType的转换 228 impl From<u8> for HeaderType { 229 fn from(value: u8) -> Self { 230 match value { 231 0x00 => Self::Standard, 232 0x01 => Self::PciPciBridge, 233 0x02 => Self::PciCardbusBridge, 234 _ => Self::Unrecognised(value), 235 } 236 } 237 } 238 /// Pci可能触发的各种错误 239 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 240 pub enum PciError { 241 /// The device reported an invalid BAR type. 242 InvalidBarType, 243 CreateMmioError, 244 InvalidBusDeviceFunction, 245 SegmentNotFound, 246 McfgTableNotFound, 247 GetWrongHeader, 248 UnrecognisedHeaderType, 249 PciDeviceStructureTransformError, 250 PciIrqError(PciIrqError), 251 } 252 ///实现PciError的Display trait，使其可以直接输出 253 impl Display for PciError { 254 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 255 match self { 256 Self::InvalidBarType => write!(f, "Invalid PCI BAR type."), 257 Self::CreateMmioError => write!(f, "Error occurred while creating mmio."), 258 Self::InvalidBusDeviceFunction => write!(f, "Found invalid BusDeviceFunction."), 259 Self::SegmentNotFound => write!(f, "Target segment not found"), 260 Self::McfgTableNotFound => write!(f, "ACPI MCFG Table not found"), 261 Self::GetWrongHeader => write!(f, "GetWrongHeader with vendor id 0xffff"), 262 Self::UnrecognisedHeaderType => write!(f, "Found device with unrecognised header type"), 263 Self::PciDeviceStructureTransformError => { 264 write!(f, "Found None When transform Pci device structure") 265 } 266 Self::PciIrqError(err) => write!(f, "Error occurred while setting irq :{:?}.", err), 267 } 268 } 269 } 270 271 /// trait类型Pci_Device_Structure表示pci设备，动态绑定三种具体设备类型：Pci_Device_Structure_General_Device、Pci_Device_Structure_Pci_to_Pci_Bridge、Pci_Device_Structure_Pci_to_Cardbus_Bridge 272 pub trait PciDeviceStructure: Send + Sync { 273 /// @brief 获取设备类型 274 /// @return HeaderType 设备类型 275 fn header_type(&self) -> HeaderType; 276 /// @brief 当其为standard设备时返回&Pci_Device_Structure_General_Device，其余情况返回None 277 #[inline(always)] 278 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 279 None 280 } 281 /// @brief 当其为pci to pci bridge设备时返回&Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 282 #[inline(always)] 283 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 284 None 285 } 286 /// @brief 当其为pci to cardbus bridge设备时返回&Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 287 #[inline(always)] 288 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 289 None 290 } 291 /// @brief 获取Pci设备共有的common_header 292 /// @return 返回其不可变引用 293 fn common_header(&self) -> &PciDeviceStructureHeader; 294 /// @brief 当其为standard设备时返回&mut Pci_Device_Structure_General_Device，其余情况返回None 295 #[inline(always)] 296 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 297 None 298 } 299 /// @brief 当其为pci to pci bridge设备时返回&mut Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 300 #[inline(always)] 301 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 302 None 303 } 304 /// @brief 当其为pci to cardbus bridge设备时返回&mut Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 305 #[inline(always)] 306 fn as_pci_to_carbus_bridge_device_mut( 307 &mut self, 308 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 309 None 310 } 311 /// @brief 返回迭代器，遍历capabilities 312 fn capabilities(&self) -> Option<CapabilityIterator> { 313 None 314 } 315 /// @brief 获取Status、Command寄存器的值 316 fn status_command(&self) -> (Status, Command) { 317 let common_header = self.common_header(); 318 let status = Status::from_bits_truncate(common_header.status); 319 let command = Command::from_bits_truncate(common_header.command); 320 (status, command) 321 } 322 /// @brief 设置Command寄存器的值 323 fn set_command(&mut self, command: Command) { 324 let common_header = self.common_header_mut(); 325 let command = command.bits(); 326 common_header.command = command; 327 PciArch::write_config( 328 &common_header.bus_device_function, 329 STATUS_COMMAND_OFFSET, 330 command as u32, 331 ); 332 } 333 /// @brief 获取Pci设备共有的common_header 334 /// @return 返回其可变引用 335 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader; 336 337 /// @brief 读取standard设备的bar寄存器，映射后将结果加入结构体的standard_device_bar变量 338 /// @return 只有standard设备才返回成功或者错误，其余返回None 339 #[inline(always)] 340 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 341 None 342 } 343 /// @brief 获取PCI设备的bar寄存器的引用 344 /// @return 345 #[inline(always)] 346 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 347 None 348 } 349 /// @brief 通过设置该pci设备的command 350 fn enable_master(&mut self) { 351 self.set_command(Command::IO_SPACE | Command::MEMORY_SPACE | Command::BUS_MASTER); 352 } 353 /// @brief 寻找设备的msix空间的offset 354 fn msix_capability_offset(&self) -> Option<u8> { 355 for capability in self.capabilities()? { 356 if capability.id == PCI_CAP_ID_MSIX { 357 return Some(capability.offset); 358 } 359 } 360 None 361 } 362 /// @brief 寻找设备的msi空间的offset 363 fn msi_capability_offset(&self) -> Option<u8> { 364 for capability in self.capabilities()? { 365 if capability.id == PCI_CAP_ID_MSI { 366 return Some(capability.offset); 367 } 368 } 369 None 370 } 371 /// @brief 返回结构体中的irq_type的可变引用 372 fn irq_type_mut(&mut self) -> Option<&mut IrqType>; 373 /// @brief 返回结构体中的irq_vector的可变引用 374 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>>; 375 } 376 377 /// Pci_Device_Structure_Header PCI设备结构体共有的头部 378 #[derive(Clone, Debug)] 379 pub struct PciDeviceStructureHeader { 380 // ==== busdevicefunction变量表示该结构体所处的位置 381 pub bus_device_function: BusDeviceFunction, 382 pub vendor_id: u16, // 供应商ID 0xffff是一个无效值，在读取访问不存在的设备的配置空间寄存器时返回 383 pub device_id: u16, // 设备ID，标志特定设备 384 pub command: u16, // 提供对设备生成和响应pci周期的能力的控制 向该寄存器写入0时，设备与pci总线断开除配置空间访问以外的所有连接 385 pub status: u16, // 用于记录pci总线相关时间的状态信息寄存器 386 pub revision_id: u8, // 修订ID，指定特定设备的修订标志符 387 pub prog_if: u8, // 编程接口字节，一个只读寄存器，指定设备具有的寄存器级别的编程接口（如果有的话） 388 pub subclass: u8, // 子类。指定设备执行的特定功能的只读寄存器 389 pub class_code: u8, // 类代码，一个只读寄存器，指定设备执行的功能类型 390 pub cache_line_size: u8, // 缓存线大小：以 32 位为单位指定系统缓存线大小。设备可以限制它可以支持的缓存线大小的数量，如果不支持的值写入该字段，设备将表现得好像写入了 0 值 391 pub latency_timer: u8, // 延迟计时器：以 PCI 总线时钟为单位指定延迟计时器。 392 pub header_type: u8, // 标头类型 a value of 0x0 specifies a general device, a value of 0x1 specifies a PCI-to-PCI bridge, and a value of 0x2 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device. 393 pub bist: u8, // Represents that status and allows control of a devices BIST (built-in self test). 394 // Here is the layout of the BIST register: 395 // | bit7 | bit6 | Bits 5-4 | Bits 3-0 | 396 // | BIST Capable | Start BIST | Reserved | Completion Code | 397 // for more details, please visit https://wiki.osdev.org/PCI 398 } 399 400 /// Pci_Device_Structure_General_Device PCI标准设备结构体 401 #[derive(Clone, Debug)] 402 pub struct PciDeviceStructureGeneralDevice { 403 pub common_header: PciDeviceStructureHeader, 404 // 中断结构体，包括legacy,msi,msix三种情况 405 pub irq_type: IrqType, 406 // 使用的中断号的vec集合 407 pub irq_vector: Vec<u16>, 408 pub standard_device_bar: PciStandardDeviceBar, 409 pub cardbus_cis_pointer: u32, // 指向卡信息结构，供在 CardBus 和 PCI 之间共享芯片的设备使用。 410 pub subsystem_vendor_id: u16, 411 pub subsystem_id: u16, 412 pub expansion_rom_base_address: u32, 413 pub capabilities_pointer: u8, 414 pub reserved0: u8, 415 pub reserved1: u16, 416 pub reserved2: u32, 417 pub interrupt_line: u8, // 指定设备的中断引脚连接到系统中断控制器的哪个输入，并由任何使用中断引脚的设备实现。对于 x86 架构，此寄存器对应于 PIC IRQ 编号 0-15（而不是 I/O APIC IRQ 编号），并且值0xFF定义为无连接。 418 pub interrupt_pin: u8, // 指定设备使用的中断引脚。其中值为0x1INTA#、0x2INTB#、0x3INTC#、0x4INTD#，0x0表示设备不使用中断引脚。 419 pub min_grant: u8, // 一个只读寄存器，用于指定设备所需的突发周期长度（以 1/4 微秒为单位）（假设时钟速率为 33 MHz） 420 pub max_latency: u8, // 一个只读寄存器，指定设备需要多长时间访问一次 PCI 总线（以 1/4 微秒为单位）。 421 } 422 impl PciDeviceStructure for PciDeviceStructureGeneralDevice { 423 #[inline(always)] 424 fn header_type(&self) -> HeaderType { 425 HeaderType::Standard 426 } 427 #[inline(always)] 428 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 429 Some(self) 430 } 431 #[inline(always)] 432 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 433 Some(self) 434 } 435 #[inline(always)] 436 fn common_header(&self) -> &PciDeviceStructureHeader { 437 &self.common_header 438 } 439 #[inline(always)] 440 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 441 &mut self.common_header 442 } 443 fn capabilities(&self) -> Option<CapabilityIterator> { 444 Some(CapabilityIterator { 445 bus_device_function: self.common_header.bus_device_function, 446 next_capability_offset: Some(self.capabilities_pointer), 447 }) 448 } 449 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 450 let common_header = &self.common_header; 451 match pci_bar_init(common_header.bus_device_function) { 452 Ok(bar) => { 453 self.standard_device_bar = bar; 454 Some(Ok(0)) 455 } 456 Err(e) => Some(Err(e)), 457 } 458 } 459 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 460 Some(&self.standard_device_bar) 461 } 462 #[inline(always)] 463 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 464 Some(&mut self.irq_type) 465 } 466 #[inline(always)] 467 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>> { 468 Some(&mut self.irq_vector) 469 } 470 } 471 472 /// Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci桥设备结构体 473 #[derive(Clone, Debug)] 474 pub struct PciDeviceStructurePciToPciBridge { 475 pub common_header: PciDeviceStructureHeader, 476 // 中断结构体，包括legacy,msi,msix三种情况 477 pub irq_type: IrqType, 478 // 使用的中断号的vec集合 479 pub irq_vector: Vec<u16>, 480 pub bar0: u32, 481 pub bar1: u32, 482 pub primary_bus_number: u8, 483 pub secondary_bus_number: u8, 484 pub subordinate_bus_number: u8, 485 pub secondary_latency_timer: u8, 486 pub io_base: u8, 487 pub io_limit: u8, 488 pub secondary_status: u16, 489 pub memory_base: u16, 490 pub memory_limit: u16, 491 pub prefetchable_memory_base: u16, 492 pub prefetchable_memory_limit: u16, 493 pub prefetchable_base_upper_32_bits: u32, 494 pub prefetchable_limit_upper_32_bits: u32, 495 pub io_base_upper_16_bits: u16, 496 pub io_limit_upper_16_bits: u16, 497 pub capability_pointer: u8, 498 pub reserved0: u8, 499 pub reserved1: u16, 500 pub expansion_rom_base_address: u32, 501 pub interrupt_line: u8, 502 pub interrupt_pin: u8, 503 pub bridge_control: u16, 504 } 505 impl PciDeviceStructure for PciDeviceStructurePciToPciBridge { 506 #[inline(always)] 507 fn header_type(&self) -> HeaderType { 508 HeaderType::PciPciBridge 509 } 510 #[inline(always)] 511 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 512 Some(self) 513 } 514 #[inline(always)] 515 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 516 Some(self) 517 } 518 #[inline(always)] 519 fn common_header(&self) -> &PciDeviceStructureHeader { 520 &self.common_header 521 } 522 #[inline(always)] 523 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 524 &mut self.common_header 525 } 526 #[inline(always)] 527 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 528 Some(&mut self.irq_type) 529 } 530 #[inline(always)] 531 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>> { 532 Some(&mut self.irq_vector) 533 } 534 } 535 /// Pci_Device_Structure_Pci_to_Cardbus_Bridge Pci_to_Cardbus桥设备结构体 536 #[derive(Clone, Debug)] 537 pub struct PciDeviceStructurePciToCardbusBridge { 538 pub common_header: PciDeviceStructureHeader, 539 pub cardbus_socket_ex_ca_base_address: u32, 540 pub offset_of_capabilities_list: u8, 541 pub reserved: u8, 542 pub secondary_status: u16, 543 pub pci_bus_number: u8, 544 pub card_bus_bus_number: u8, 545 pub subordinate_bus_number: u8, 546 pub card_bus_latency_timer: u8, 547 pub memory_base_address0: u32, 548 pub memory_limit0: u32, 549 pub memory_base_address1: u32, 550 pub memory_limit1: u32, 551 pub io_base_address0: u32, 552 pub io_limit0: u32, 553 pub io_base_address1: u32, 554 pub io_limit1: u32, 555 pub interrupt_line: u8, 556 pub interrupt_pin: u8, 557 pub bridge_control: u16, 558 pub subsystem_device_id: u16, 559 pub subsystem_vendor_id: u16, 560 pub pc_card_legacy_mode_base_address_16_bit: u32, 561 } 562 impl PciDeviceStructure for PciDeviceStructurePciToCardbusBridge { 563 #[inline(always)] 564 fn header_type(&self) -> HeaderType { 565 HeaderType::PciCardbusBridge 566 } 567 #[inline(always)] 568 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 569 Some(&self) 570 } 571 #[inline(always)] 572 fn as_pci_to_carbus_bridge_device_mut( 573 &mut self, 574 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 575 Some(self) 576 } 577 #[inline(always)] 578 fn common_header(&self) -> &PciDeviceStructureHeader { 579 &self.common_header 580 } 581 #[inline(always)] 582 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 583 &mut self.common_header 584 } 585 #[inline(always)] 586 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 587 None 588 } 589 #[inline(always)] 590 fn irq_vector_mut(&mut self) -> Option<&mut Vec<u16>> { 591 None 592 } 593 } 594 595 /// 代表一个PCI segement greoup. 596 #[derive(Clone, Debug)] 597 pub struct PciRoot { 598 pub physical_address_base: PhysAddr, //物理地址，acpi获取 599 pub mmio_guard: Option<Arc<MMIOSpaceGuard>>, //映射后的虚拟地址，为方便访问数据这里转化成指针 600 pub segement_group_number: SegmentGroupNumber, //segement greoup的id 601 pub bus_begin: u8, //该分组中的最小bus 602 pub bus_end: u8, //该分组中的最大bus 603 } 604 ///线程间共享需要，该结构体只需要在初始化时写入数据，无需读写锁保证线程安全 605 unsafe impl Send for PciRoot {} 606 unsafe impl Sync for PciRoot {} 607 ///实现PciRoot的Display trait，自定义输出 608 impl Display for PciRoot { 609 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 610 write!( 611 f, 612 "PCI Root with segement:{}, bus begin at {}, bus end at {}, physical address at {:?},mapped at {:?}", 613 self.segement_group_number, self.bus_begin, self.bus_end, self.physical_address_base, self.mmio_guard 614 ) 615 } 616 } 617 618 impl PciRoot { 619 /// @brief 初始化结构体，获取ecam root所在物理地址后map到虚拟地址，再将该虚拟地址加入mmio_base变量 620 /// @return 成功返回结果，错误返回错误类型 621 pub fn new(segment_group_number: SegmentGroupNumber) -> Result<Self, PciError> { 622 let mut pci_root = PciArch::ecam_root(segment_group_number)?; 623 pci_root.map()?; 624 Ok(pci_root) 625 } 626 /// @brief 完成物理地址到虚拟地址的映射，并将虚拟地址加入mmio_base变量 627 /// @return 返回错误或Ok(0) 628 fn map(&mut self) -> Result<u8, PciError> { 629 //kdebug!("bus_begin={},bus_end={}", self.bus_begin,self.bus_end); 630 let bus_number = (self.bus_end - self.bus_begin) as u32 + 1; 631 let bus_number_double = (bus_number - 1) / 2 + 1; //一个bus占据1MB空间，计算全部bus占据空间相对于2MB空间的个数 632 633 let size = (bus_number_double as usize) * (PAGE_2M_SIZE as usize); 634 unsafe { 635 let space_guard = mmio_pool() 636 .create_mmio(size as usize) 637 .map_err(|_| PciError::CreateMmioError)?; 638 let space_guard = Arc::new(space_guard); 639 self.mmio_guard = Some(space_guard.clone()); 640 641 assert!(space_guard 642 .map_phys(self.physical_address_base, size) 643 .is_ok()); 644 } 645 return Ok(0); 646 } 647 /// @brief 获得要操作的寄存器相对于mmio_offset的偏移量 648 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 649 /// @param register_offset 寄存器在设备中的offset 650 /// @return u32 要操作的寄存器相对于mmio_offset的偏移量 651 fn cam_offset(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 652 assert!(bus_device_function.valid()); 653 let bdf = ((bus_device_function.bus - self.bus_begin) as u32) << 8 654 | (bus_device_function.device as u32) << 3 655 | bus_device_function.function as u32; 656 let address = bdf << 12 | register_offset as u32; 657 // Ensure that address is word-aligned. 658 assert!(address & 0x3 == 0); 659 address 660 } 661 /// @brief 通过bus_device_function和offset读取相应位置寄存器的值（32位） 662 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 663 /// @param register_offset 寄存器在设备中的offset 664 /// @return u32 寄存器读值结果 665 pub fn read_config(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 666 let address = self.cam_offset(bus_device_function, register_offset); 667 unsafe { 668 // Right shift to convert from byte offset to word offset. 669 ((self.mmio_guard.as_ref().unwrap().vaddr().data() as *mut u32) 670 .add((address >> 2) as usize)) 671 .read_volatile() 672 } 673 } 674 675 /// @brief 通过bus_device_function和offset写入相应位置寄存器值（32位） 676 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 677 /// @param register_offset 寄存器在设备中的offset 678 /// @param data 要写入的值 679 pub fn write_config( 680 &mut self, 681 bus_device_function: BusDeviceFunction, 682 register_offset: u16, 683 data: u32, 684 ) { 685 let address = self.cam_offset(bus_device_function, register_offset); 686 // Safe because both the `mmio_base` and the address offset are properly aligned, and the 687 // resulting pointer is within the MMIO range of the CAM. 688 unsafe { 689 // Right shift to convert from byte offset to word offset. 690 ((self.mmio_guard.as_ref().unwrap().vaddr().data() as *mut u32) 691 .add((address >> 2) as usize)) 692 .write_volatile(data) 693 } 694 } 695 /// @brief 返回迭代器，遍历pcie设备的external_capabilities 696 pub fn external_capabilities( 697 &self, 698 bus_device_function: BusDeviceFunction, 699 ) -> ExternalCapabilityIterator { 700 ExternalCapabilityIterator { 701 root: self, 702 bus_device_function, 703 next_capability_offset: Some(0x100), 704 } 705 } 706 } 707 /// Gets the capabilities 'pointer' for the device function, if any. 708 /// @brief 获取第一个capability 的offset 709 /// @param bus_device_function PCI设备的唯一标识 710 /// @return Option<u8> offset 711 pub fn capabilities_offset(bus_device_function: BusDeviceFunction) -> Option<u8> { 712 let result = PciArch::read_config(&bus_device_function, STATUS_COMMAND_OFFSET); 713 let status: Status = Status::from_bits_truncate((result >> 16) as u16); 714 if status.contains(Status::CAPABILITIES_LIST) { 715 let cap_pointer = PciArch::read_config(&bus_device_function, 0x34) as u8 & 0xFC; 716 Some(cap_pointer) 717 } else { 718 None 719 } 720 } 721 722 /// @brief 读取pci设备头部 723 /// @param bus_device_function PCI设备的唯一标识 724 /// @param add_to_list 是否添加到链表 725 /// @return 返回的header(trait 类型) 726 fn pci_read_header( 727 bus_device_function: BusDeviceFunction, 728 add_to_list: bool, 729 ) -> Result<Box<dyn PciDeviceStructure>, PciError> { 730 // 先读取公共header 731 let result = PciArch::read_config(&bus_device_function, 0x00); 732 let vendor_id = result as u16; 733 let device_id = (result >> 16) as u16; 734 735 let result = PciArch::read_config(&bus_device_function, 0x04); 736 let command = result as u16; 737 let status = (result >> 16) as u16; 738 739 let result = PciArch::read_config(&bus_device_function, 0x08); 740 let revision_id = result as u8; 741 let prog_if = (result >> 8) as u8; 742 let subclass = (result >> 16) as u8; 743 let class_code = (result >> 24) as u8; 744 745 let result = PciArch::read_config(&bus_device_function, 0x0c); 746 let cache_line_size = result as u8; 747 let latency_timer = (result >> 8) as u8; 748 let header_type = (result >> 16) as u8; 749 let bist = (result >> 24) as u8; 750 if vendor_id == 0xffff { 751 return Err(PciError::GetWrongHeader); 752 } 753 let header = PciDeviceStructureHeader { 754 bus_device_function, 755 vendor_id, 756 device_id, 757 command, 758 status, 759 revision_id, 760 prog_if, 761 subclass, 762 class_code, 763 cache_line_size, 764 latency_timer, 765 header_type, 766 bist, 767 }; 768 match HeaderType::from(header_type & 0x7f) { 769 HeaderType::Standard => { 770 let general_device = pci_read_general_device_header(header, &bus_device_function); 771 let box_general_device = Box::new(general_device); 772 let box_general_device_clone = box_general_device.clone(); 773 if add_to_list { 774 PCI_DEVICE_LINKEDLIST.add(box_general_device); 775 } 776 Ok(box_general_device_clone) 777 } 778 HeaderType::PciPciBridge => { 779 let pci_to_pci_bridge = pci_read_pci_to_pci_bridge_header(header, &bus_device_function); 780 let box_pci_to_pci_bridge = Box::new(pci_to_pci_bridge); 781 let box_pci_to_pci_bridge_clone = box_pci_to_pci_bridge.clone(); 782 if add_to_list { 783 PCI_DEVICE_LINKEDLIST.add(box_pci_to_pci_bridge); 784 } 785 Ok(box_pci_to_pci_bridge_clone) 786 } 787 HeaderType::PciCardbusBridge => { 788 let pci_cardbus_bridge = 789 pci_read_pci_to_cardbus_bridge_header(header, &bus_device_function); 790 let box_pci_cardbus_bridge = Box::new(pci_cardbus_bridge); 791 let box_pci_cardbus_bridge_clone = box_pci_cardbus_bridge.clone(); 792 if add_to_list { 793 PCI_DEVICE_LINKEDLIST.add(box_pci_cardbus_bridge); 794 } 795 Ok(box_pci_cardbus_bridge_clone) 796 } 797 HeaderType::Unrecognised(_) => Err(PciError::UnrecognisedHeaderType), 798 } 799 } 800 801 /// @brief 读取type为0x0的pci设备的header 802 /// 本函数只应被 pci_read_header()调用 803 /// @param common_header 共有头部 804 /// @param bus_device_function PCI设备的唯一标识 805 /// @return Pci_Device_Structure_General_Device 标准设备头部 806 fn pci_read_general_device_header( 807 common_header: PciDeviceStructureHeader, 808 bus_device_function: &BusDeviceFunction, 809 ) -> PciDeviceStructureGeneralDevice { 810 let standard_device_bar = PciStandardDeviceBar::default(); 811 let cardbus_cis_pointer = PciArch::read_config(bus_device_function, 0x28); 812 813 let result = PciArch::read_config(bus_device_function, 0x2c); 814 let subsystem_vendor_id = result as u16; 815 let subsystem_id = (result >> 16) as u16; 816 817 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x30); 818 819 let result = PciArch::read_config(bus_device_function, 0x34); 820 let capabilities_pointer = result as u8; 821 let reserved0 = (result >> 8) as u8; 822 let reserved1 = (result >> 16) as u16; 823 824 let reserved2 = PciArch::read_config(bus_device_function, 0x38); 825 826 let result = PciArch::read_config(bus_device_function, 0x3c); 827 let interrupt_line = result as u8; 828 let interrupt_pin = (result >> 8) as u8; 829 let min_grant = (result >> 16) as u8; 830 let max_latency = (result >> 24) as u8; 831 PciDeviceStructureGeneralDevice { 832 common_header, 833 irq_type: IrqType::Unused, 834 irq_vector: Vec::new(), 835 standard_device_bar, 836 cardbus_cis_pointer, 837 subsystem_vendor_id, 838 subsystem_id, 839 expansion_rom_base_address, 840 capabilities_pointer, 841 reserved0, 842 reserved1, 843 reserved2, 844 interrupt_line, 845 interrupt_pin, 846 min_grant, 847 max_latency, 848 } 849 } 850 851 /// @brief 读取type为0x1的pci设备的header 852 /// 本函数只应被 pci_read_header()调用 853 /// @param common_header 共有头部 854 /// @param bus_device_function PCI设备的唯一标识 855 /// @return Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci 桥设备头部 856 fn pci_read_pci_to_pci_bridge_header( 857 common_header: PciDeviceStructureHeader, 858 bus_device_function: &BusDeviceFunction, 859 ) -> PciDeviceStructurePciToPciBridge { 860 let bar0 = PciArch::read_config(bus_device_function, 0x10); 861 let bar1 = PciArch::read_config(bus_device_function, 0x14); 862 863 let result = PciArch::read_config(bus_device_function, 0x18); 864 865 let primary_bus_number = result as u8; 866 let secondary_bus_number = (result >> 8) as u8; 867 let subordinate_bus_number = (result >> 16) as u8; 868 let secondary_latency_timer = (result >> 24) as u8; 869 870 let result = PciArch::read_config(bus_device_function, 0x1c); 871 let io_base = result as u8; 872 let io_limit = (result >> 8) as u8; 873 let secondary_status = (result >> 16) as u16; 874 875 let result = PciArch::read_config(bus_device_function, 0x20); 876 let memory_base = result as u16; 877 let memory_limit = (result >> 16) as u16; 878 879 let result = PciArch::read_config(bus_device_function, 0x24); 880 let prefetchable_memory_base = result as u16; 881 let prefetchable_memory_limit = (result >> 16) as u16; 882 883 let prefetchable_base_upper_32_bits = PciArch::read_config(bus_device_function, 0x28); 884 let prefetchable_limit_upper_32_bits = PciArch::read_config(bus_device_function, 0x2c); 885 886 let result = PciArch::read_config(bus_device_function, 0x30); 887 let io_base_upper_16_bits = result as u16; 888 let io_limit_upper_16_bits = (result >> 16) as u16; 889 890 let result = PciArch::read_config(bus_device_function, 0x34); 891 let capability_pointer = result as u8; 892 let reserved0 = (result >> 8) as u8; 893 let reserved1 = (result >> 16) as u16; 894 895 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x38); 896 897 let result = PciArch::read_config(bus_device_function, 0x3c); 898 let interrupt_line = result as u8; 899 let interrupt_pin = (result >> 8) as u8; 900 let bridge_control = (result >> 16) as u16; 901 PciDeviceStructurePciToPciBridge { 902 common_header, 903 irq_type: IrqType::Unused, 904 irq_vector: Vec::new(), 905 bar0, 906 bar1, 907 primary_bus_number, 908 secondary_bus_number, 909 subordinate_bus_number, 910 secondary_latency_timer, 911 io_base, 912 io_limit, 913 secondary_status, 914 memory_base, 915 memory_limit, 916 prefetchable_memory_base, 917 prefetchable_memory_limit, 918 prefetchable_base_upper_32_bits, 919 prefetchable_limit_upper_32_bits, 920 io_base_upper_16_bits, 921 io_limit_upper_16_bits, 922 capability_pointer, 923 reserved0, 924 reserved1, 925 expansion_rom_base_address, 926 interrupt_line, 927 interrupt_pin, 928 bridge_control, 929 } 930 } 931 932 /// @brief 读取type为0x2的pci设备的header 933 /// 本函数只应被 pci_read_header()调用 934 /// @param common_header 共有头部 935 /// @param bus_device_function PCI设备的唯一标识 936 /// @return Pci_Device_Structure_Pci_to_Cardbus_Bridge pci-to-cardbus 桥设备头部 937 fn pci_read_pci_to_cardbus_bridge_header( 938 common_header: PciDeviceStructureHeader, 939 busdevicefunction: &BusDeviceFunction, 940 ) -> PciDeviceStructurePciToCardbusBridge { 941 let cardbus_socket_ex_ca_base_address = PciArch::read_config(busdevicefunction, 0x10); 942 943 let result = PciArch::read_config(busdevicefunction, 0x14); 944 let offset_of_capabilities_list = result as u8; 945 let reserved = (result >> 8) as u8; 946 let secondary_status = (result >> 16) as u16; 947 948 let result = PciArch::read_config(busdevicefunction, 0x18); 949 let pci_bus_number = result as u8; 950 let card_bus_bus_number = (result >> 8) as u8; 951 let subordinate_bus_number = (result >> 16) as u8; 952 let card_bus_latency_timer = (result >> 24) as u8; 953 954 let memory_base_address0 = PciArch::read_config(busdevicefunction, 0x1c); 955 let memory_limit0 = PciArch::read_config(busdevicefunction, 0x20); 956 let memory_base_address1 = PciArch::read_config(busdevicefunction, 0x24); 957 let memory_limit1 = PciArch::read_config(busdevicefunction, 0x28); 958 959 let io_base_address0 = PciArch::read_config(busdevicefunction, 0x2c); 960 let io_limit0 = PciArch::read_config(busdevicefunction, 0x30); 961 let io_base_address1 = PciArch::read_config(busdevicefunction, 0x34); 962 let io_limit1 = PciArch::read_config(busdevicefunction, 0x38); 963 let result = PciArch::read_config(busdevicefunction, 0x3c); 964 let interrupt_line = result as u8; 965 let interrupt_pin = (result >> 8) as u8; 966 let bridge_control = (result >> 16) as u16; 967 968 let result = PciArch::read_config(busdevicefunction, 0x40); 969 let subsystem_device_id = result as u16; 970 let subsystem_vendor_id = (result >> 16) as u16; 971 972 let pc_card_legacy_mode_base_address_16_bit = PciArch::read_config(busdevicefunction, 0x44); 973 PciDeviceStructurePciToCardbusBridge { 974 common_header, 975 cardbus_socket_ex_ca_base_address, 976 offset_of_capabilities_list, 977 reserved, 978 secondary_status, 979 pci_bus_number, 980 card_bus_bus_number, 981 subordinate_bus_number, 982 card_bus_latency_timer, 983 memory_base_address0, 984 memory_limit0, 985 memory_base_address1, 986 memory_limit1, 987 io_base_address0, 988 io_limit0, 989 io_base_address1, 990 io_limit1, 991 interrupt_line, 992 interrupt_pin, 993 bridge_control, 994 subsystem_device_id, 995 subsystem_vendor_id, 996 pc_card_legacy_mode_base_address_16_bit, 997 } 998 } 999 1000 /// @brief 检查所有bus上的设备并将其加入链表 1001 /// @return 成功返回ok(),失败返回失败原因 1002 fn pci_check_all_buses() -> Result<u8, PciError> { 1003 kinfo!("Checking all devices in PCI bus..."); 1004 let busdevicefunction = BusDeviceFunction { 1005 bus: 0, 1006 device: 0, 1007 function: 0, 1008 }; 1009 let header = pci_read_header(busdevicefunction, false)?; 1010 let common_header = header.common_header(); 1011 pci_check_bus(0)?; 1012 if common_header.header_type & 0x80 != 0 { 1013 for function in 1..8 { 1014 pci_check_bus(function)?; 1015 } 1016 } 1017 Ok(0) 1018 } 1019 /// @brief 检查特定设备并将其加入链表 1020 /// @return 成功返回ok(),失败返回失败原因 1021 fn pci_check_function(busdevicefunction: BusDeviceFunction) -> Result<u8, PciError> { 1022 //kdebug!("PCI check function {}", busdevicefunction.function); 1023 let header = match pci_read_header(busdevicefunction, true) { 1024 Ok(header) => header, 1025 Err(PciError::GetWrongHeader) => { 1026 return Ok(255); 1027 } 1028 Err(e) => { 1029 return Err(e); 1030 } 1031 }; 1032 let common_header = header.common_header(); 1033 if (common_header.class_code == 0x06) 1034 && (common_header.subclass == 0x04 || common_header.subclass == 0x09) 1035 { 1036 let pci_to_pci_bridge = header 1037 .as_pci_to_pci_bridge_device() 1038 .ok_or(PciError::PciDeviceStructureTransformError)?; 1039 let secondary_bus = pci_to_pci_bridge.secondary_bus_number; 1040 pci_check_bus(secondary_bus)?; 1041 } 1042 Ok(0) 1043 } 1044 1045 /// @brief 检查device上的设备并将其加入链表 1046 /// @return 成功返回ok(),失败返回失败原因 1047 fn pci_check_device(bus: u8, device: u8) -> Result<u8, PciError> { 1048 //kdebug!("PCI check device {}", device); 1049 let busdevicefunction = BusDeviceFunction { 1050 bus, 1051 device, 1052 function: 0, 1053 }; 1054 let header = match pci_read_header(busdevicefunction, false) { 1055 Ok(header) => header, 1056 Err(PciError::GetWrongHeader) => { 1057 //设备不存在，直接返回即可，不用终止遍历 1058 return Ok(255); 1059 } 1060 Err(e) => { 1061 return Err(e); 1062 } 1063 }; 1064 pci_check_function(busdevicefunction)?; 1065 let common_header = header.common_header(); 1066 if common_header.header_type & 0x80 != 0 { 1067 kdebug!( 1068 "Detected multi func device in bus{},device{}", 1069 busdevicefunction.bus, 1070 busdevicefunction.device 1071 ); 1072 // 这是一个多function的设备，因此查询剩余的function 1073 for function in 1..8 { 1074 let busdevicefunction = BusDeviceFunction { 1075 bus, 1076 device, 1077 function, 1078 }; 1079 pci_check_function(busdevicefunction)?; 1080 } 1081 } 1082 Ok(0) 1083 } 1084 /// @brief 检查该bus上的设备并将其加入链表 1085 /// @return 成功返回ok(),失败返回失败原因 1086 fn pci_check_bus(bus: u8) -> Result<u8, PciError> { 1087 //kdebug!("PCI check bus {}", bus); 1088 for device in 0..32 { 1089 pci_check_device(bus, device)?; 1090 } 1091 Ok(0) 1092 } 1093 /// @brief pci初始化函数(for c) 1094 #[no_mangle] 1095 pub extern "C" fn rs_pci_init() { 1096 pci_init(); 1097 if PCI_ROOT_0.is_some() { 1098 kdebug!("{}", PCI_ROOT_0.as_ref().unwrap()); 1099 //以下为ecam的读取寄存器值测试，经测试可正常读取 1100 // let bus_device_function = BusDeviceFunction { 1101 // bus: 0, 1102 // device: 2, 1103 // function: 0, 1104 // }; 1105 // kdebug!( 1106 // "Ecam read virtio-net device status={:#x}", 1107 // (PCI_ROOT_0.unwrap().read_config(bus_device_function, 4)>>16) as u16 1108 // ); 1109 } 1110 } 1111 /// @brief pci初始化函数 1112 pub fn pci_init() { 1113 kinfo!("Initializing PCI bus..."); 1114 if let Err(e) = pci_check_all_buses() { 1115 kerror!("pci init failed when checking bus because of error: {}", e); 1116 return; 1117 } 1118 kinfo!( 1119 "Total pci device and function num = {}", 1120 PCI_DEVICE_LINKEDLIST.num() 1121 ); 1122 let list = PCI_DEVICE_LINKEDLIST.read(); 1123 for box_pci_device in list.iter() { 1124 let common_header = box_pci_device.common_header(); 1125 match box_pci_device.header_type() { 1126 HeaderType::Standard if common_header.status & 0x10 != 0 => { 1127 kinfo!("Found pci standard device with class code ={} subclass={} status={:#x} cap_pointer={:#x} vendor={:#x}, device id={:#x},bdf={}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer,common_header.vendor_id, common_header.device_id,common_header.bus_device_function); 1128 } 1129 HeaderType::Standard => { 1130 kinfo!( 1131 "Found pci standard device with class code ={} subclass={} status={:#x} ", 1132 common_header.class_code, 1133 common_header.subclass, 1134 common_header.status 1135 ); 1136 } 1137 HeaderType::PciPciBridge if common_header.status & 0x10 != 0 => { 1138 kinfo!("Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} cap_pointer={:#x}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer); 1139 } 1140 HeaderType::PciPciBridge => { 1141 kinfo!( 1142 "Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} ", 1143 common_header.class_code, 1144 common_header.subclass, 1145 common_header.status 1146 ); 1147 } 1148 HeaderType::PciCardbusBridge => { 1149 kinfo!( 1150 "Found pcicardbus bridge device with class code ={} subclass={} status={:#x} ", 1151 common_header.class_code, 1152 common_header.subclass, 1153 common_header.status 1154 ); 1155 } 1156 HeaderType::Unrecognised(_) => {} 1157 } 1158 } 1159 kinfo!("PCI bus initialized."); 1160 } 1161 1162 /// An identifier for a PCI bus, device and function. 1163 /// PCI设备的唯一标识 1164 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1165 pub struct BusDeviceFunction { 1166 /// The PCI bus number, between 0 and 255. 1167 pub bus: u8, 1168 /// The device number on the bus, between 0 and 31. 1169 pub device: u8, 1170 /// The function number of the device, between 0 and 7. 1171 pub function: u8, 1172 } 1173 impl BusDeviceFunction { 1174 /// Returns whether the device and function numbers are valid, i.e. the device is between 0 and 1175 ///@brief 检测BusDeviceFunction实例是否有效 1176 ///@param self 1177 ///@return bool 是否有效 1178 #[allow(dead_code)] 1179 pub fn valid(&self) -> bool { 1180 self.device < 32 && self.function < 8 1181 } 1182 } 1183 ///实现BusDeviceFunction的Display trait，使其可以直接输出 1184 impl Display for BusDeviceFunction { 1185 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 1186 write!( 1187 f, 1188 "bus {} device {} function{}", 1189 self.bus, self.device, self.function 1190 ) 1191 } 1192 } 1193 /// The location allowed for a memory BAR. 1194 /// memory BAR的三种情况 1195 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1196 pub enum MemoryBarType { 1197 /// The BAR has a 32-bit address and can be mapped anywhere in 32-bit address space. 1198 Width32, 1199 /// The BAR must be mapped below 1MiB. 1200 Below1MiB, 1201 /// The BAR has a 64-bit address and can be mapped anywhere in 64-bit address space. 1202 Width64, 1203 } 1204 ///实现MemoryBarType与u8的类型转换 1205 impl From<MemoryBarType> for u8 { 1206 fn from(bar_type: MemoryBarType) -> Self { 1207 match bar_type { 1208 MemoryBarType::Width32 => 0, 1209 MemoryBarType::Below1MiB => 1, 1210 MemoryBarType::Width64 => 2, 1211 } 1212 } 1213 } 1214 ///实现MemoryBarType与u8的类型转换 1215 impl TryFrom<u8> for MemoryBarType { 1216 type Error = PciError; 1217 fn try_from(value: u8) -> Result<Self, Self::Error> { 1218 match value { 1219 0 => Ok(Self::Width32), 1220 1 => Ok(Self::Below1MiB), 1221 2 => Ok(Self::Width64), 1222 _ => Err(PciError::InvalidBarType), 1223 } 1224 } 1225 } 1226 1227 /// Information about a PCI Base Address Register. 1228 /// BAR的三种类型 Memory/IO/Unused 1229 #[derive(Clone, Debug)] 1230 pub enum BarInfo { 1231 /// The BAR is for a memory region. 1232 Memory { 1233 /// The size of the BAR address and where it can be located. 1234 address_type: MemoryBarType, 1235 /// If true, then reading from the region doesn't have side effects. The CPU may cache reads 1236 /// and merge repeated stores. 1237 prefetchable: bool, 1238 /// The memory address, always 16-byte aligned. 1239 address: u64, 1240 /// The size of the BAR in bytes. 1241 size: u32, 1242 /// The virtaddress for a memory bar(mapped). 1243 mmio_guard: Arc<MMIOSpaceGuard>, 1244 }, 1245 /// The BAR is for an I/O region. 1246 IO { 1247 /// The I/O address, always 4-byte aligned. 1248 address: u32, 1249 /// The size of the BAR in bytes. 1250 size: u32, 1251 }, 1252 Unused, 1253 } 1254 1255 impl BarInfo { 1256 /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO 1257 /// BAR. 1258 ///@brief 得到某个bar的memory_address与size(前提是他的类型为Memory Bar) 1259 ///@param self 1260 ///@return Option<(u64, u32) 是Memory Bar返回内存地址与大小，不是则返回None 1261 pub fn memory_address_size(&self) -> Option<(u64, u32)> { 1262 if let Self::Memory { address, size, .. } = self { 1263 Some((*address, *size)) 1264 } else { 1265 None 1266 } 1267 } 1268 ///@brief 得到某个bar的virtaddress(前提是他的类型为Memory Bar) 1269 ///@param self 1270 ///@return Option<(u64) 是Memory Bar返回映射的虚拟地址，不是则返回None 1271 pub fn virtual_address(&self) -> Option<VirtAddr> { 1272 if let Self::Memory { mmio_guard, .. } = self { 1273 Some(mmio_guard.vaddr()) 1274 } else { 1275 None 1276 } 1277 } 1278 } 1279 ///实现BarInfo的Display trait，自定义输出 1280 impl Display for BarInfo { 1281 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1282 match self { 1283 Self::Memory { 1284 address_type, 1285 prefetchable, 1286 address, 1287 size, 1288 mmio_guard, 1289 } => write!( 1290 f, 1291 "Memory space at {:#010x}, size {}, type {:?}, prefetchable {}, mmio_guard: {:?}", 1292 address, size, address_type, prefetchable, mmio_guard 1293 ), 1294 Self::IO { address, size } => { 1295 write!(f, "I/O space at {:#010x}, size {}", address, size) 1296 } 1297 Self::Unused => { 1298 write!(f, "Unused bar") 1299 } 1300 } 1301 } 1302 } 1303 // todo 增加对桥的bar的支持 1304 pub trait PciDeviceBar {} 1305 1306 ///一个普通PCI设备（非桥）有6个BAR寄存器，PciStandardDeviceBar存储其全部信息 1307 #[derive(Clone, Debug)] 1308 pub struct PciStandardDeviceBar { 1309 bar0: BarInfo, 1310 bar1: BarInfo, 1311 bar2: BarInfo, 1312 bar3: BarInfo, 1313 bar4: BarInfo, 1314 bar5: BarInfo, 1315 } 1316 1317 impl PciStandardDeviceBar { 1318 ///@brief 得到某个bar的barinfo 1319 ///@param self ，bar_index(0-5) 1320 ///@return Result<&BarInfo, PciError> bar_index在0-5则返回对应的bar_info结构体，超出范围则返回错误 1321 pub fn get_bar(&self, bar_index: u8) -> Result<&BarInfo, PciError> { 1322 match bar_index { 1323 0 => Ok(&self.bar0), 1324 1 => Ok(&self.bar1), 1325 2 => Ok(&self.bar2), 1326 3 => Ok(&self.bar3), 1327 4 => Ok(&self.bar4), 1328 5 => Ok(&self.bar5), 1329 _ => Err(PciError::InvalidBarType), 1330 } 1331 } 1332 } 1333 ///实现PciStandardDeviceBar的Display trait，使其可以直接输出 1334 impl Display for PciStandardDeviceBar { 1335 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1336 write!( 1337 f, 1338 "\r\nBar0:{}\r\nBar1:{}\r\nBar2:{}\r\nBar3:{}\r\nBar4:{}\r\nBar5:{}", 1339 self.bar0, self.bar1, self.bar2, self.bar3, self.bar4, self.bar5 1340 ) 1341 } 1342 } 1343 ///实现PciStandardDeviceBar的Default trait，使其可以简单初始化 1344 impl Default for PciStandardDeviceBar { 1345 fn default() -> Self { 1346 PciStandardDeviceBar { 1347 bar0: BarInfo::Unused, 1348 bar1: BarInfo::Unused, 1349 bar2: BarInfo::Unused, 1350 bar3: BarInfo::Unused, 1351 bar4: BarInfo::Unused, 1352 bar5: BarInfo::Unused, 1353 } 1354 } 1355 } 1356 1357 ///@brief 将某个pci设备的bar寄存器读取值后映射到虚拟地址 1358 ///@param self ，bus_device_function PCI设备的唯一标识符 1359 ///@return Result<PciStandardDeviceBar, PciError> 成功则返回对应的PciStandardDeviceBar结构体，失败则返回错误类型 1360 pub fn pci_bar_init( 1361 bus_device_function: BusDeviceFunction, 1362 ) -> Result<PciStandardDeviceBar, PciError> { 1363 let mut device_bar: PciStandardDeviceBar = PciStandardDeviceBar::default(); 1364 let mut bar_index_ignore: u8 = 255; 1365 for bar_index in 0..6 { 1366 if bar_index == bar_index_ignore { 1367 continue; 1368 } 1369 let bar_info; 1370 let bar_orig = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1371 PciArch::write_config( 1372 &bus_device_function, 1373 BAR0_OFFSET + 4 * bar_index, 1374 0xffffffff, 1375 ); 1376 let size_mask = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1377 // A wrapping add is necessary to correctly handle the case of unused BARs, which read back 1378 // as 0, and should be treated as size 0. 1379 let size = (!(size_mask & 0xfffffff0)).wrapping_add(1); 1380 //kdebug!("bar_orig:{:#x},size: {:#x}", bar_orig,size); 1381 // Restore the original value. 1382 PciArch::write_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index, bar_orig); 1383 if size == 0 { 1384 continue; 1385 } 1386 if bar_orig & 0x00000001 == 0x00000001 { 1387 // I/O space 1388 let address = bar_orig & 0xfffffffc; 1389 bar_info = BarInfo::IO { address, size }; 1390 } else { 1391 // Memory space 1392 let mut address = u64::from(bar_orig & 0xfffffff0); 1393 let prefetchable = bar_orig & 0x00000008 != 0; 1394 let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?; 1395 if address_type == MemoryBarType::Width64 { 1396 if bar_index >= 5 { 1397 return Err(PciError::InvalidBarType); 1398 } 1399 let address_top = 1400 PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * (bar_index + 1)); 1401 address |= u64::from(address_top) << 32; 1402 bar_index_ignore = bar_index + 1; //下个bar跳过，因为64位的memory bar覆盖了两个bar 1403 } 1404 let pci_address = PciAddr::new(address as usize); 1405 let paddr = PciArch::address_pci_to_physical(pci_address); //PCI总线域物理地址转换为存储器域物理地址 1406 1407 let space_guard: Arc<MMIOSpaceGuard>; 1408 unsafe { 1409 let size_want = size as usize; 1410 let tmp = mmio_pool() 1411 .create_mmio(size_want) 1412 .map_err(|_| PciError::CreateMmioError)?; 1413 space_guard = Arc::new(tmp); 1414 //kdebug!("Pci bar init: mmio space: {space_guard:?}, paddr={paddr:?}, size_want={size_want}"); 1415 assert!( 1416 space_guard.map_phys(paddr, size_want).is_ok(), 1417 "pci_bar_init: map_phys failed" 1418 ); 1419 } 1420 bar_info = BarInfo::Memory { 1421 address_type, 1422 prefetchable, 1423 address, 1424 size, 1425 mmio_guard: space_guard, 1426 }; 1427 } 1428 match bar_index { 1429 0 => { 1430 device_bar.bar0 = bar_info; 1431 } 1432 1 => { 1433 device_bar.bar1 = bar_info; 1434 } 1435 2 => { 1436 device_bar.bar2 = bar_info; 1437 } 1438 3 => { 1439 device_bar.bar3 = bar_info; 1440 } 1441 4 => { 1442 device_bar.bar4 = bar_info; 1443 } 1444 5 => { 1445 device_bar.bar5 = bar_info; 1446 } 1447 _ => {} 1448 } 1449 } 1450 //kdebug!("pci_device_bar:{}", device_bar); 1451 return Ok(device_bar); 1452 } 1453 1454 /// Information about a PCI device capability. 1455 /// PCI设备的capability的信息 1456 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1457 pub struct CapabilityInfo { 1458 /// The offset of the capability in the PCI configuration space of the device function. 1459 pub offset: u8, 1460 /// The ID of the capability. 1461 pub id: u8, 1462 /// The third and fourth bytes of the capability, to save reading them again. 1463 pub private_header: u16, 1464 } 1465 1466 /// Iterator over capabilities for a device. 1467 /// 创建迭代器以遍历PCI设备的capability 1468 #[derive(Debug)] 1469 pub struct CapabilityIterator { 1470 pub bus_device_function: BusDeviceFunction, 1471 pub next_capability_offset: Option<u8>, 1472 } 1473 1474 impl Iterator for CapabilityIterator { 1475 type Item = CapabilityInfo; 1476 fn next(&mut self) -> Option<Self::Item> { 1477 let offset = self.next_capability_offset?; 1478 1479 // Read the first 4 bytes of the capability. 1480 let capability_header = PciArch::read_config(&self.bus_device_function, offset); 1481 let id = capability_header as u8; 1482 let next_offset = (capability_header >> 8) as u8; 1483 let private_header = (capability_header >> 16) as u16; 1484 1485 self.next_capability_offset = if next_offset == 0 { 1486 None 1487 } else if next_offset < 64 || next_offset & 0x3 != 0 { 1488 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1489 None 1490 } else { 1491 Some(next_offset) 1492 }; 1493 1494 Some(CapabilityInfo { 1495 offset, 1496 id, 1497 private_header, 1498 }) 1499 } 1500 } 1501 1502 /// Information about a PCIe device capability. 1503 /// PCIe设备的external capability的信息 1504 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1505 pub struct ExternalCapabilityInfo { 1506 /// The offset of the capability in the PCI configuration space of the device function. 1507 pub offset: u16, 1508 /// The ID of the capability. 1509 pub id: u16, 1510 /// The third and fourth bytes of the capability, to save reading them again. 1511 pub capability_version: u8, 1512 } 1513 1514 /// Iterator over capabilities for a device. 1515 /// 创建迭代器以遍历PCIe设备的external capability 1516 #[derive(Debug)] 1517 pub struct ExternalCapabilityIterator<'a> { 1518 pub root: &'a PciRoot, 1519 pub bus_device_function: BusDeviceFunction, 1520 pub next_capability_offset: Option<u16>, 1521 } 1522 impl<'a> Iterator for ExternalCapabilityIterator<'a> { 1523 type Item = ExternalCapabilityInfo; 1524 fn next(&mut self) -> Option<Self::Item> { 1525 let offset = self.next_capability_offset?; 1526 1527 // Read the first 4 bytes of the capability. 1528 let capability_header = self.root.read_config(self.bus_device_function, offset); 1529 let id = capability_header as u16; 1530 let next_offset = (capability_header >> 20) as u16; 1531 let capability_version = ((capability_header >> 16) & 0xf) as u8; 1532 1533 self.next_capability_offset = if next_offset == 0 { 1534 None 1535 } else if next_offset < 0x100 || next_offset & 0x3 != 0 { 1536 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1537 None 1538 } else { 1539 Some(next_offset) 1540 }; 1541 1542 Some(ExternalCapabilityInfo { 1543 offset, 1544 id, 1545 capability_version, 1546 }) 1547 } 1548 } 1549