1 #![allow(dead_code)] 2 // 目前仅支持单主桥单Segment 3 4 use crate::arch::{PciArch, TraitPciArch}; 5 use crate::include::bindings::bindings::{ 6 initial_mm, mm_map, mm_struct, PAGE_2M_SIZE, VM_DONTCOPY, VM_IO, 7 }; 8 use crate::libs::rwlock::{RwLock, RwLockReadGuard, RwLockWriteGuard}; 9 use crate::mm::mmio_buddy::MMIO_POOL; 10 use crate::{kdebug, kerror, kinfo, kwarn}; 11 use alloc::vec::Vec; 12 use alloc::{boxed::Box, collections::LinkedList}; 13 use bitflags::bitflags; 14 15 use core::{ 16 convert::TryFrom, 17 fmt::{self, Debug, Display, Formatter}, 18 }; 19 20 // PCI_DEVICE_LINKEDLIST 添加了读写锁的全局链表，里面存储了检索到的PCI设备结构体 21 // PCI_ROOT_0 Segment为0的全局PciRoot 22 lazy_static! { 23 pub static ref PCI_DEVICE_LINKEDLIST: PciDeviceLinkedList = PciDeviceLinkedList::new(); 24 pub static ref PCI_ROOT_0: Option<PciRoot> = { 25 match PciRoot::new(0) { 26 Ok(root) => Some(root), 27 Err(err) => { 28 kerror!("Pci_root init failed because of error: {}", err); 29 None 30 } 31 } 32 }; 33 } 34 /// PCI域地址 35 #[derive(Clone, Copy, Eq, Ord, PartialEq, PartialOrd)] 36 #[repr(transparent)] 37 pub struct PciAddr(usize); 38 39 impl PciAddr { 40 #[inline(always)] 41 pub const fn new(address: usize) -> Self { 42 Self(address) 43 } 44 45 /// @brief 获取PCI域地址的值 46 #[inline(always)] 47 pub fn data(&self) -> usize { 48 self.0 49 } 50 51 /// @brief 将PCI域地址加上一个偏移量 52 #[inline(always)] 53 pub fn add(self, offset: usize) -> Self { 54 Self(self.0 + offset) 55 } 56 57 /// @brief 判断PCI域地址是否按照指定要求对齐 58 #[inline(always)] 59 pub fn check_aligned(&self, align: usize) -> bool { 60 return self.0 & (align - 1) == 0; 61 } 62 } 63 impl Debug for PciAddr { 64 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { 65 write!(f, "PciAddr({:#x})", self.0) 66 } 67 } 68 69 /// 添加了读写锁的链表，存储PCI设备结构体 70 pub struct PciDeviceLinkedList { 71 list: RwLock<LinkedList<Box<dyn PciDeviceStructure>>>, 72 } 73 74 impl PciDeviceLinkedList { 75 /// @brief 初始化结构体 76 fn new() -> Self { 77 PciDeviceLinkedList { 78 list: RwLock::new(LinkedList::new()), 79 } 80 } 81 /// @brief 获取可读的linkedlist(读锁守卫) 82 /// @return RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> 读锁守卫 83 pub fn read(&self) -> RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 84 self.list.read() 85 } 86 /// @brief 获取可写的linkedlist(写锁守卫) 87 /// @return RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> 写锁守卫 88 pub fn write(&self) -> RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 89 self.list.write() 90 } 91 /// @brief 获取链表中PCI结构体数目 92 /// @return usize 链表中PCI结构体数目 93 pub fn num(&self) -> usize { 94 let list = self.list.read(); 95 list.len() 96 } 97 /// @brief 添加Pci设备结构体到链表中 98 pub fn add(&self, device: Box<dyn PciDeviceStructure>) { 99 let mut list = self.list.write(); 100 list.push_back(device); 101 } 102 } 103 104 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其可变引用 105 /// @param list 链表的写锁守卫 106 /// @param class_code 寄存器值 107 /// @param subclass 寄存器值，与class_code一起确定设备类型 108 /// @return Vec<&'a mut Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的可变引用的容器 109 pub fn get_pci_device_structure_mut<'a>( 110 list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 111 class_code: u8, 112 subclass: u8, 113 ) -> Vec<&'a mut Box<(dyn PciDeviceStructure)>> { 114 let mut result = Vec::new(); 115 for box_pci_device_structure in list.iter_mut() { 116 let common_header = (*box_pci_device_structure).common_header(); 117 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 118 result.push(box_pci_device_structure); 119 } 120 } 121 result 122 } 123 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其不可变引用 124 /// @param list 链表的读锁守卫 125 /// @param class_code 寄存器值 126 /// @param subclass 寄存器值，与class_code一起确定设备类型 127 /// @return Vec<&'a Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的不可变引用的容器 128 pub fn get_pci_device_structure<'a>( 129 list: &'a mut RwLockReadGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 130 class_code: u8, 131 subclass: u8, 132 ) -> Vec<&'a Box<(dyn PciDeviceStructure)>> { 133 let mut result = Vec::new(); 134 for box_pci_device_structure in list.iter() { 135 let common_header = (*box_pci_device_structure).common_header(); 136 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 137 result.push(box_pci_device_structure); 138 } 139 } 140 result 141 } 142 143 //Bar0寄存器的offset 144 const BAR0_OFFSET: u8 = 0x10; 145 //Status、Command寄存器的offset 146 const STATUS_COMMAND_OFFSET: u8 = 0x04; 147 /// ID for vendor-specific PCI capabilities.(Virtio Capabilities) 148 pub const PCI_CAP_ID_VNDR: u8 = 0x09; 149 pub const PORT_PCI_CONFIG_ADDRESS: u16 = 0xcf8; 150 pub const PORT_PCI_CONFIG_DATA: u16 = 0xcfc; 151 // pci设备分组的id 152 pub type SegmentGroupNumber = u16; //理论上最多支持65535个Segment_Group 153 154 bitflags! { 155 /// The status register in PCI configuration space. 156 pub struct Status: u16 { 157 // Bits 0-2 are reserved. 158 /// The state of the device's INTx# signal. 159 const INTERRUPT_STATUS = 1 << 3; 160 /// The device has a linked list of capabilities. 161 const CAPABILITIES_LIST = 1 << 4; 162 /// The device is capabile of running at 66 MHz rather than 33 MHz. 163 const MHZ_66_CAPABLE = 1 << 5; 164 // Bit 6 is reserved. 165 /// The device can accept fast back-to-back transactions not from the same agent. 166 const FAST_BACK_TO_BACK_CAPABLE = 1 << 7; 167 /// The bus agent observed a parity error (if parity error handling is enabled). 168 const MASTER_DATA_PARITY_ERROR = 1 << 8; 169 // Bits 9-10 are DEVSEL timing. 170 /// A target device terminated a transaction with target-abort. 171 const SIGNALED_TARGET_ABORT = 1 << 11; 172 /// A master device transaction was terminated with target-abort. 173 const RECEIVED_TARGET_ABORT = 1 << 12; 174 /// A master device transaction was terminated with master-abort. 175 const RECEIVED_MASTER_ABORT = 1 << 13; 176 /// A device asserts SERR#. 177 const SIGNALED_SYSTEM_ERROR = 1 << 14; 178 /// The device detects a parity error, even if parity error handling is disabled. 179 const DETECTED_PARITY_ERROR = 1 << 15; 180 } 181 } 182 183 bitflags! { 184 /// The command register in PCI configuration space. 185 pub struct Command: u16 { 186 /// The device can respond to I/O Space accesses. 187 const IO_SPACE = 1 << 0; 188 /// The device can respond to Memory Space accesses. 189 const MEMORY_SPACE = 1 << 1; 190 /// The device can behave as a bus master. 191 const BUS_MASTER = 1 << 2; 192 /// The device can monitor Special Cycle operations. 193 const SPECIAL_CYCLES = 1 << 3; 194 /// The device can generate the Memory Write and Invalidate command. 195 const MEMORY_WRITE_AND_INVALIDATE_ENABLE = 1 << 4; 196 /// The device will snoop palette register data. 197 const VGA_PALETTE_SNOOP = 1 << 5; 198 /// The device should take its normal action when a parity error is detected. 199 const PARITY_ERROR_RESPONSE = 1 << 6; 200 // Bit 7 is reserved. 201 /// The SERR# driver is enabled. 202 const SERR_ENABLE = 1 << 8; 203 /// The device is allowed to generate fast back-to-back transactions. 204 const FAST_BACK_TO_BACK_ENABLE = 1 << 9; 205 /// Assertion of the device's INTx# signal is disabled. 206 const INTERRUPT_DISABLE = 1 << 10; 207 } 208 } 209 210 /// The type of a PCI device function header. 211 /// 标头类型/设备类型 212 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 213 pub enum HeaderType { 214 /// A normal PCI device. 215 Standard, 216 /// A PCI to PCI bridge. 217 PciPciBridge, 218 /// A PCI to CardBus bridge. 219 PciCardbusBridge, 220 /// Unrecognised header type. 221 Unrecognised(u8), 222 } 223 /// u8到HeaderType的转换 224 impl From<u8> for HeaderType { 225 fn from(value: u8) -> Self { 226 match value { 227 0x00 => Self::Standard, 228 0x01 => Self::PciPciBridge, 229 0x02 => Self::PciCardbusBridge, 230 _ => Self::Unrecognised(value), 231 } 232 } 233 } 234 /// Pci可能触发的各种错误 235 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 236 pub enum PciError { 237 /// The device reported an invalid BAR type. 238 InvalidBarType, 239 CreateMmioError, 240 InvalidBusDeviceFunction, 241 SegmentNotFound, 242 GetWrongHeader, 243 UnrecognisedHeaderType, 244 PciDeviceStructureTransformError, 245 } 246 ///实现PciError的Display trait，使其可以直接输出 247 impl Display for PciError { 248 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 249 match self { 250 Self::InvalidBarType => write!(f, "Invalid PCI BAR type."), 251 Self::CreateMmioError => write!(f, "Error occurred while creating mmio."), 252 Self::InvalidBusDeviceFunction => write!(f, "Found invalid BusDeviceFunction."), 253 Self::SegmentNotFound => write!(f, "Target segment not found"), 254 Self::GetWrongHeader => write!(f, "GetWrongHeader with vendor id 0xffff"), 255 Self::UnrecognisedHeaderType => write!(f, "Found device with unrecognised header type"), 256 Self::PciDeviceStructureTransformError => { 257 write!(f, "Found None When transform Pci device structure") 258 } 259 } 260 } 261 } 262 263 /// trait类型Pci_Device_Structure表示pci设备，动态绑定三种具体设备类型：Pci_Device_Structure_General_Device、Pci_Device_Structure_Pci_to_Pci_Bridge、Pci_Device_Structure_Pci_to_Cardbus_Bridge 264 pub trait PciDeviceStructure: Send + Sync { 265 /// @brief 获取设备类型 266 /// @return HeaderType 设备类型 267 fn header_type(&self) -> HeaderType; 268 /// @brief 当其为standard设备时返回&Pci_Device_Structure_General_Device，其余情况返回None 269 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 270 None 271 } 272 /// @brief 当其为pci to pci bridge设备时返回&Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 273 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 274 None 275 } 276 /// @brief 当其为pci to cardbus bridge设备时返回&Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 277 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 278 None 279 } 280 /// @brief 获取Pci设备共有的common_header 281 /// @return 返回其不可变引用 282 fn common_header(&self) -> &PciDeviceStructureHeader; 283 /// @brief 当其为standard设备时返回&mut Pci_Device_Structure_General_Device，其余情况返回None 284 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 285 None 286 } 287 /// @brief 当其为pci to pci bridge设备时返回&mut Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 288 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 289 None 290 } 291 /// @brief 当其为pci to cardbus bridge设备时返回&mut Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 292 fn as_pci_to_carbus_bridge_device_mut( 293 &mut self, 294 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 295 None 296 } 297 /// @brief 返回迭代器，遍历capabilities 298 fn capabilities(&self) -> Option<CapabilityIterator> { 299 None 300 } 301 /// @brief 获取Status、Command寄存器的值 302 fn status_command(&self) -> (Status, Command) { 303 let common_header = self.common_header(); 304 let status = Status::from_bits_truncate(common_header.status); 305 let command = Command::from_bits_truncate(common_header.command); 306 (status, command) 307 } 308 /// @brief 设置Command寄存器的值 309 fn set_command(&mut self, command: Command) { 310 let common_header = self.common_header_mut(); 311 let command = command.bits(); 312 common_header.command = command; 313 PciArch::write_config( 314 &common_header.bus_device_function, 315 STATUS_COMMAND_OFFSET, 316 command as u32, 317 ); 318 } 319 /// @brief 获取Pci设备共有的common_header 320 /// @return 返回其可变引用 321 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader; 322 /// @brief 读取standard设备的bar寄存器，映射后将结果加入结构体的standard_device_bar变量 323 /// @return 只有standard设备才返回成功或者错误，其余返回None 324 fn bar_init(&mut self) -> Option<Result<u8, PciError>> { 325 None 326 } 327 /// todo 328 fn msix_init(&mut self) -> Option<Result<u8, PciError>> { 329 None 330 } 331 fn enable_master(&mut self) { 332 self.set_command(Command::IO_SPACE | Command::MEMORY_SPACE | Command::BUS_MASTER); 333 } 334 } 335 336 /// Pci_Device_Structure_Header PCI设备结构体共有的头部 337 #[derive(Clone, Debug)] 338 pub struct PciDeviceStructureHeader { 339 // 包含msix table地址的bar的mmio基地址 todo:以下四个作为一个结构体统一管理 340 pub msix_mmio_vaddr: u64, 341 pub msix_mmio_size: u64, // msix映射长度 342 pub msix_offset: u32, // msix表的offset 343 pub msix_table_size: u16, // msix表的表项数量 344 // ==== busdevicefunction变量表示该结构体所处的位置 345 pub bus_device_function: BusDeviceFunction, 346 pub vendor_id: u16, // 供应商ID 0xffff是一个无效值，在读取访问不存在的设备的配置空间寄存器时返回 347 pub device_id: u16, // 设备ID，标志特定设备 348 pub command: u16, // 提供对设备生成和响应pci周期的能力的控制 向该寄存器写入0时，设备与pci总线断开除配置空间访问以外的所有连接 349 pub status: u16, // 用于记录pci总线相关时间的状态信息寄存器 350 pub revision_id: u8, // 修订ID，指定特定设备的修订标志符 351 pub prog_if: u8, // 编程接口字节，一个只读寄存器，指定设备具有的寄存器级别的编程接口（如果有的话） 352 pub subclass: u8, // 子类。指定设备执行的特定功能的只读寄存器 353 pub class_code: u8, // 类代码，一个只读寄存器，指定设备执行的功能类型 354 pub cache_line_size: u8, // 缓存线大小：以 32 位为单位指定系统缓存线大小。设备可以限制它可以支持的缓存线大小的数量，如果不支持的值写入该字段，设备将表现得好像写入了 0 值 355 pub latency_timer: u8, // 延迟计时器：以 PCI 总线时钟为单位指定延迟计时器。 356 pub header_type: u8, // 标头类型 a value of 0x0 specifies a general device, a value of 0x1 specifies a PCI-to-PCI bridge, and a value of 0x2 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device. 357 pub bist: u8, // Represents that status and allows control of a devices BIST (built-in self test). 358 // Here is the layout of the BIST register: 359 // | bit7 | bit6 | Bits 5-4 | Bits 3-0 | 360 // | BIST Capable | Start BIST | Reserved | Completion Code | 361 // for more details, please visit https://wiki.osdev.org/PCI 362 } 363 364 /// Pci_Device_Structure_General_Device PCI标准设备结构体 365 #[derive(Clone, Debug)] 366 pub struct PciDeviceStructureGeneralDevice { 367 pub common_header: PciDeviceStructureHeader, 368 pub standard_device_bar: PciStandardDeviceBar, 369 pub cardbus_cis_pointer: u32, // 指向卡信息结构，供在 CardBus 和 PCI 之间共享芯片的设备使用。 370 pub subsystem_vendor_id: u16, 371 pub subsystem_id: u16, 372 pub expansion_rom_base_address: u32, 373 pub capabilities_pointer: u8, 374 pub reserved0: u8, 375 pub reserved1: u16, 376 pub reserved2: u32, 377 pub interrupt_line: u8, // 指定设备的中断引脚连接到系统中断控制器的哪个输入，并由任何使用中断引脚的设备实现。对于 x86 架构，此寄存器对应于 PIC IRQ 编号 0-15（而不是 I/O APIC IRQ 编号），并且值0xFF定义为无连接。 378 pub interrupt_pin: u8, // 指定设备使用的中断引脚。其中值为0x1INTA#、0x2INTB#、0x3INTC#、0x4INTD#，0x0表示设备不使用中断引脚。 379 pub min_grant: u8, // 一个只读寄存器，用于指定设备所需的突发周期长度（以 1/4 微秒为单位）（假设时钟速率为 33 MHz） 380 pub max_latency: u8, // 一个只读寄存器，指定设备需要多长时间访问一次 PCI 总线（以 1/4 微秒为单位）。 381 } 382 impl PciDeviceStructure for PciDeviceStructureGeneralDevice { 383 fn header_type(&self) -> HeaderType { 384 HeaderType::Standard 385 } 386 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 387 Some(self) 388 } 389 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 390 Some(self) 391 } 392 fn common_header(&self) -> &PciDeviceStructureHeader { 393 &self.common_header 394 } 395 396 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 397 &mut self.common_header 398 } 399 fn capabilities(&self) -> Option<CapabilityIterator> { 400 Some(CapabilityIterator { 401 bus_device_function: self.common_header.bus_device_function, 402 next_capability_offset: Some(self.capabilities_pointer), 403 }) 404 } 405 fn bar_init(&mut self) -> Option<Result<u8, PciError>> { 406 let common_header = &self.common_header; 407 match pci_bar_init(common_header.bus_device_function) { 408 Ok(bar) => { 409 self.standard_device_bar = bar; 410 Some(Ok(0)) 411 } 412 Err(e) => Some(Err(e)), 413 } 414 } 415 } 416 /// Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci桥设备结构体 417 #[derive(Clone, Debug)] 418 pub struct PciDeviceStructurePciToPciBridge { 419 pub common_header: PciDeviceStructureHeader, 420 pub bar0: u32, 421 pub bar1: u32, 422 pub primary_bus_number: u8, 423 pub secondary_bus_number: u8, 424 pub subordinate_bus_number: u8, 425 pub secondary_latency_timer: u8, 426 pub io_base: u8, 427 pub io_limit: u8, 428 pub secondary_status: u16, 429 pub memory_base: u16, 430 pub memory_limit: u16, 431 pub prefetchable_memory_base: u16, 432 pub prefetchable_memory_limit: u16, 433 pub prefetchable_base_upper_32_bits: u32, 434 pub prefetchable_limit_upper_32_bits: u32, 435 pub io_base_upper_16_bits: u16, 436 pub io_limit_upper_16_bits: u16, 437 pub capability_pointer: u8, 438 pub reserved0: u8, 439 pub reserved1: u16, 440 pub expansion_rom_base_address: u32, 441 pub interrupt_line: u8, 442 pub interrupt_pin: u8, 443 pub bridge_control: u16, 444 } 445 impl PciDeviceStructure for PciDeviceStructurePciToPciBridge { 446 fn header_type(&self) -> HeaderType { 447 HeaderType::PciPciBridge 448 } 449 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 450 Some(self) 451 } 452 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 453 Some(self) 454 } 455 fn common_header(&self) -> &PciDeviceStructureHeader { 456 &self.common_header 457 } 458 459 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 460 &mut self.common_header 461 } 462 } 463 /// Pci_Device_Structure_Pci_to_Cardbus_Bridge Pci_to_Cardbus桥设备结构体 464 #[derive(Clone, Debug)] 465 pub struct PciDeviceStructurePciToCardbusBridge { 466 pub common_header: PciDeviceStructureHeader, 467 pub cardbus_socket_ex_ca_base_address: u32, 468 pub offset_of_capabilities_list: u8, 469 pub reserved: u8, 470 pub secondary_status: u16, 471 pub pci_bus_number: u8, 472 pub card_bus_bus_number: u8, 473 pub subordinate_bus_number: u8, 474 pub card_bus_latency_timer: u8, 475 pub memory_base_address0: u32, 476 pub memory_limit0: u32, 477 pub memory_base_address1: u32, 478 pub memory_limit1: u32, 479 pub io_base_address0: u32, 480 pub io_limit0: u32, 481 pub io_base_address1: u32, 482 pub io_limit1: u32, 483 pub interrupt_line: u8, 484 pub interrupt_pin: u8, 485 pub bridge_control: u16, 486 pub subsystem_device_id: u16, 487 pub subsystem_vendor_id: u16, 488 pub pc_card_legacy_mode_base_address_16_bit: u32, 489 } 490 impl PciDeviceStructure for PciDeviceStructurePciToCardbusBridge { 491 fn header_type(&self) -> HeaderType { 492 HeaderType::PciCardbusBridge 493 } 494 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 495 Some(&self) 496 } 497 fn as_pci_to_carbus_bridge_device_mut( 498 &mut self, 499 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 500 Some(self) 501 } 502 fn common_header(&self) -> &PciDeviceStructureHeader { 503 &self.common_header 504 } 505 506 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 507 &mut self.common_header 508 } 509 } 510 511 /// 代表一个PCI segement greoup. 512 #[derive(Copy, Clone, Debug, PartialEq)] 513 pub struct PciRoot { 514 pub physical_address_base: u64, //物理地址，acpi获取 515 pub mmio_base: Option<*mut u32>, //映射后的虚拟地址，为方便访问数据这里转化成指针 516 pub segement_group_number: SegmentGroupNumber, //segement greoup的id 517 pub bus_begin: u8, //该分组中的最小bus 518 pub bus_end: u8, //该分组中的最大bus 519 } 520 ///线程间共享需要，该结构体只需要在初始化时写入数据，无需读写锁保证线程安全 521 unsafe impl Send for PciRoot {} 522 unsafe impl Sync for PciRoot {} 523 ///实现PciRoot的Display trait，自定义输出 524 impl Display for PciRoot { 525 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 526 write!( 527 f, 528 "PCI Root with segement:{}, bus begin at {}, bus end at {}, physical address at {:#x},mapped at {:#x}", 529 self.segement_group_number, self.bus_begin, self.bus_end, self.physical_address_base, self.mmio_base.unwrap() as usize 530 ) 531 } 532 } 533 534 impl PciRoot { 535 /// @brief 初始化结构体，获取ecam root所在物理地址后map到虚拟地址，再将该虚拟地址加入mmio_base变量 536 /// @return 成功返回结果，错误返回错误类型 537 pub fn new(segment_group_number: SegmentGroupNumber) -> Result<Self, PciError> { 538 let mut pci_root = PciArch::ecam_root(segment_group_number)?; 539 pci_root.map()?; 540 Ok(pci_root) 541 } 542 /// @brief 完成物理地址到虚拟地址的映射，并将虚拟地址加入mmio_base变量 543 /// @return 返回错误或Ok(0) 544 fn map(&mut self) -> Result<u8, PciError> { 545 //kdebug!("bus_begin={},bus_end={}", self.bus_begin,self.bus_end); 546 let bus_number = (self.bus_end - self.bus_begin) as u32 + 1; 547 let bus_number_double = (bus_number - 1) / 2 + 1; //一个bus占据1MB空间，计算全部bus占据空间相对于2MB空间的个数 548 let mut virtaddress: u64 = 0; 549 let vaddr_ptr = &mut virtaddress as *mut u64; 550 let mut virtsize: u64 = 0; 551 let virtsize_ptr = &mut virtsize as *mut u64; 552 let size = bus_number_double * PAGE_2M_SIZE; 553 unsafe { 554 let initial_mm_ptr = &mut initial_mm as *mut mm_struct; 555 if let Err(_) = 556 MMIO_POOL.create_mmio(size, (VM_IO | VM_DONTCOPY) as u64, vaddr_ptr, virtsize_ptr) 557 { 558 kerror!("Create mmio failed when initing ecam"); 559 return Err(PciError::CreateMmioError); 560 }; 561 //kdebug!("virtaddress={:#x},virtsize={:#x}",virtaddress,virtsize); 562 mm_map( 563 initial_mm_ptr, 564 virtaddress, 565 size as u64, 566 self.physical_address_base, 567 ); 568 } 569 self.mmio_base = Some(virtaddress as *mut u32); 570 Ok(0) 571 } 572 /// @brief 获得要操作的寄存器相对于mmio_offset的偏移量 573 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 574 /// @param register_offset 寄存器在设备中的offset 575 /// @return u32 要操作的寄存器相对于mmio_offset的偏移量 576 fn cam_offset(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 577 assert!(bus_device_function.valid()); 578 let bdf = ((bus_device_function.bus - self.bus_begin) as u32) << 8 579 | (bus_device_function.device as u32) << 3 580 | bus_device_function.function as u32; 581 let address = bdf << 12 | register_offset as u32; 582 // Ensure that address is word-aligned. 583 assert!(address & 0x3 == 0); 584 address 585 } 586 /// @brief 通过bus_device_function和offset读取相应位置寄存器的值（32位） 587 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 588 /// @param register_offset 寄存器在设备中的offset 589 /// @return u32 寄存器读值结果 590 pub fn read_config(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 591 let address = self.cam_offset(bus_device_function, register_offset); 592 unsafe { 593 // Right shift to convert from byte offset to word offset. 594 (self.mmio_base.unwrap().add((address >> 2) as usize)).read_volatile() 595 } 596 } 597 598 /// @brief 通过bus_device_function和offset写入相应位置寄存器值（32位） 599 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 600 /// @param register_offset 寄存器在设备中的offset 601 /// @param data 要写入的值 602 pub fn write_config( 603 &mut self, 604 bus_device_function: BusDeviceFunction, 605 register_offset: u16, 606 data: u32, 607 ) { 608 let address = self.cam_offset(bus_device_function, register_offset); 609 // Safe because both the `mmio_base` and the address offset are properly aligned, and the 610 // resulting pointer is within the MMIO range of the CAM. 611 unsafe { 612 // Right shift to convert from byte offset to word offset. 613 (self.mmio_base.unwrap().add((address >> 2) as usize)).write_volatile(data) 614 } 615 } 616 /// @brief 返回迭代器，遍历pcie设备的external_capabilities 617 pub fn external_capabilities( 618 &self, 619 bus_device_function: BusDeviceFunction, 620 ) -> ExternalCapabilityIterator { 621 ExternalCapabilityIterator { 622 root: self, 623 bus_device_function, 624 next_capability_offset: Some(0x100), 625 } 626 } 627 } 628 /// Gets the capabilities 'pointer' for the device function, if any. 629 /// @brief 获取第一个capability 的offset 630 /// @param bus_device_function PCI设备的唯一标识 631 /// @return Option<u8> offset 632 pub fn capabilities_offset(bus_device_function: BusDeviceFunction) -> Option<u8> { 633 let result = PciArch::read_config(&bus_device_function, STATUS_COMMAND_OFFSET); 634 let status: Status = Status::from_bits_truncate((result >> 16) as u16); 635 if status.contains(Status::CAPABILITIES_LIST) { 636 let cap_pointer = PciArch::read_config(&bus_device_function, 0x34) as u8 & 0xFC; 637 Some(cap_pointer) 638 } else { 639 None 640 } 641 } 642 643 /// @brief 读取pci设备头部 644 /// @param bus_device_function PCI设备的唯一标识 645 /// @param add_to_list 是否添加到链表 646 /// @return 返回的header(trait 类型) 647 fn pci_read_header( 648 bus_device_function: BusDeviceFunction, 649 add_to_list: bool, 650 ) -> Result<Box<dyn PciDeviceStructure>, PciError> { 651 // 先读取公共header 652 let result = PciArch::read_config(&bus_device_function, 0x00); 653 let vendor_id = result as u16; 654 let device_id = (result >> 16) as u16; 655 656 let result = PciArch::read_config(&bus_device_function, 0x04); 657 let command = result as u16; 658 let status = (result >> 16) as u16; 659 660 let result = PciArch::read_config(&bus_device_function, 0x08); 661 let revision_id = result as u8; 662 let prog_if = (result >> 8) as u8; 663 let subclass = (result >> 16) as u8; 664 let class_code = (result >> 24) as u8; 665 666 let result = PciArch::read_config(&bus_device_function, 0x0c); 667 let cache_line_size = result as u8; 668 let latency_timer = (result >> 8) as u8; 669 let header_type = (result >> 16) as u8; 670 let bist = (result >> 24) as u8; 671 if vendor_id == 0xffff { 672 return Err(PciError::GetWrongHeader); 673 } 674 let header = PciDeviceStructureHeader { 675 msix_mmio_vaddr: 0, 676 msix_mmio_size: 0, 677 msix_offset: 0, 678 msix_table_size: 0, 679 bus_device_function, 680 vendor_id, 681 device_id, 682 command, 683 status, 684 revision_id, 685 prog_if, 686 subclass, 687 class_code, 688 cache_line_size, 689 latency_timer, 690 header_type, 691 bist, 692 }; 693 match HeaderType::from(header_type & 0x7f) { 694 HeaderType::Standard => { 695 let general_device = pci_read_general_device_header(header, &bus_device_function); 696 let box_general_device = Box::new(general_device); 697 let box_general_device_clone = box_general_device.clone(); 698 if add_to_list { 699 PCI_DEVICE_LINKEDLIST.add(box_general_device); 700 } 701 Ok(box_general_device_clone) 702 } 703 HeaderType::PciPciBridge => { 704 let pci_to_pci_bridge = pci_read_pci_to_pci_bridge_header(header, &bus_device_function); 705 let box_pci_to_pci_bridge = Box::new(pci_to_pci_bridge); 706 let box_pci_to_pci_bridge_clone = box_pci_to_pci_bridge.clone(); 707 if add_to_list { 708 PCI_DEVICE_LINKEDLIST.add(box_pci_to_pci_bridge); 709 } 710 Ok(box_pci_to_pci_bridge_clone) 711 } 712 HeaderType::PciCardbusBridge => { 713 let pci_cardbus_bridge = 714 pci_read_pci_to_cardbus_bridge_header(header, &bus_device_function); 715 let box_pci_cardbus_bridge = Box::new(pci_cardbus_bridge); 716 let box_pci_cardbus_bridge_clone = box_pci_cardbus_bridge.clone(); 717 if add_to_list { 718 PCI_DEVICE_LINKEDLIST.add(box_pci_cardbus_bridge); 719 } 720 Ok(box_pci_cardbus_bridge_clone) 721 } 722 HeaderType::Unrecognised(_) => Err(PciError::UnrecognisedHeaderType), 723 } 724 } 725 726 /// @brief 读取type为0x0的pci设备的header 727 /// 本函数只应被 pci_read_header()调用 728 /// @param common_header 共有头部 729 /// @param bus_device_function PCI设备的唯一标识 730 /// @return Pci_Device_Structure_General_Device 标准设备头部 731 fn pci_read_general_device_header( 732 common_header: PciDeviceStructureHeader, 733 bus_device_function: &BusDeviceFunction, 734 ) -> PciDeviceStructureGeneralDevice { 735 let standard_device_bar = PciStandardDeviceBar::default(); 736 let cardbus_cis_pointer = PciArch::read_config(bus_device_function, 0x28); 737 738 let result = PciArch::read_config(bus_device_function, 0x2c); 739 let subsystem_vendor_id = result as u16; 740 let subsystem_id = (result >> 16) as u16; 741 742 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x30); 743 744 let result = PciArch::read_config(bus_device_function, 0x34); 745 let capabilities_pointer = result as u8; 746 let reserved0 = (result >> 8) as u8; 747 let reserved1 = (result >> 16) as u16; 748 749 let reserved2 = PciArch::read_config(bus_device_function, 0x38); 750 751 let result = PciArch::read_config(bus_device_function, 0x3c); 752 let interrupt_line = result as u8; 753 let interrupt_pin = (result >> 8) as u8; 754 let min_grant = (result >> 16) as u8; 755 let max_latency = (result >> 24) as u8; 756 PciDeviceStructureGeneralDevice { 757 common_header, 758 standard_device_bar, 759 cardbus_cis_pointer, 760 subsystem_vendor_id, 761 subsystem_id, 762 expansion_rom_base_address, 763 capabilities_pointer, 764 reserved0, 765 reserved1, 766 reserved2, 767 interrupt_line, 768 interrupt_pin, 769 min_grant, 770 max_latency, 771 } 772 } 773 774 /// @brief 读取type为0x1的pci设备的header 775 /// 本函数只应被 pci_read_header()调用 776 /// @param common_header 共有头部 777 /// @param bus_device_function PCI设备的唯一标识 778 /// @return Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci 桥设备头部 779 fn pci_read_pci_to_pci_bridge_header( 780 common_header: PciDeviceStructureHeader, 781 bus_device_function: &BusDeviceFunction, 782 ) -> PciDeviceStructurePciToPciBridge { 783 let bar0 = PciArch::read_config(bus_device_function, 0x10); 784 let bar1 = PciArch::read_config(bus_device_function, 0x14); 785 786 let result = PciArch::read_config(bus_device_function, 0x18); 787 788 let primary_bus_number = result as u8; 789 let secondary_bus_number = (result >> 8) as u8; 790 let subordinate_bus_number = (result >> 16) as u8; 791 let secondary_latency_timer = (result >> 24) as u8; 792 793 let result = PciArch::read_config(bus_device_function, 0x1c); 794 let io_base = result as u8; 795 let io_limit = (result >> 8) as u8; 796 let secondary_status = (result >> 16) as u16; 797 798 let result = PciArch::read_config(bus_device_function, 0x20); 799 let memory_base = result as u16; 800 let memory_limit = (result >> 16) as u16; 801 802 let result = PciArch::read_config(bus_device_function, 0x24); 803 let prefetchable_memory_base = result as u16; 804 let prefetchable_memory_limit = (result >> 16) as u16; 805 806 let prefetchable_base_upper_32_bits = PciArch::read_config(bus_device_function, 0x28); 807 let prefetchable_limit_upper_32_bits = PciArch::read_config(bus_device_function, 0x2c); 808 809 let result = PciArch::read_config(bus_device_function, 0x30); 810 let io_base_upper_16_bits = result as u16; 811 let io_limit_upper_16_bits = (result >> 16) as u16; 812 813 let result = PciArch::read_config(bus_device_function, 0x34); 814 let capability_pointer = result as u8; 815 let reserved0 = (result >> 8) as u8; 816 let reserved1 = (result >> 16) as u16; 817 818 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x38); 819 820 let result = PciArch::read_config(bus_device_function, 0x3c); 821 let interrupt_line = result as u8; 822 let interrupt_pin = (result >> 8) as u8; 823 let bridge_control = (result >> 16) as u16; 824 PciDeviceStructurePciToPciBridge { 825 common_header, 826 bar0, 827 bar1, 828 primary_bus_number, 829 secondary_bus_number, 830 subordinate_bus_number, 831 secondary_latency_timer, 832 io_base, 833 io_limit, 834 secondary_status, 835 memory_base, 836 memory_limit, 837 prefetchable_memory_base, 838 prefetchable_memory_limit, 839 prefetchable_base_upper_32_bits, 840 prefetchable_limit_upper_32_bits, 841 io_base_upper_16_bits, 842 io_limit_upper_16_bits, 843 capability_pointer, 844 reserved0, 845 reserved1, 846 expansion_rom_base_address, 847 interrupt_line, 848 interrupt_pin, 849 bridge_control, 850 } 851 } 852 853 /// @brief 读取type为0x2的pci设备的header 854 /// 本函数只应被 pci_read_header()调用 855 /// @param common_header 共有头部 856 /// @param bus_device_function PCI设备的唯一标识 857 /// @return ) -> Pci_Device_Structure_Pci_to_Cardbus_Bridge pci-to-cardbus 桥设备头部 858 fn pci_read_pci_to_cardbus_bridge_header( 859 common_header: PciDeviceStructureHeader, 860 busdevicefunction: &BusDeviceFunction, 861 ) -> PciDeviceStructurePciToCardbusBridge { 862 let cardbus_socket_ex_ca_base_address = PciArch::read_config(busdevicefunction, 0x10); 863 864 let result = PciArch::read_config(busdevicefunction, 0x14); 865 let offset_of_capabilities_list = result as u8; 866 let reserved = (result >> 8) as u8; 867 let secondary_status = (result >> 16) as u16; 868 869 let result = PciArch::read_config(busdevicefunction, 0x18); 870 let pci_bus_number = result as u8; 871 let card_bus_bus_number = (result >> 8) as u8; 872 let subordinate_bus_number = (result >> 16) as u8; 873 let card_bus_latency_timer = (result >> 24) as u8; 874 875 let memory_base_address0 = PciArch::read_config(busdevicefunction, 0x1c); 876 let memory_limit0 = PciArch::read_config(busdevicefunction, 0x20); 877 let memory_base_address1 = PciArch::read_config(busdevicefunction, 0x24); 878 let memory_limit1 = PciArch::read_config(busdevicefunction, 0x28); 879 880 let io_base_address0 = PciArch::read_config(busdevicefunction, 0x2c); 881 let io_limit0 = PciArch::read_config(busdevicefunction, 0x30); 882 let io_base_address1 = PciArch::read_config(busdevicefunction, 0x34); 883 let io_limit1 = PciArch::read_config(busdevicefunction, 0x38); 884 let result = PciArch::read_config(busdevicefunction, 0x3c); 885 let interrupt_line = result as u8; 886 let interrupt_pin = (result >> 8) as u8; 887 let bridge_control = (result >> 16) as u16; 888 889 let result = PciArch::read_config(busdevicefunction, 0x40); 890 let subsystem_device_id = result as u16; 891 let subsystem_vendor_id = (result >> 16) as u16; 892 893 let pc_card_legacy_mode_base_address_16_bit = PciArch::read_config(busdevicefunction, 0x44); 894 PciDeviceStructurePciToCardbusBridge { 895 common_header, 896 cardbus_socket_ex_ca_base_address, 897 offset_of_capabilities_list, 898 reserved, 899 secondary_status, 900 pci_bus_number, 901 card_bus_bus_number, 902 subordinate_bus_number, 903 card_bus_latency_timer, 904 memory_base_address0, 905 memory_limit0, 906 memory_base_address1, 907 memory_limit1, 908 io_base_address0, 909 io_limit0, 910 io_base_address1, 911 io_limit1, 912 interrupt_line, 913 interrupt_pin, 914 bridge_control, 915 subsystem_device_id, 916 subsystem_vendor_id, 917 pc_card_legacy_mode_base_address_16_bit, 918 } 919 } 920 921 /// @brief 检查所有bus上的设备并将其加入链表 922 /// @return 成功返回ok(),失败返回失败原因 923 fn pci_check_all_buses() -> Result<u8, PciError> { 924 kinfo!("Checking all devices in PCI bus..."); 925 let busdevicefunction = BusDeviceFunction { 926 bus: 0, 927 device: 0, 928 function: 0, 929 }; 930 let header = pci_read_header(busdevicefunction, false)?; 931 let common_header = header.common_header(); 932 pci_check_bus(0)?; 933 if common_header.header_type & 0x80 != 0 { 934 for function in 1..8 { 935 pci_check_bus(function)?; 936 } 937 } 938 Ok(0) 939 } 940 /// @brief 检查特定设备并将其加入链表 941 /// @return 成功返回ok(),失败返回失败原因 942 fn pci_check_function(busdevicefunction: BusDeviceFunction) -> Result<u8, PciError> { 943 //kdebug!("PCI check function {}", busdevicefunction.function); 944 let header = match pci_read_header(busdevicefunction, true) { 945 Ok(header) => header, 946 Err(PciError::GetWrongHeader) => { 947 return Ok(255); 948 } 949 Err(e) => { 950 return Err(e); 951 } 952 }; 953 let common_header = header.common_header(); 954 if (common_header.class_code == 0x06) 955 && (common_header.subclass == 0x04 || common_header.subclass == 0x09) 956 { 957 let pci_to_pci_bridge = header 958 .as_pci_to_pci_bridge_device() 959 .ok_or(PciError::PciDeviceStructureTransformError)?; 960 let secondary_bus = pci_to_pci_bridge.secondary_bus_number; 961 pci_check_bus(secondary_bus)?; 962 } 963 Ok(0) 964 } 965 966 /// @brief 检查device上的设备并将其加入链表 967 /// @return 成功返回ok(),失败返回失败原因 968 fn pci_check_device(bus: u8, device: u8) -> Result<u8, PciError> { 969 //kdebug!("PCI check device {}", device); 970 let busdevicefunction = BusDeviceFunction { 971 bus, 972 device, 973 function: 0, 974 }; 975 let header = match pci_read_header(busdevicefunction, false) { 976 Ok(header) => header, 977 Err(PciError::GetWrongHeader) => { 978 //设备不存在，直接返回即可，不用终止遍历 979 return Ok(255); 980 } 981 Err(e) => { 982 return Err(e); 983 } 984 }; 985 pci_check_function(busdevicefunction)?; 986 let common_header = header.common_header(); 987 if common_header.header_type & 0x80 != 0 { 988 kdebug!( 989 "Detected multi func device in bus{},device{}", 990 busdevicefunction.bus, 991 busdevicefunction.device 992 ); 993 // 这是一个多function的设备，因此查询剩余的function 994 for function in 1..8 { 995 let busdevicefunction = BusDeviceFunction { 996 bus, 997 device, 998 function, 999 }; 1000 pci_check_function(busdevicefunction)?; 1001 } 1002 } 1003 Ok(0) 1004 } 1005 /// @brief 检查该bus上的设备并将其加入链表 1006 /// @return 成功返回ok(),失败返回失败原因 1007 fn pci_check_bus(bus: u8) -> Result<u8, PciError> { 1008 //kdebug!("PCI check bus {}", bus); 1009 for device in 0..32 { 1010 pci_check_device(bus, device)?; 1011 } 1012 Ok(0) 1013 } 1014 /// @brief pci初始化函数(for c) 1015 #[no_mangle] 1016 pub extern "C" fn rs_pci_init() { 1017 pci_init(); 1018 if PCI_ROOT_0.is_some() { 1019 kdebug!("{}", PCI_ROOT_0.unwrap()); 1020 //以下为ecam的读取寄存器值测试，经测试可正常读取 1021 // let bus_device_function = BusDeviceFunction { 1022 // bus: 0, 1023 // device: 2, 1024 // function: 0, 1025 // }; 1026 // kdebug!( 1027 // "Ecam read virtio-net device status={:#x}", 1028 // (PCI_ROOT_0.unwrap().read_config(bus_device_function, 4)>>16) as u16 1029 // ); 1030 } 1031 } 1032 /// @brief pci初始化函数 1033 pub fn pci_init() { 1034 kinfo!("Initializing PCI bus..."); 1035 if let Err(e) = pci_check_all_buses() { 1036 kerror!("pci init failed when checking bus because of error: {}", e); 1037 return; 1038 } 1039 kinfo!( 1040 "Total pci device and function num = {}", 1041 PCI_DEVICE_LINKEDLIST.num() 1042 ); 1043 let list = PCI_DEVICE_LINKEDLIST.read(); 1044 for box_pci_device in list.iter() { 1045 let common_header = box_pci_device.common_header(); 1046 match box_pci_device.header_type() { 1047 HeaderType::Standard if common_header.status & 0x10 != 0 => { 1048 kinfo!("Found pci standard device with class code ={} subclass={} status={:#x} cap_pointer={:#x} vendor={:#x}, device id={:#x},bdf={}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer,common_header.vendor_id, common_header.device_id,common_header.bus_device_function); 1049 } 1050 HeaderType::Standard => { 1051 kinfo!( 1052 "Found pci standard device with class code ={} subclass={} status={:#x} ", 1053 common_header.class_code, 1054 common_header.subclass, 1055 common_header.status 1056 ); 1057 } 1058 HeaderType::PciPciBridge if common_header.status & 0x10 != 0 => { 1059 kinfo!("Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} cap_pointer={:#x}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer); 1060 } 1061 HeaderType::PciPciBridge => { 1062 kinfo!( 1063 "Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} ", 1064 common_header.class_code, 1065 common_header.subclass, 1066 common_header.status 1067 ); 1068 } 1069 HeaderType::PciCardbusBridge => { 1070 kinfo!( 1071 "Found pcicardbus bridge device with class code ={} subclass={} status={:#x} ", 1072 common_header.class_code, 1073 common_header.subclass, 1074 common_header.status 1075 ); 1076 } 1077 HeaderType::Unrecognised(_) => {} 1078 } 1079 } 1080 kinfo!("PCI bus initialized."); 1081 } 1082 1083 /// An identifier for a PCI bus, device and function. 1084 /// PCI设备的唯一标识 1085 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1086 pub struct BusDeviceFunction { 1087 /// The PCI bus number, between 0 and 255. 1088 pub bus: u8, 1089 /// The device number on the bus, between 0 and 31. 1090 pub device: u8, 1091 /// The function number of the device, between 0 and 7. 1092 pub function: u8, 1093 } 1094 impl BusDeviceFunction { 1095 /// Returns whether the device and function numbers are valid, i.e. the device is between 0 and 1096 ///@brief 检测BusDeviceFunction实例是否有效 1097 ///@param self 1098 ///@return bool 是否有效 1099 #[allow(dead_code)] 1100 pub fn valid(&self) -> bool { 1101 self.device < 32 && self.function < 8 1102 } 1103 } 1104 ///实现BusDeviceFunction的Display trait，使其可以直接输出 1105 impl Display for BusDeviceFunction { 1106 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 1107 write!( 1108 f, 1109 "bus {} device {} function{}", 1110 self.bus, self.device, self.function 1111 ) 1112 } 1113 } 1114 /// The location allowed for a memory BAR. 1115 /// memory BAR的三种情况 1116 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1117 pub enum MemoryBarType { 1118 /// The BAR has a 32-bit address and can be mapped anywhere in 32-bit address space. 1119 Width32, 1120 /// The BAR must be mapped below 1MiB. 1121 Below1MiB, 1122 /// The BAR has a 64-bit address and can be mapped anywhere in 64-bit address space. 1123 Width64, 1124 } 1125 ///实现MemoryBarType与u8的类型转换 1126 impl From<MemoryBarType> for u8 { 1127 fn from(bar_type: MemoryBarType) -> Self { 1128 match bar_type { 1129 MemoryBarType::Width32 => 0, 1130 MemoryBarType::Below1MiB => 1, 1131 MemoryBarType::Width64 => 2, 1132 } 1133 } 1134 } 1135 ///实现MemoryBarType与u8的类型转换 1136 impl TryFrom<u8> for MemoryBarType { 1137 type Error = PciError; 1138 fn try_from(value: u8) -> Result<Self, Self::Error> { 1139 match value { 1140 0 => Ok(Self::Width32), 1141 1 => Ok(Self::Below1MiB), 1142 2 => Ok(Self::Width64), 1143 _ => Err(PciError::InvalidBarType), 1144 } 1145 } 1146 } 1147 1148 /// Information about a PCI Base Address Register. 1149 /// BAR的三种类型 Memory/IO/Unused 1150 #[derive(Clone, Debug, Eq, PartialEq)] 1151 pub enum BarInfo { 1152 /// The BAR is for a memory region. 1153 Memory { 1154 /// The size of the BAR address and where it can be located. 1155 address_type: MemoryBarType, 1156 /// If true, then reading from the region doesn't have side effects. The CPU may cache reads 1157 /// and merge repeated stores. 1158 prefetchable: bool, 1159 /// The memory address, always 16-byte aligned. 1160 address: u64, 1161 /// The size of the BAR in bytes. 1162 size: u32, 1163 /// The virtaddress for a memory bar(mapped). 1164 virtaddress: u64, 1165 }, 1166 /// The BAR is for an I/O region. 1167 IO { 1168 /// The I/O address, always 4-byte aligned. 1169 address: u32, 1170 /// The size of the BAR in bytes. 1171 size: u32, 1172 }, 1173 Unused, 1174 } 1175 1176 impl BarInfo { 1177 /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO 1178 /// BAR. 1179 ///@brief 得到某个bar的memory_address与size(前提是他的类型为Memory Bar) 1180 ///@param self 1181 ///@return Option<(u64, u32) 是Memory Bar返回内存地址与大小，不是则返回None 1182 pub fn memory_address_size(&self) -> Option<(u64, u32)> { 1183 if let Self::Memory { address, size, .. } = self { 1184 Some((*address, *size)) 1185 } else { 1186 None 1187 } 1188 } 1189 ///@brief 得到某个bar的virtaddress(前提是他的类型为Memory Bar) 1190 ///@param self 1191 ///@return Option<(u64) 是Memory Bar返回映射的虚拟地址，不是则返回None 1192 pub fn virtual_address(&self) -> Option<u64> { 1193 if let Self::Memory { virtaddress, .. } = self { 1194 Some(*virtaddress) 1195 } else { 1196 None 1197 } 1198 } 1199 } 1200 ///实现BarInfo的Display trait，自定义输出 1201 impl Display for BarInfo { 1202 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1203 match self { 1204 Self::Memory { 1205 address_type, 1206 prefetchable, 1207 address, 1208 size, 1209 virtaddress, 1210 } => write!( 1211 f, 1212 "Memory space at {:#010x}, size {}, type {:?}, prefetchable {},mapped at {:#x}", 1213 address, size, address_type, prefetchable, virtaddress 1214 ), 1215 Self::IO { address, size } => { 1216 write!(f, "I/O space at {:#010x}, size {}", address, size) 1217 } 1218 Self::Unused => { 1219 write!(f, "Unused bar") 1220 } 1221 } 1222 } 1223 } 1224 ///一个普通PCI设备（非桥）有6个BAR寄存器，PciStandardDeviceBar存储其全部信息 1225 #[derive(Clone, Debug, Eq, PartialEq)] 1226 pub struct PciStandardDeviceBar { 1227 bar0: BarInfo, 1228 bar1: BarInfo, 1229 bar2: BarInfo, 1230 bar3: BarInfo, 1231 bar4: BarInfo, 1232 bar5: BarInfo, 1233 } 1234 1235 impl PciStandardDeviceBar { 1236 ///@brief 得到某个bar的barinfo 1237 ///@param self ，bar_index(0-5) 1238 ///@return Result<&BarInfo, PciError> bar_index在0-5则返回对应的bar_info结构体，超出范围则返回错误 1239 pub fn get_bar(&self, bar_index: u8) -> Result<&BarInfo, PciError> { 1240 match bar_index { 1241 0 => Ok(&self.bar0), 1242 1 => Ok(&self.bar1), 1243 2 => Ok(&self.bar2), 1244 3 => Ok(&self.bar3), 1245 4 => Ok(&self.bar4), 1246 5 => Ok(&self.bar5), 1247 _ => Err(PciError::InvalidBarType), 1248 } 1249 } 1250 } 1251 ///实现PciStandardDeviceBar的Display trait，使其可以直接输出 1252 impl Display for PciStandardDeviceBar { 1253 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1254 write!( 1255 f, 1256 "\r\nBar0:{}\r\n Bar1:{}\r\n Bar2:{}\r\n Bar3:{}\r\nBar4:{}\r\nBar5:{}", 1257 self.bar0, self.bar1, self.bar2, self.bar3, self.bar4, self.bar5 1258 ) 1259 } 1260 } 1261 ///实现PciStandardDeviceBar的Default trait，使其可以简单初始化 1262 impl Default for PciStandardDeviceBar { 1263 fn default() -> Self { 1264 PciStandardDeviceBar { 1265 bar0: BarInfo::Unused, 1266 bar1: BarInfo::Unused, 1267 bar2: BarInfo::Unused, 1268 bar3: BarInfo::Unused, 1269 bar4: BarInfo::Unused, 1270 bar5: BarInfo::Unused, 1271 } 1272 } 1273 } 1274 1275 ///@brief 将某个pci设备的bar寄存器读取值后映射到虚拟地址 1276 ///@param self ，bus_device_function PCI设备的唯一标识符 1277 ///@return Result<PciStandardDeviceBar, PciError> 成功则返回对应的PciStandardDeviceBar结构体，失败则返回错误类型 1278 pub fn pci_bar_init( 1279 bus_device_function: BusDeviceFunction, 1280 ) -> Result<PciStandardDeviceBar, PciError> { 1281 let mut device_bar: PciStandardDeviceBar = PciStandardDeviceBar::default(); 1282 let mut bar_index_ignore: u8 = 255; 1283 for bar_index in 0..6 { 1284 if bar_index == bar_index_ignore { 1285 continue; 1286 } 1287 let bar_info; 1288 let mut virtaddress: u64 = 0; 1289 let bar_orig = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1290 PciArch::write_config( 1291 &bus_device_function, 1292 BAR0_OFFSET + 4 * bar_index, 1293 0xffffffff, 1294 ); 1295 let size_mask = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1296 // A wrapping add is necessary to correctly handle the case of unused BARs, which read back 1297 // as 0, and should be treated as size 0. 1298 let size = (!(size_mask & 0xfffffff0)).wrapping_add(1); 1299 //kdebug!("bar_orig:{:#x},size: {:#x}", bar_orig,size); 1300 // Restore the original value. 1301 PciArch::write_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index, bar_orig); 1302 if size == 0 { 1303 continue; 1304 } 1305 if bar_orig & 0x00000001 == 0x00000001 { 1306 // I/O space 1307 let address = bar_orig & 0xfffffffc; 1308 bar_info = BarInfo::IO { address, size }; 1309 } else { 1310 // Memory space 1311 let mut address = u64::from(bar_orig & 0xfffffff0); 1312 let prefetchable = bar_orig & 0x00000008 != 0; 1313 let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?; 1314 if address_type == MemoryBarType::Width64 { 1315 if bar_index >= 5 { 1316 return Err(PciError::InvalidBarType); 1317 } 1318 let address_top = 1319 PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * (bar_index + 1)); 1320 address |= u64::from(address_top) << 32; 1321 bar_index_ignore = bar_index + 1; //下个bar跳过，因为64位的memory bar覆盖了两个bar 1322 } 1323 let pci_address = PciAddr::new(address as usize); 1324 address = PciArch::address_pci_to_physical(pci_address) as u64; //PCI总线域物理地址转换为存储器域物理地址 1325 unsafe { 1326 let vaddr_ptr = &mut virtaddress as *mut u64; 1327 let mut virtsize: u64 = 0; 1328 let virtsize_ptr = &mut virtsize as *mut u64; 1329 let initial_mm_ptr = &mut initial_mm as *mut mm_struct; 1330 //kdebug!("size want={:#x}", size); 1331 if let Err(_) = MMIO_POOL.create_mmio( 1332 size, 1333 (VM_IO | VM_DONTCOPY) as u64, 1334 vaddr_ptr, 1335 virtsize_ptr, 1336 ) { 1337 kerror!("Create mmio failed when initing pci bar"); 1338 return Err(PciError::CreateMmioError); 1339 }; 1340 //kdebug!("virtaddress={:#x},virtsize={:#x}",virtaddress,virtsize); 1341 mm_map(initial_mm_ptr, virtaddress, size as u64, address); 1342 } 1343 bar_info = BarInfo::Memory { 1344 address_type, 1345 prefetchable, 1346 address, 1347 size, 1348 virtaddress, 1349 }; 1350 } 1351 match bar_index { 1352 0 => { 1353 device_bar.bar0 = bar_info; 1354 } 1355 1 => { 1356 device_bar.bar1 = bar_info; 1357 } 1358 2 => { 1359 device_bar.bar2 = bar_info; 1360 } 1361 3 => { 1362 device_bar.bar3 = bar_info; 1363 } 1364 4 => { 1365 device_bar.bar4 = bar_info; 1366 } 1367 5 => { 1368 device_bar.bar5 = bar_info; 1369 } 1370 _ => {} 1371 } 1372 } 1373 kdebug!("pci_device_bar:{}", device_bar); 1374 return Ok(device_bar); 1375 } 1376 1377 /// Information about a PCI device capability. 1378 /// PCI设备的capability的信息 1379 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1380 pub struct CapabilityInfo { 1381 /// The offset of the capability in the PCI configuration space of the device function. 1382 pub offset: u8, 1383 /// The ID of the capability. 1384 pub id: u8, 1385 /// The third and fourth bytes of the capability, to save reading them again. 1386 pub private_header: u16, 1387 } 1388 1389 /// Iterator over capabilities for a device. 1390 /// 创建迭代器以遍历PCI设备的capability 1391 #[derive(Debug)] 1392 pub struct CapabilityIterator { 1393 pub bus_device_function: BusDeviceFunction, 1394 pub next_capability_offset: Option<u8>, 1395 } 1396 1397 impl Iterator for CapabilityIterator { 1398 type Item = CapabilityInfo; 1399 fn next(&mut self) -> Option<Self::Item> { 1400 let offset = self.next_capability_offset?; 1401 1402 // Read the first 4 bytes of the capability. 1403 let capability_header = PciArch::read_config(&self.bus_device_function, offset); 1404 let id = capability_header as u8; 1405 let next_offset = (capability_header >> 8) as u8; 1406 let private_header = (capability_header >> 16) as u16; 1407 1408 self.next_capability_offset = if next_offset == 0 { 1409 None 1410 } else if next_offset < 64 || next_offset & 0x3 != 0 { 1411 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1412 None 1413 } else { 1414 Some(next_offset) 1415 }; 1416 1417 Some(CapabilityInfo { 1418 offset, 1419 id, 1420 private_header, 1421 }) 1422 } 1423 } 1424 1425 /// Information about a PCIe device capability. 1426 /// PCIe设备的external capability的信息 1427 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1428 pub struct ExternalCapabilityInfo { 1429 /// The offset of the capability in the PCI configuration space of the device function. 1430 pub offset: u16, 1431 /// The ID of the capability. 1432 pub id: u16, 1433 /// The third and fourth bytes of the capability, to save reading them again. 1434 pub capability_version: u8, 1435 } 1436 1437 /// Iterator over capabilities for a device. 1438 /// 创建迭代器以遍历PCIe设备的external capability 1439 #[derive(Debug)] 1440 pub struct ExternalCapabilityIterator<'a> { 1441 pub root: &'a PciRoot, 1442 pub bus_device_function: BusDeviceFunction, 1443 pub next_capability_offset: Option<u16>, 1444 } 1445 impl<'a> Iterator for ExternalCapabilityIterator<'a> { 1446 type Item = ExternalCapabilityInfo; 1447 fn next(&mut self) -> Option<Self::Item> { 1448 let offset = self.next_capability_offset?; 1449 1450 // Read the first 4 bytes of the capability. 1451 let capability_header = self.root.read_config(self.bus_device_function, offset); 1452 let id = capability_header as u16; 1453 let next_offset = (capability_header >> 20) as u16; 1454 let capability_version = ((capability_header >> 16) & 0xf) as u8; 1455 1456 self.next_capability_offset = if next_offset == 0 { 1457 None 1458 } else if next_offset < 0x100 || next_offset & 0x3 != 0 { 1459 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1460 None 1461 } else { 1462 Some(next_offset) 1463 }; 1464 1465 Some(ExternalCapabilityInfo { 1466 offset, 1467 id, 1468 capability_version, 1469 }) 1470 } 1471 } 1472