1 #![allow(dead_code)] 2 // 目前仅支持单主桥单Segment 3 4 use super::pci_irq::{IrqType, PciIrqError}; 5 use crate::arch::{PciArch, TraitPciArch}; 6 use crate::exception::IrqNumber; 7 use crate::include::bindings::bindings::PAGE_2M_SIZE; 8 use crate::libs::rwlock::{RwLock, RwLockReadGuard, RwLockWriteGuard}; 9 10 use crate::mm::mmio_buddy::{mmio_pool, MMIOSpaceGuard}; 11 12 use crate::mm::{PhysAddr, VirtAddr}; 13 use crate::{kdebug, kerror, kinfo, kwarn}; 14 use alloc::sync::Arc; 15 use alloc::vec::Vec; 16 use alloc::{boxed::Box, collections::LinkedList}; 17 use bitflags::bitflags; 18 19 use core::{ 20 convert::TryFrom, 21 fmt::{self, Debug, Display, Formatter}, 22 }; 23 // PCI_DEVICE_LINKEDLIST 添加了读写锁的全局链表，里面存储了检索到的PCI设备结构体 24 // PCI_ROOT_0 Segment为0的全局PciRoot 25 lazy_static! { 26 pub static ref PCI_DEVICE_LINKEDLIST: PciDeviceLinkedList = PciDeviceLinkedList::new(); 27 pub static ref PCI_ROOT_0: Option<PciRoot> = { 28 match PciRoot::new(0) { 29 Ok(root) => Some(root), 30 Err(err) => { 31 kerror!("Pci_root init failed because of error: {}", err); 32 None 33 } 34 } 35 }; 36 } 37 /// PCI域地址 38 #[derive(Clone, Copy, Eq, Ord, PartialEq, PartialOrd)] 39 #[repr(transparent)] 40 pub struct PciAddr(usize); 41 42 impl PciAddr { 43 #[inline(always)] 44 pub const fn new(address: usize) -> Self { 45 Self(address) 46 } 47 48 /// @brief 获取PCI域地址的值 49 #[inline(always)] 50 pub fn data(&self) -> usize { 51 self.0 52 } 53 54 /// @brief 将PCI域地址加上一个偏移量 55 #[inline(always)] 56 pub fn add(self, offset: usize) -> Self { 57 Self(self.0 + offset) 58 } 59 60 /// @brief 判断PCI域地址是否按照指定要求对齐 61 #[inline(always)] 62 pub fn check_aligned(&self, align: usize) -> bool { 63 return self.0 & (align - 1) == 0; 64 } 65 } 66 impl Debug for PciAddr { 67 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { 68 write!(f, "PciAddr({:#x})", self.0) 69 } 70 } 71 72 /// 添加了读写锁的链表，存储PCI设备结构体 73 pub struct PciDeviceLinkedList { 74 list: RwLock<LinkedList<Box<dyn PciDeviceStructure>>>, 75 } 76 77 impl PciDeviceLinkedList { 78 /// @brief 初始化结构体 79 fn new() -> Self { 80 PciDeviceLinkedList { 81 list: RwLock::new(LinkedList::new()), 82 } 83 } 84 /// @brief 获取可读的linkedlist(读锁守卫) 85 /// @return RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> 读锁守卫 86 pub fn read(&self) -> RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 87 self.list.read() 88 } 89 /// @brief 获取可写的linkedlist(写锁守卫) 90 /// @return RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> 写锁守卫 91 pub fn write(&self) -> RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 92 self.list.write() 93 } 94 /// @brief 获取链表中PCI结构体数目 95 /// @return usize 链表中PCI结构体数目 96 pub fn num(&self) -> usize { 97 let list = self.list.read(); 98 list.len() 99 } 100 /// @brief 添加Pci设备结构体到链表中 101 pub fn add(&self, device: Box<dyn PciDeviceStructure>) { 102 let mut list = self.list.write(); 103 list.push_back(device); 104 } 105 } 106 107 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其可变引用 108 /// @param list 链表的写锁守卫 109 /// @param class_code 寄存器值 110 /// @param subclass 寄存器值，与class_code一起确定设备类型 111 /// @return Vec<&'a mut Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的可变引用的容器 112 pub fn get_pci_device_structure_mut<'a>( 113 list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 114 class_code: u8, 115 subclass: u8, 116 ) -> Vec<&'a mut Box<(dyn PciDeviceStructure)>> { 117 let mut result = Vec::new(); 118 for box_pci_device_structure in list.iter_mut() { 119 let common_header = (*box_pci_device_structure).common_header(); 120 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 121 result.push(box_pci_device_structure); 122 } 123 } 124 result 125 } 126 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其不可变引用 127 /// @param list 链表的读锁守卫 128 /// @param class_code 寄存器值 129 /// @param subclass 寄存器值，与class_code一起确定设备类型 130 /// @return Vec<&'a Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的不可变引用的容器 131 #[allow(clippy::borrowed_box)] 132 pub fn get_pci_device_structure<'a>( 133 list: &'a mut RwLockReadGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 134 class_code: u8, 135 subclass: u8, 136 ) -> Vec<&'a Box<(dyn PciDeviceStructure)>> { 137 let mut result = Vec::new(); 138 for box_pci_device_structure in list.iter() { 139 let common_header = (*box_pci_device_structure).common_header(); 140 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 141 result.push(box_pci_device_structure); 142 } 143 } 144 result 145 } 146 147 //Bar0寄存器的offset 148 const BAR0_OFFSET: u8 = 0x10; 149 //Status、Command寄存器的offset 150 const STATUS_COMMAND_OFFSET: u8 = 0x04; 151 /// ID for vendor-specific PCI capabilities.(Virtio Capabilities) 152 pub const PCI_CAP_ID_VNDR: u8 = 0x09; 153 pub const PCI_CAP_ID_MSI: u8 = 0x05; 154 pub const PCI_CAP_ID_MSIX: u8 = 0x11; 155 pub const PORT_PCI_CONFIG_ADDRESS: u16 = 0xcf8; 156 pub const PORT_PCI_CONFIG_DATA: u16 = 0xcfc; 157 // pci设备分组的id 158 pub type SegmentGroupNumber = u16; //理论上最多支持65535个Segment_Group 159 160 bitflags! { 161 /// The status register in PCI configuration space. 162 pub struct Status: u16 { 163 // Bits 0-2 are reserved. 164 /// The state of the device's INTx# signal. 165 const INTERRUPT_STATUS = 1 << 3; 166 /// The device has a linked list of capabilities. 167 const CAPABILITIES_LIST = 1 << 4; 168 /// The device is capabile of running at 66 MHz rather than 33 MHz. 169 const MHZ_66_CAPABLE = 1 << 5; 170 // Bit 6 is reserved. 171 /// The device can accept fast back-to-back transactions not from the same agent. 172 const FAST_BACK_TO_BACK_CAPABLE = 1 << 7; 173 /// The bus agent observed a parity error (if parity error handling is enabled). 174 const MASTER_DATA_PARITY_ERROR = 1 << 8; 175 // Bits 9-10 are DEVSEL timing. 176 /// A target device terminated a transaction with target-abort. 177 const SIGNALED_TARGET_ABORT = 1 << 11; 178 /// A master device transaction was terminated with target-abort. 179 const RECEIVED_TARGET_ABORT = 1 << 12; 180 /// A master device transaction was terminated with master-abort. 181 const RECEIVED_MASTER_ABORT = 1 << 13; 182 /// A device asserts SERR#. 183 const SIGNALED_SYSTEM_ERROR = 1 << 14; 184 /// The device detects a parity error, even if parity error handling is disabled. 185 const DETECTED_PARITY_ERROR = 1 << 15; 186 } 187 } 188 189 bitflags! { 190 /// The command register in PCI configuration space. 191 pub struct Command: u16 { 192 /// The device can respond to I/O Space accesses. 193 const IO_SPACE = 1 << 0; 194 /// The device can respond to Memory Space accesses. 195 const MEMORY_SPACE = 1 << 1; 196 /// The device can behave as a bus master. 197 const BUS_MASTER = 1 << 2; 198 /// The device can monitor Special Cycle operations. 199 const SPECIAL_CYCLES = 1 << 3; 200 /// The device can generate the Memory Write and Invalidate command. 201 const MEMORY_WRITE_AND_INVALIDATE_ENABLE = 1 << 4; 202 /// The device will snoop palette register data. 203 const VGA_PALETTE_SNOOP = 1 << 5; 204 /// The device should take its normal action when a parity error is detected. 205 const PARITY_ERROR_RESPONSE = 1 << 6; 206 // Bit 7 is reserved. 207 /// The SERR# driver is enabled. 208 const SERR_ENABLE = 1 << 8; 209 /// The device is allowed to generate fast back-to-back transactions. 210 const FAST_BACK_TO_BACK_ENABLE = 1 << 9; 211 /// Assertion of the device's INTx# signal is disabled. 212 const INTERRUPT_DISABLE = 1 << 10; 213 } 214 } 215 216 /// The type of a PCI device function header. 217 /// 标头类型/设备类型 218 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 219 pub enum HeaderType { 220 /// A normal PCI device. 221 Standard, 222 /// A PCI to PCI bridge. 223 PciPciBridge, 224 /// A PCI to CardBus bridge. 225 PciCardbusBridge, 226 /// Unrecognised header type. 227 Unrecognised(u8), 228 } 229 /// u8到HeaderType的转换 230 impl From<u8> for HeaderType { 231 fn from(value: u8) -> Self { 232 match value { 233 0x00 => Self::Standard, 234 0x01 => Self::PciPciBridge, 235 0x02 => Self::PciCardbusBridge, 236 _ => Self::Unrecognised(value), 237 } 238 } 239 } 240 /// Pci可能触发的各种错误 241 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 242 pub enum PciError { 243 /// The device reported an invalid BAR type. 244 InvalidBarType, 245 CreateMmioError, 246 InvalidBusDeviceFunction, 247 SegmentNotFound, 248 McfgTableNotFound, 249 GetWrongHeader, 250 UnrecognisedHeaderType, 251 PciDeviceStructureTransformError, 252 PciIrqError(PciIrqError), 253 } 254 ///实现PciError的Display trait，使其可以直接输出 255 impl Display for PciError { 256 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 257 match self { 258 Self::InvalidBarType => write!(f, "Invalid PCI BAR type."), 259 Self::CreateMmioError => write!(f, "Error occurred while creating mmio."), 260 Self::InvalidBusDeviceFunction => write!(f, "Found invalid BusDeviceFunction."), 261 Self::SegmentNotFound => write!(f, "Target segment not found"), 262 Self::McfgTableNotFound => write!(f, "ACPI MCFG Table not found"), 263 Self::GetWrongHeader => write!(f, "GetWrongHeader with vendor id 0xffff"), 264 Self::UnrecognisedHeaderType => write!(f, "Found device with unrecognised header type"), 265 Self::PciDeviceStructureTransformError => { 266 write!(f, "Found None When transform Pci device structure") 267 } 268 Self::PciIrqError(err) => write!(f, "Error occurred while setting irq :{:?}.", err), 269 } 270 } 271 } 272 273 /// trait类型Pci_Device_Structure表示pci设备，动态绑定三种具体设备类型：Pci_Device_Structure_General_Device、Pci_Device_Structure_Pci_to_Pci_Bridge、Pci_Device_Structure_Pci_to_Cardbus_Bridge 274 pub trait PciDeviceStructure: Send + Sync { 275 /// @brief 获取设备类型 276 /// @return HeaderType 设备类型 277 fn header_type(&self) -> HeaderType; 278 /// @brief 当其为standard设备时返回&Pci_Device_Structure_General_Device，其余情况返回None 279 #[inline(always)] 280 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 281 None 282 } 283 /// @brief 当其为pci to pci bridge设备时返回&Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 284 #[inline(always)] 285 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 286 None 287 } 288 /// @brief 当其为pci to cardbus bridge设备时返回&Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 289 #[inline(always)] 290 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 291 None 292 } 293 /// @brief 获取Pci设备共有的common_header 294 /// @return 返回其不可变引用 295 fn common_header(&self) -> &PciDeviceStructureHeader; 296 /// @brief 当其为standard设备时返回&mut Pci_Device_Structure_General_Device，其余情况返回None 297 #[inline(always)] 298 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 299 None 300 } 301 /// @brief 当其为pci to pci bridge设备时返回&mut Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 302 #[inline(always)] 303 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 304 None 305 } 306 /// @brief 当其为pci to cardbus bridge设备时返回&mut Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 307 #[inline(always)] 308 fn as_pci_to_carbus_bridge_device_mut( 309 &mut self, 310 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 311 None 312 } 313 /// @brief 返回迭代器，遍历capabilities 314 fn capabilities(&self) -> Option<CapabilityIterator> { 315 None 316 } 317 /// @brief 获取Status、Command寄存器的值 318 fn status_command(&self) -> (Status, Command) { 319 let common_header = self.common_header(); 320 let status = Status::from_bits_truncate(common_header.status); 321 let command = Command::from_bits_truncate(common_header.command); 322 (status, command) 323 } 324 /// @brief 设置Command寄存器的值 325 fn set_command(&mut self, command: Command) { 326 let common_header = self.common_header_mut(); 327 let command = command.bits(); 328 common_header.command = command; 329 PciArch::write_config( 330 &common_header.bus_device_function, 331 STATUS_COMMAND_OFFSET, 332 command as u32, 333 ); 334 } 335 /// @brief 获取Pci设备共有的common_header 336 /// @return 返回其可变引用 337 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader; 338 339 /// @brief 读取standard设备的bar寄存器，映射后将结果加入结构体的standard_device_bar变量 340 /// @return 只有standard设备才返回成功或者错误，其余返回None 341 #[inline(always)] 342 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 343 None 344 } 345 /// @brief 获取PCI设备的bar寄存器的引用 346 /// @return 347 #[inline(always)] 348 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 349 None 350 } 351 /// @brief 通过设置该pci设备的command 352 fn enable_master(&mut self) { 353 self.set_command(Command::IO_SPACE | Command::MEMORY_SPACE | Command::BUS_MASTER); 354 } 355 /// @brief 寻找设备的msix空间的offset 356 fn msix_capability_offset(&self) -> Option<u8> { 357 for capability in self.capabilities()? { 358 if capability.id == PCI_CAP_ID_MSIX { 359 return Some(capability.offset); 360 } 361 } 362 None 363 } 364 /// @brief 寻找设备的msi空间的offset 365 fn msi_capability_offset(&self) -> Option<u8> { 366 for capability in self.capabilities()? { 367 if capability.id == PCI_CAP_ID_MSI { 368 return Some(capability.offset); 369 } 370 } 371 None 372 } 373 /// @brief 返回结构体中的irq_type的可变引用 374 fn irq_type_mut(&mut self) -> Option<&mut IrqType>; 375 /// @brief 返回结构体中的irq_vector的可变引用 376 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>>; 377 } 378 379 /// Pci_Device_Structure_Header PCI设备结构体共有的头部 380 #[derive(Clone, Debug)] 381 pub struct PciDeviceStructureHeader { 382 // ==== busdevicefunction变量表示该结构体所处的位置 383 pub bus_device_function: BusDeviceFunction, 384 pub vendor_id: u16, // 供应商ID 0xffff是一个无效值，在读取访问不存在的设备的配置空间寄存器时返回 385 pub device_id: u16, // 设备ID，标志特定设备 386 pub command: u16, // 提供对设备生成和响应pci周期的能力的控制 向该寄存器写入0时，设备与pci总线断开除配置空间访问以外的所有连接 387 pub status: u16, // 用于记录pci总线相关时间的状态信息寄存器 388 pub revision_id: u8, // 修订ID，指定特定设备的修订标志符 389 pub prog_if: u8, // 编程接口字节，一个只读寄存器，指定设备具有的寄存器级别的编程接口（如果有的话） 390 pub subclass: u8, // 子类。指定设备执行的特定功能的只读寄存器 391 pub class_code: u8, // 类代码，一个只读寄存器，指定设备执行的功能类型 392 pub cache_line_size: u8, // 缓存线大小：以 32 位为单位指定系统缓存线大小。设备可以限制它可以支持的缓存线大小的数量，如果不支持的值写入该字段，设备将表现得好像写入了 0 值 393 pub latency_timer: u8, // 延迟计时器：以 PCI 总线时钟为单位指定延迟计时器。 394 pub header_type: u8, // 标头类型 a value of 0x0 specifies a general device, a value of 0x1 specifies a PCI-to-PCI bridge, and a value of 0x2 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device. 395 pub bist: u8, // Represents that status and allows control of a devices BIST (built-in self test). 396 // Here is the layout of the BIST register: 397 // | bit7 | bit6 | Bits 5-4 | Bits 3-0 | 398 // | BIST Capable | Start BIST | Reserved | Completion Code | 399 // for more details, please visit https://wiki.osdev.org/PCI 400 } 401 402 /// Pci_Device_Structure_General_Device PCI标准设备结构体 403 #[derive(Clone, Debug)] 404 pub struct PciDeviceStructureGeneralDevice { 405 pub common_header: PciDeviceStructureHeader, 406 // 中断结构体，包括legacy,msi,msix三种情况 407 pub irq_type: IrqType, 408 // 使用的中断号的vec集合 409 pub irq_vector: Vec<IrqNumber>, 410 pub standard_device_bar: PciStandardDeviceBar, 411 pub cardbus_cis_pointer: u32, // 指向卡信息结构，供在 CardBus 和 PCI 之间共享芯片的设备使用。 412 pub subsystem_vendor_id: u16, 413 pub subsystem_id: u16, 414 pub expansion_rom_base_address: u32, 415 pub capabilities_pointer: u8, 416 pub reserved0: u8, 417 pub reserved1: u16, 418 pub reserved2: u32, 419 pub interrupt_line: u8, // 指定设备的中断引脚连接到系统中断控制器的哪个输入，并由任何使用中断引脚的设备实现。对于 x86 架构，此寄存器对应于 PIC IRQ 编号 0-15（而不是 I/O APIC IRQ 编号），并且值0xFF定义为无连接。 420 pub interrupt_pin: u8, // 指定设备使用的中断引脚。其中值为0x1INTA#、0x2INTB#、0x3INTC#、0x4INTD#，0x0表示设备不使用中断引脚。 421 pub min_grant: u8, // 一个只读寄存器，用于指定设备所需的突发周期长度（以 1/4 微秒为单位）（假设时钟速率为 33 MHz） 422 pub max_latency: u8, // 一个只读寄存器，指定设备需要多长时间访问一次 PCI 总线（以 1/4 微秒为单位）。 423 } 424 impl PciDeviceStructure for PciDeviceStructureGeneralDevice { 425 #[inline(always)] 426 fn header_type(&self) -> HeaderType { 427 HeaderType::Standard 428 } 429 #[inline(always)] 430 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 431 Some(self) 432 } 433 #[inline(always)] 434 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 435 Some(self) 436 } 437 #[inline(always)] 438 fn common_header(&self) -> &PciDeviceStructureHeader { 439 &self.common_header 440 } 441 #[inline(always)] 442 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 443 &mut self.common_header 444 } 445 fn capabilities(&self) -> Option<CapabilityIterator> { 446 Some(CapabilityIterator { 447 bus_device_function: self.common_header.bus_device_function, 448 next_capability_offset: Some(self.capabilities_pointer), 449 }) 450 } 451 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 452 let common_header = &self.common_header; 453 match pci_bar_init(common_header.bus_device_function) { 454 Ok(bar) => { 455 self.standard_device_bar = bar; 456 Some(Ok(0)) 457 } 458 Err(e) => Some(Err(e)), 459 } 460 } 461 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 462 Some(&self.standard_device_bar) 463 } 464 #[inline(always)] 465 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 466 Some(&mut self.irq_type) 467 } 468 #[inline(always)] 469 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>> { 470 Some(&mut self.irq_vector) 471 } 472 } 473 474 /// Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci桥设备结构体 475 #[derive(Clone, Debug)] 476 pub struct PciDeviceStructurePciToPciBridge { 477 pub common_header: PciDeviceStructureHeader, 478 // 中断结构体，包括legacy,msi,msix三种情况 479 pub irq_type: IrqType, 480 // 使用的中断号的vec集合 481 pub irq_vector: Vec<IrqNumber>, 482 pub bar0: u32, 483 pub bar1: u32, 484 pub primary_bus_number: u8, 485 pub secondary_bus_number: u8, 486 pub subordinate_bus_number: u8, 487 pub secondary_latency_timer: u8, 488 pub io_base: u8, 489 pub io_limit: u8, 490 pub secondary_status: u16, 491 pub memory_base: u16, 492 pub memory_limit: u16, 493 pub prefetchable_memory_base: u16, 494 pub prefetchable_memory_limit: u16, 495 pub prefetchable_base_upper_32_bits: u32, 496 pub prefetchable_limit_upper_32_bits: u32, 497 pub io_base_upper_16_bits: u16, 498 pub io_limit_upper_16_bits: u16, 499 pub capability_pointer: u8, 500 pub reserved0: u8, 501 pub reserved1: u16, 502 pub expansion_rom_base_address: u32, 503 pub interrupt_line: u8, 504 pub interrupt_pin: u8, 505 pub bridge_control: u16, 506 } 507 impl PciDeviceStructure for PciDeviceStructurePciToPciBridge { 508 #[inline(always)] 509 fn header_type(&self) -> HeaderType { 510 HeaderType::PciPciBridge 511 } 512 #[inline(always)] 513 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 514 Some(self) 515 } 516 #[inline(always)] 517 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 518 Some(self) 519 } 520 #[inline(always)] 521 fn common_header(&self) -> &PciDeviceStructureHeader { 522 &self.common_header 523 } 524 #[inline(always)] 525 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 526 &mut self.common_header 527 } 528 #[inline(always)] 529 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 530 Some(&mut self.irq_type) 531 } 532 #[inline(always)] 533 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>> { 534 Some(&mut self.irq_vector) 535 } 536 } 537 /// Pci_Device_Structure_Pci_to_Cardbus_Bridge Pci_to_Cardbus桥设备结构体 538 #[derive(Clone, Debug)] 539 pub struct PciDeviceStructurePciToCardbusBridge { 540 pub common_header: PciDeviceStructureHeader, 541 pub cardbus_socket_ex_ca_base_address: u32, 542 pub offset_of_capabilities_list: u8, 543 pub reserved: u8, 544 pub secondary_status: u16, 545 pub pci_bus_number: u8, 546 pub card_bus_bus_number: u8, 547 pub subordinate_bus_number: u8, 548 pub card_bus_latency_timer: u8, 549 pub memory_base_address0: u32, 550 pub memory_limit0: u32, 551 pub memory_base_address1: u32, 552 pub memory_limit1: u32, 553 pub io_base_address0: u32, 554 pub io_limit0: u32, 555 pub io_base_address1: u32, 556 pub io_limit1: u32, 557 pub interrupt_line: u8, 558 pub interrupt_pin: u8, 559 pub bridge_control: u16, 560 pub subsystem_device_id: u16, 561 pub subsystem_vendor_id: u16, 562 pub pc_card_legacy_mode_base_address_16_bit: u32, 563 } 564 impl PciDeviceStructure for PciDeviceStructurePciToCardbusBridge { 565 #[inline(always)] 566 fn header_type(&self) -> HeaderType { 567 HeaderType::PciCardbusBridge 568 } 569 #[inline(always)] 570 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 571 Some(self) 572 } 573 #[inline(always)] 574 fn as_pci_to_carbus_bridge_device_mut( 575 &mut self, 576 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 577 Some(self) 578 } 579 #[inline(always)] 580 fn common_header(&self) -> &PciDeviceStructureHeader { 581 &self.common_header 582 } 583 #[inline(always)] 584 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 585 &mut self.common_header 586 } 587 #[inline(always)] 588 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 589 None 590 } 591 #[inline(always)] 592 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>> { 593 None 594 } 595 } 596 597 /// 代表一个PCI segement greoup. 598 #[derive(Clone, Debug)] 599 pub struct PciRoot { 600 pub physical_address_base: PhysAddr, //物理地址，acpi获取 601 pub mmio_guard: Option<Arc<MMIOSpaceGuard>>, //映射后的虚拟地址，为方便访问数据这里转化成指针 602 pub segement_group_number: SegmentGroupNumber, //segement greoup的id 603 pub bus_begin: u8, //该分组中的最小bus 604 pub bus_end: u8, //该分组中的最大bus 605 } 606 ///线程间共享需要，该结构体只需要在初始化时写入数据，无需读写锁保证线程安全 607 unsafe impl Send for PciRoot {} 608 unsafe impl Sync for PciRoot {} 609 ///实现PciRoot的Display trait，自定义输出 610 impl Display for PciRoot { 611 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 612 write!( 613 f, 614 "PCI Root with segement:{}, bus begin at {}, bus end at {}, physical address at {:?},mapped at {:?}", 615 self.segement_group_number, self.bus_begin, self.bus_end, self.physical_address_base, self.mmio_guard 616 ) 617 } 618 } 619 620 impl PciRoot { 621 /// @brief 初始化结构体，获取ecam root所在物理地址后map到虚拟地址，再将该虚拟地址加入mmio_base变量 622 /// @return 成功返回结果，错误返回错误类型 623 pub fn new(segment_group_number: SegmentGroupNumber) -> Result<Self, PciError> { 624 let mut pci_root = PciArch::ecam_root(segment_group_number)?; 625 pci_root.map()?; 626 Ok(pci_root) 627 } 628 /// @brief 完成物理地址到虚拟地址的映射，并将虚拟地址加入mmio_base变量 629 /// @return 返回错误或Ok(0) 630 fn map(&mut self) -> Result<u8, PciError> { 631 //kdebug!("bus_begin={},bus_end={}", self.bus_begin,self.bus_end); 632 let bus_number = (self.bus_end - self.bus_begin) as u32 + 1; 633 let bus_number_double = (bus_number - 1) / 2 + 1; //一个bus占据1MB空间，计算全部bus占据空间相对于2MB空间的个数 634 635 let size = (bus_number_double as usize) * (PAGE_2M_SIZE as usize); 636 unsafe { 637 let space_guard = mmio_pool() 638 .create_mmio(size) 639 .map_err(|_| PciError::CreateMmioError)?; 640 let space_guard = Arc::new(space_guard); 641 self.mmio_guard = Some(space_guard.clone()); 642 643 assert!(space_guard 644 .map_phys(self.physical_address_base, size) 645 .is_ok()); 646 } 647 return Ok(0); 648 } 649 /// @brief 获得要操作的寄存器相对于mmio_offset的偏移量 650 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 651 /// @param register_offset 寄存器在设备中的offset 652 /// @return u32 要操作的寄存器相对于mmio_offset的偏移量 653 fn cam_offset(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 654 assert!(bus_device_function.valid()); 655 let bdf = ((bus_device_function.bus - self.bus_begin) as u32) << 8 656 | (bus_device_function.device as u32) << 3 657 | bus_device_function.function as u32; 658 let address = bdf << 12 | register_offset as u32; 659 // Ensure that address is word-aligned. 660 assert!(address & 0x3 == 0); 661 address 662 } 663 /// @brief 通过bus_device_function和offset读取相应位置寄存器的值（32位） 664 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 665 /// @param register_offset 寄存器在设备中的offset 666 /// @return u32 寄存器读值结果 667 pub fn read_config(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 668 let address = self.cam_offset(bus_device_function, register_offset); 669 unsafe { 670 // Right shift to convert from byte offset to word offset. 671 ((self.mmio_guard.as_ref().unwrap().vaddr().data() as *mut u32) 672 .add((address >> 2) as usize)) 673 .read_volatile() 674 } 675 } 676 677 /// @brief 通过bus_device_function和offset写入相应位置寄存器值（32位） 678 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 679 /// @param register_offset 寄存器在设备中的offset 680 /// @param data 要写入的值 681 pub fn write_config( 682 &mut self, 683 bus_device_function: BusDeviceFunction, 684 register_offset: u16, 685 data: u32, 686 ) { 687 let address = self.cam_offset(bus_device_function, register_offset); 688 // Safe because both the `mmio_base` and the address offset are properly aligned, and the 689 // resulting pointer is within the MMIO range of the CAM. 690 unsafe { 691 // Right shift to convert from byte offset to word offset. 692 ((self.mmio_guard.as_ref().unwrap().vaddr().data() as *mut u32) 693 .add((address >> 2) as usize)) 694 .write_volatile(data) 695 } 696 } 697 /// @brief 返回迭代器，遍历pcie设备的external_capabilities 698 pub fn external_capabilities( 699 &self, 700 bus_device_function: BusDeviceFunction, 701 ) -> ExternalCapabilityIterator { 702 ExternalCapabilityIterator { 703 root: self, 704 bus_device_function, 705 next_capability_offset: Some(0x100), 706 } 707 } 708 } 709 /// Gets the capabilities 'pointer' for the device function, if any. 710 /// @brief 获取第一个capability 的offset 711 /// @param bus_device_function PCI设备的唯一标识 712 /// @return Option<u8> offset 713 pub fn capabilities_offset(bus_device_function: BusDeviceFunction) -> Option<u8> { 714 let result = PciArch::read_config(&bus_device_function, STATUS_COMMAND_OFFSET); 715 let status: Status = Status::from_bits_truncate((result >> 16) as u16); 716 if status.contains(Status::CAPABILITIES_LIST) { 717 let cap_pointer = PciArch::read_config(&bus_device_function, 0x34) as u8 & 0xFC; 718 Some(cap_pointer) 719 } else { 720 None 721 } 722 } 723 724 /// @brief 读取pci设备头部 725 /// @param bus_device_function PCI设备的唯一标识 726 /// @param add_to_list 是否添加到链表 727 /// @return 返回的header(trait 类型) 728 fn pci_read_header( 729 bus_device_function: BusDeviceFunction, 730 add_to_list: bool, 731 ) -> Result<Box<dyn PciDeviceStructure>, PciError> { 732 // 先读取公共header 733 let result = PciArch::read_config(&bus_device_function, 0x00); 734 let vendor_id = result as u16; 735 let device_id = (result >> 16) as u16; 736 737 let result = PciArch::read_config(&bus_device_function, 0x04); 738 let command = result as u16; 739 let status = (result >> 16) as u16; 740 741 let result = PciArch::read_config(&bus_device_function, 0x08); 742 let revision_id = result as u8; 743 let prog_if = (result >> 8) as u8; 744 let subclass = (result >> 16) as u8; 745 let class_code = (result >> 24) as u8; 746 747 let result = PciArch::read_config(&bus_device_function, 0x0c); 748 let cache_line_size = result as u8; 749 let latency_timer = (result >> 8) as u8; 750 let header_type = (result >> 16) as u8; 751 let bist = (result >> 24) as u8; 752 if vendor_id == 0xffff { 753 return Err(PciError::GetWrongHeader); 754 } 755 let header = PciDeviceStructureHeader { 756 bus_device_function, 757 vendor_id, 758 device_id, 759 command, 760 status, 761 revision_id, 762 prog_if, 763 subclass, 764 class_code, 765 cache_line_size, 766 latency_timer, 767 header_type, 768 bist, 769 }; 770 match HeaderType::from(header_type & 0x7f) { 771 HeaderType::Standard => { 772 let general_device = pci_read_general_device_header(header, &bus_device_function); 773 let box_general_device = Box::new(general_device); 774 let box_general_device_clone = box_general_device.clone(); 775 if add_to_list { 776 PCI_DEVICE_LINKEDLIST.add(box_general_device); 777 } 778 Ok(box_general_device_clone) 779 } 780 HeaderType::PciPciBridge => { 781 let pci_to_pci_bridge = pci_read_pci_to_pci_bridge_header(header, &bus_device_function); 782 let box_pci_to_pci_bridge = Box::new(pci_to_pci_bridge); 783 let box_pci_to_pci_bridge_clone = box_pci_to_pci_bridge.clone(); 784 if add_to_list { 785 PCI_DEVICE_LINKEDLIST.add(box_pci_to_pci_bridge); 786 } 787 Ok(box_pci_to_pci_bridge_clone) 788 } 789 HeaderType::PciCardbusBridge => { 790 let pci_cardbus_bridge = 791 pci_read_pci_to_cardbus_bridge_header(header, &bus_device_function); 792 let box_pci_cardbus_bridge = Box::new(pci_cardbus_bridge); 793 let box_pci_cardbus_bridge_clone = box_pci_cardbus_bridge.clone(); 794 if add_to_list { 795 PCI_DEVICE_LINKEDLIST.add(box_pci_cardbus_bridge); 796 } 797 Ok(box_pci_cardbus_bridge_clone) 798 } 799 HeaderType::Unrecognised(_) => Err(PciError::UnrecognisedHeaderType), 800 } 801 } 802 803 /// @brief 读取type为0x0的pci设备的header 804 /// 本函数只应被 pci_read_header()调用 805 /// @param common_header 共有头部 806 /// @param bus_device_function PCI设备的唯一标识 807 /// @return Pci_Device_Structure_General_Device 标准设备头部 808 fn pci_read_general_device_header( 809 common_header: PciDeviceStructureHeader, 810 bus_device_function: &BusDeviceFunction, 811 ) -> PciDeviceStructureGeneralDevice { 812 let standard_device_bar = PciStandardDeviceBar::default(); 813 let cardbus_cis_pointer = PciArch::read_config(bus_device_function, 0x28); 814 815 let result = PciArch::read_config(bus_device_function, 0x2c); 816 let subsystem_vendor_id = result as u16; 817 let subsystem_id = (result >> 16) as u16; 818 819 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x30); 820 821 let result = PciArch::read_config(bus_device_function, 0x34); 822 let capabilities_pointer = result as u8; 823 let reserved0 = (result >> 8) as u8; 824 let reserved1 = (result >> 16) as u16; 825 826 let reserved2 = PciArch::read_config(bus_device_function, 0x38); 827 828 let result = PciArch::read_config(bus_device_function, 0x3c); 829 let interrupt_line = result as u8; 830 let interrupt_pin = (result >> 8) as u8; 831 let min_grant = (result >> 16) as u8; 832 let max_latency = (result >> 24) as u8; 833 PciDeviceStructureGeneralDevice { 834 common_header, 835 irq_type: IrqType::Unused, 836 irq_vector: Vec::new(), 837 standard_device_bar, 838 cardbus_cis_pointer, 839 subsystem_vendor_id, 840 subsystem_id, 841 expansion_rom_base_address, 842 capabilities_pointer, 843 reserved0, 844 reserved1, 845 reserved2, 846 interrupt_line, 847 interrupt_pin, 848 min_grant, 849 max_latency, 850 } 851 } 852 853 /// @brief 读取type为0x1的pci设备的header 854 /// 本函数只应被 pci_read_header()调用 855 /// @param common_header 共有头部 856 /// @param bus_device_function PCI设备的唯一标识 857 /// @return Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci 桥设备头部 858 fn pci_read_pci_to_pci_bridge_header( 859 common_header: PciDeviceStructureHeader, 860 bus_device_function: &BusDeviceFunction, 861 ) -> PciDeviceStructurePciToPciBridge { 862 let bar0 = PciArch::read_config(bus_device_function, 0x10); 863 let bar1 = PciArch::read_config(bus_device_function, 0x14); 864 865 let result = PciArch::read_config(bus_device_function, 0x18); 866 867 let primary_bus_number = result as u8; 868 let secondary_bus_number = (result >> 8) as u8; 869 let subordinate_bus_number = (result >> 16) as u8; 870 let secondary_latency_timer = (result >> 24) as u8; 871 872 let result = PciArch::read_config(bus_device_function, 0x1c); 873 let io_base = result as u8; 874 let io_limit = (result >> 8) as u8; 875 let secondary_status = (result >> 16) as u16; 876 877 let result = PciArch::read_config(bus_device_function, 0x20); 878 let memory_base = result as u16; 879 let memory_limit = (result >> 16) as u16; 880 881 let result = PciArch::read_config(bus_device_function, 0x24); 882 let prefetchable_memory_base = result as u16; 883 let prefetchable_memory_limit = (result >> 16) as u16; 884 885 let prefetchable_base_upper_32_bits = PciArch::read_config(bus_device_function, 0x28); 886 let prefetchable_limit_upper_32_bits = PciArch::read_config(bus_device_function, 0x2c); 887 888 let result = PciArch::read_config(bus_device_function, 0x30); 889 let io_base_upper_16_bits = result as u16; 890 let io_limit_upper_16_bits = (result >> 16) as u16; 891 892 let result = PciArch::read_config(bus_device_function, 0x34); 893 let capability_pointer = result as u8; 894 let reserved0 = (result >> 8) as u8; 895 let reserved1 = (result >> 16) as u16; 896 897 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x38); 898 899 let result = PciArch::read_config(bus_device_function, 0x3c); 900 let interrupt_line = result as u8; 901 let interrupt_pin = (result >> 8) as u8; 902 let bridge_control = (result >> 16) as u16; 903 PciDeviceStructurePciToPciBridge { 904 common_header, 905 irq_type: IrqType::Unused, 906 irq_vector: Vec::new(), 907 bar0, 908 bar1, 909 primary_bus_number, 910 secondary_bus_number, 911 subordinate_bus_number, 912 secondary_latency_timer, 913 io_base, 914 io_limit, 915 secondary_status, 916 memory_base, 917 memory_limit, 918 prefetchable_memory_base, 919 prefetchable_memory_limit, 920 prefetchable_base_upper_32_bits, 921 prefetchable_limit_upper_32_bits, 922 io_base_upper_16_bits, 923 io_limit_upper_16_bits, 924 capability_pointer, 925 reserved0, 926 reserved1, 927 expansion_rom_base_address, 928 interrupt_line, 929 interrupt_pin, 930 bridge_control, 931 } 932 } 933 934 /// @brief 读取type为0x2的pci设备的header 935 /// 本函数只应被 pci_read_header()调用 936 /// @param common_header 共有头部 937 /// @param bus_device_function PCI设备的唯一标识 938 /// @return Pci_Device_Structure_Pci_to_Cardbus_Bridge pci-to-cardbus 桥设备头部 939 fn pci_read_pci_to_cardbus_bridge_header( 940 common_header: PciDeviceStructureHeader, 941 busdevicefunction: &BusDeviceFunction, 942 ) -> PciDeviceStructurePciToCardbusBridge { 943 let cardbus_socket_ex_ca_base_address = PciArch::read_config(busdevicefunction, 0x10); 944 945 let result = PciArch::read_config(busdevicefunction, 0x14); 946 let offset_of_capabilities_list = result as u8; 947 let reserved = (result >> 8) as u8; 948 let secondary_status = (result >> 16) as u16; 949 950 let result = PciArch::read_config(busdevicefunction, 0x18); 951 let pci_bus_number = result as u8; 952 let card_bus_bus_number = (result >> 8) as u8; 953 let subordinate_bus_number = (result >> 16) as u8; 954 let card_bus_latency_timer = (result >> 24) as u8; 955 956 let memory_base_address0 = PciArch::read_config(busdevicefunction, 0x1c); 957 let memory_limit0 = PciArch::read_config(busdevicefunction, 0x20); 958 let memory_base_address1 = PciArch::read_config(busdevicefunction, 0x24); 959 let memory_limit1 = PciArch::read_config(busdevicefunction, 0x28); 960 961 let io_base_address0 = PciArch::read_config(busdevicefunction, 0x2c); 962 let io_limit0 = PciArch::read_config(busdevicefunction, 0x30); 963 let io_base_address1 = PciArch::read_config(busdevicefunction, 0x34); 964 let io_limit1 = PciArch::read_config(busdevicefunction, 0x38); 965 let result = PciArch::read_config(busdevicefunction, 0x3c); 966 let interrupt_line = result as u8; 967 let interrupt_pin = (result >> 8) as u8; 968 let bridge_control = (result >> 16) as u16; 969 970 let result = PciArch::read_config(busdevicefunction, 0x40); 971 let subsystem_device_id = result as u16; 972 let subsystem_vendor_id = (result >> 16) as u16; 973 974 let pc_card_legacy_mode_base_address_16_bit = PciArch::read_config(busdevicefunction, 0x44); 975 PciDeviceStructurePciToCardbusBridge { 976 common_header, 977 cardbus_socket_ex_ca_base_address, 978 offset_of_capabilities_list, 979 reserved, 980 secondary_status, 981 pci_bus_number, 982 card_bus_bus_number, 983 subordinate_bus_number, 984 card_bus_latency_timer, 985 memory_base_address0, 986 memory_limit0, 987 memory_base_address1, 988 memory_limit1, 989 io_base_address0, 990 io_limit0, 991 io_base_address1, 992 io_limit1, 993 interrupt_line, 994 interrupt_pin, 995 bridge_control, 996 subsystem_device_id, 997 subsystem_vendor_id, 998 pc_card_legacy_mode_base_address_16_bit, 999 } 1000 } 1001 1002 /// @brief 检查所有bus上的设备并将其加入链表 1003 /// @return 成功返回ok(),失败返回失败原因 1004 fn pci_check_all_buses() -> Result<u8, PciError> { 1005 kinfo!("Checking all devices in PCI bus..."); 1006 let busdevicefunction = BusDeviceFunction { 1007 bus: 0, 1008 device: 0, 1009 function: 0, 1010 }; 1011 let header = pci_read_header(busdevicefunction, false)?; 1012 let common_header = header.common_header(); 1013 pci_check_bus(0)?; 1014 if common_header.header_type & 0x80 != 0 { 1015 for function in 1..8 { 1016 pci_check_bus(function)?; 1017 } 1018 } 1019 Ok(0) 1020 } 1021 /// @brief 检查特定设备并将其加入链表 1022 /// @return 成功返回ok(),失败返回失败原因 1023 fn pci_check_function(busdevicefunction: BusDeviceFunction) -> Result<u8, PciError> { 1024 //kdebug!("PCI check function {}", busdevicefunction.function); 1025 let header = match pci_read_header(busdevicefunction, true) { 1026 Ok(header) => header, 1027 Err(PciError::GetWrongHeader) => { 1028 return Ok(255); 1029 } 1030 Err(e) => { 1031 return Err(e); 1032 } 1033 }; 1034 let common_header = header.common_header(); 1035 if (common_header.class_code == 0x06) 1036 && (common_header.subclass == 0x04 || common_header.subclass == 0x09) 1037 { 1038 let pci_to_pci_bridge = header 1039 .as_pci_to_pci_bridge_device() 1040 .ok_or(PciError::PciDeviceStructureTransformError)?; 1041 let secondary_bus = pci_to_pci_bridge.secondary_bus_number; 1042 pci_check_bus(secondary_bus)?; 1043 } 1044 Ok(0) 1045 } 1046 1047 /// @brief 检查device上的设备并将其加入链表 1048 /// @return 成功返回ok(),失败返回失败原因 1049 fn pci_check_device(bus: u8, device: u8) -> Result<u8, PciError> { 1050 //kdebug!("PCI check device {}", device); 1051 let busdevicefunction = BusDeviceFunction { 1052 bus, 1053 device, 1054 function: 0, 1055 }; 1056 let header = match pci_read_header(busdevicefunction, false) { 1057 Ok(header) => header, 1058 Err(PciError::GetWrongHeader) => { 1059 //设备不存在，直接返回即可，不用终止遍历 1060 return Ok(255); 1061 } 1062 Err(e) => { 1063 return Err(e); 1064 } 1065 }; 1066 pci_check_function(busdevicefunction)?; 1067 let common_header = header.common_header(); 1068 if common_header.header_type & 0x80 != 0 { 1069 kdebug!( 1070 "Detected multi func device in bus{},device{}", 1071 busdevicefunction.bus, 1072 busdevicefunction.device 1073 ); 1074 // 这是一个多function的设备，因此查询剩余的function 1075 for function in 1..8 { 1076 let busdevicefunction = BusDeviceFunction { 1077 bus, 1078 device, 1079 function, 1080 }; 1081 pci_check_function(busdevicefunction)?; 1082 } 1083 } 1084 Ok(0) 1085 } 1086 /// @brief 检查该bus上的设备并将其加入链表 1087 /// @return 成功返回ok(),失败返回失败原因 1088 fn pci_check_bus(bus: u8) -> Result<u8, PciError> { 1089 //kdebug!("PCI check bus {}", bus); 1090 for device in 0..32 { 1091 pci_check_device(bus, device)?; 1092 } 1093 Ok(0) 1094 } 1095 1096 /// pci初始化函数 1097 #[inline(never)] 1098 pub fn pci_init() { 1099 kinfo!("Initializing PCI bus..."); 1100 if let Err(e) = pci_check_all_buses() { 1101 kerror!("pci init failed when checking bus because of error: {}", e); 1102 return; 1103 } 1104 kinfo!( 1105 "Total pci device and function num = {}", 1106 PCI_DEVICE_LINKEDLIST.num() 1107 ); 1108 let list = PCI_DEVICE_LINKEDLIST.read(); 1109 for box_pci_device in list.iter() { 1110 let common_header = box_pci_device.common_header(); 1111 match box_pci_device.header_type() { 1112 HeaderType::Standard if common_header.status & 0x10 != 0 => { 1113 kinfo!("Found pci standard device with class code ={} subclass={} status={:#x} cap_pointer={:#x} vendor={:#x}, device id={:#x},bdf={}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer,common_header.vendor_id, common_header.device_id,common_header.bus_device_function); 1114 } 1115 HeaderType::Standard => { 1116 kinfo!( 1117 "Found pci standard device with class code ={} subclass={} status={:#x} ", 1118 common_header.class_code, 1119 common_header.subclass, 1120 common_header.status 1121 ); 1122 } 1123 HeaderType::PciPciBridge if common_header.status & 0x10 != 0 => { 1124 kinfo!("Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} cap_pointer={:#x}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer); 1125 } 1126 HeaderType::PciPciBridge => { 1127 kinfo!( 1128 "Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} ", 1129 common_header.class_code, 1130 common_header.subclass, 1131 common_header.status 1132 ); 1133 } 1134 HeaderType::PciCardbusBridge => { 1135 kinfo!( 1136 "Found pcicardbus bridge device with class code ={} subclass={} status={:#x} ", 1137 common_header.class_code, 1138 common_header.subclass, 1139 common_header.status 1140 ); 1141 } 1142 HeaderType::Unrecognised(_) => {} 1143 } 1144 } 1145 kinfo!("PCI bus initialized."); 1146 } 1147 1148 /// An identifier for a PCI bus, device and function. 1149 /// PCI设备的唯一标识 1150 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1151 pub struct BusDeviceFunction { 1152 /// The PCI bus number, between 0 and 255. 1153 pub bus: u8, 1154 /// The device number on the bus, between 0 and 31. 1155 pub device: u8, 1156 /// The function number of the device, between 0 and 7. 1157 pub function: u8, 1158 } 1159 impl BusDeviceFunction { 1160 /// Returns whether the device and function numbers are valid, i.e. the device is between 0 and 1161 ///@brief 检测BusDeviceFunction实例是否有效 1162 ///@param self 1163 ///@return bool 是否有效 1164 #[allow(dead_code)] 1165 pub fn valid(&self) -> bool { 1166 self.device < 32 && self.function < 8 1167 } 1168 } 1169 ///实现BusDeviceFunction的Display trait，使其可以直接输出 1170 impl Display for BusDeviceFunction { 1171 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 1172 write!( 1173 f, 1174 "bus {} device {} function{}", 1175 self.bus, self.device, self.function 1176 ) 1177 } 1178 } 1179 /// The location allowed for a memory BAR. 1180 /// memory BAR的三种情况 1181 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1182 pub enum MemoryBarType { 1183 /// The BAR has a 32-bit address and can be mapped anywhere in 32-bit address space. 1184 Width32, 1185 /// The BAR must be mapped below 1MiB. 1186 Below1MiB, 1187 /// The BAR has a 64-bit address and can be mapped anywhere in 64-bit address space. 1188 Width64, 1189 } 1190 ///实现MemoryBarType与u8的类型转换 1191 impl From<MemoryBarType> for u8 { 1192 fn from(bar_type: MemoryBarType) -> Self { 1193 match bar_type { 1194 MemoryBarType::Width32 => 0, 1195 MemoryBarType::Below1MiB => 1, 1196 MemoryBarType::Width64 => 2, 1197 } 1198 } 1199 } 1200 ///实现MemoryBarType与u8的类型转换 1201 impl TryFrom<u8> for MemoryBarType { 1202 type Error = PciError; 1203 fn try_from(value: u8) -> Result<Self, Self::Error> { 1204 match value { 1205 0 => Ok(Self::Width32), 1206 1 => Ok(Self::Below1MiB), 1207 2 => Ok(Self::Width64), 1208 _ => Err(PciError::InvalidBarType), 1209 } 1210 } 1211 } 1212 1213 /// Information about a PCI Base Address Register. 1214 /// BAR的三种类型 Memory/IO/Unused 1215 #[derive(Clone, Debug)] 1216 pub enum BarInfo { 1217 /// The BAR is for a memory region. 1218 Memory { 1219 /// The size of the BAR address and where it can be located. 1220 address_type: MemoryBarType, 1221 /// If true, then reading from the region doesn't have side effects. The CPU may cache reads 1222 /// and merge repeated stores. 1223 prefetchable: bool, 1224 /// The memory address, always 16-byte aligned. 1225 address: u64, 1226 /// The size of the BAR in bytes. 1227 size: u32, 1228 /// The virtaddress for a memory bar(mapped). 1229 mmio_guard: Arc<MMIOSpaceGuard>, 1230 }, 1231 /// The BAR is for an I/O region. 1232 IO { 1233 /// The I/O address, always 4-byte aligned. 1234 address: u32, 1235 /// The size of the BAR in bytes. 1236 size: u32, 1237 }, 1238 Unused, 1239 } 1240 1241 impl BarInfo { 1242 /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO 1243 /// BAR. 1244 ///@brief 得到某个bar的memory_address与size(前提是他的类型为Memory Bar) 1245 ///@param self 1246 ///@return Option<(u64, u32) 是Memory Bar返回内存地址与大小，不是则返回None 1247 pub fn memory_address_size(&self) -> Option<(u64, u32)> { 1248 if let Self::Memory { address, size, .. } = self { 1249 Some((*address, *size)) 1250 } else { 1251 None 1252 } 1253 } 1254 ///@brief 得到某个bar的virtaddress(前提是他的类型为Memory Bar) 1255 ///@param self 1256 ///@return Option<(u64) 是Memory Bar返回映射的虚拟地址，不是则返回None 1257 pub fn virtual_address(&self) -> Option<VirtAddr> { 1258 if let Self::Memory { mmio_guard, .. } = self { 1259 Some(mmio_guard.vaddr()) 1260 } else { 1261 None 1262 } 1263 } 1264 } 1265 ///实现BarInfo的Display trait，自定义输出 1266 impl Display for BarInfo { 1267 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1268 match self { 1269 Self::Memory { 1270 address_type, 1271 prefetchable, 1272 address, 1273 size, 1274 mmio_guard, 1275 } => write!( 1276 f, 1277 "Memory space at {:#010x}, size {}, type {:?}, prefetchable {}, mmio_guard: {:?}", 1278 address, size, address_type, prefetchable, mmio_guard 1279 ), 1280 Self::IO { address, size } => { 1281 write!(f, "I/O space at {:#010x}, size {}", address, size) 1282 } 1283 Self::Unused => { 1284 write!(f, "Unused bar") 1285 } 1286 } 1287 } 1288 } 1289 // todo 增加对桥的bar的支持 1290 pub trait PciDeviceBar {} 1291 1292 ///一个普通PCI设备（非桥）有6个BAR寄存器，PciStandardDeviceBar存储其全部信息 1293 #[derive(Clone, Debug)] 1294 pub struct PciStandardDeviceBar { 1295 bar0: BarInfo, 1296 bar1: BarInfo, 1297 bar2: BarInfo, 1298 bar3: BarInfo, 1299 bar4: BarInfo, 1300 bar5: BarInfo, 1301 } 1302 1303 impl PciStandardDeviceBar { 1304 ///@brief 得到某个bar的barinfo 1305 ///@param self ，bar_index(0-5) 1306 ///@return Result<&BarInfo, PciError> bar_index在0-5则返回对应的bar_info结构体，超出范围则返回错误 1307 pub fn get_bar(&self, bar_index: u8) -> Result<&BarInfo, PciError> { 1308 match bar_index { 1309 0 => Ok(&self.bar0), 1310 1 => Ok(&self.bar1), 1311 2 => Ok(&self.bar2), 1312 3 => Ok(&self.bar3), 1313 4 => Ok(&self.bar4), 1314 5 => Ok(&self.bar5), 1315 _ => Err(PciError::InvalidBarType), 1316 } 1317 } 1318 } 1319 ///实现PciStandardDeviceBar的Display trait，使其可以直接输出 1320 impl Display for PciStandardDeviceBar { 1321 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1322 write!( 1323 f, 1324 "\r\nBar0:{}\r\nBar1:{}\r\nBar2:{}\r\nBar3:{}\r\nBar4:{}\r\nBar5:{}", 1325 self.bar0, self.bar1, self.bar2, self.bar3, self.bar4, self.bar5 1326 ) 1327 } 1328 } 1329 ///实现PciStandardDeviceBar的Default trait，使其可以简单初始化 1330 impl Default for PciStandardDeviceBar { 1331 fn default() -> Self { 1332 PciStandardDeviceBar { 1333 bar0: BarInfo::Unused, 1334 bar1: BarInfo::Unused, 1335 bar2: BarInfo::Unused, 1336 bar3: BarInfo::Unused, 1337 bar4: BarInfo::Unused, 1338 bar5: BarInfo::Unused, 1339 } 1340 } 1341 } 1342 1343 ///@brief 将某个pci设备的bar寄存器读取值后映射到虚拟地址 1344 ///@param self ，bus_device_function PCI设备的唯一标识符 1345 ///@return Result<PciStandardDeviceBar, PciError> 成功则返回对应的PciStandardDeviceBar结构体，失败则返回错误类型 1346 pub fn pci_bar_init( 1347 bus_device_function: BusDeviceFunction, 1348 ) -> Result<PciStandardDeviceBar, PciError> { 1349 let mut device_bar: PciStandardDeviceBar = PciStandardDeviceBar::default(); 1350 let mut bar_index_ignore: u8 = 255; 1351 for bar_index in 0..6 { 1352 if bar_index == bar_index_ignore { 1353 continue; 1354 } 1355 let bar_info; 1356 let bar_orig = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1357 PciArch::write_config( 1358 &bus_device_function, 1359 BAR0_OFFSET + 4 * bar_index, 1360 0xffffffff, 1361 ); 1362 let size_mask = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 1363 // A wrapping add is necessary to correctly handle the case of unused BARs, which read back 1364 // as 0, and should be treated as size 0. 1365 let size = (!(size_mask & 0xfffffff0)).wrapping_add(1); 1366 //kdebug!("bar_orig:{:#x},size: {:#x}", bar_orig,size); 1367 // Restore the original value. 1368 PciArch::write_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index, bar_orig); 1369 if size == 0 { 1370 continue; 1371 } 1372 if bar_orig & 0x00000001 == 0x00000001 { 1373 // I/O space 1374 let address = bar_orig & 0xfffffffc; 1375 bar_info = BarInfo::IO { address, size }; 1376 } else { 1377 // Memory space 1378 let mut address = u64::from(bar_orig & 0xfffffff0); 1379 let prefetchable = bar_orig & 0x00000008 != 0; 1380 let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?; 1381 if address_type == MemoryBarType::Width64 { 1382 if bar_index >= 5 { 1383 return Err(PciError::InvalidBarType); 1384 } 1385 let address_top = 1386 PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * (bar_index + 1)); 1387 address |= u64::from(address_top) << 32; 1388 bar_index_ignore = bar_index + 1; //下个bar跳过，因为64位的memory bar覆盖了两个bar 1389 } 1390 let pci_address = PciAddr::new(address as usize); 1391 let paddr = PciArch::address_pci_to_physical(pci_address); //PCI总线域物理地址转换为存储器域物理地址 1392 1393 let space_guard: Arc<MMIOSpaceGuard>; 1394 unsafe { 1395 let size_want = size as usize; 1396 let tmp = mmio_pool() 1397 .create_mmio(size_want) 1398 .map_err(|_| PciError::CreateMmioError)?; 1399 space_guard = Arc::new(tmp); 1400 //kdebug!("Pci bar init: mmio space: {space_guard:?}, paddr={paddr:?}, size_want={size_want}"); 1401 assert!( 1402 space_guard.map_phys(paddr, size_want).is_ok(), 1403 "pci_bar_init: map_phys failed" 1404 ); 1405 } 1406 bar_info = BarInfo::Memory { 1407 address_type, 1408 prefetchable, 1409 address, 1410 size, 1411 mmio_guard: space_guard, 1412 }; 1413 } 1414 match bar_index { 1415 0 => { 1416 device_bar.bar0 = bar_info; 1417 } 1418 1 => { 1419 device_bar.bar1 = bar_info; 1420 } 1421 2 => { 1422 device_bar.bar2 = bar_info; 1423 } 1424 3 => { 1425 device_bar.bar3 = bar_info; 1426 } 1427 4 => { 1428 device_bar.bar4 = bar_info; 1429 } 1430 5 => { 1431 device_bar.bar5 = bar_info; 1432 } 1433 _ => {} 1434 } 1435 } 1436 //kdebug!("pci_device_bar:{}", device_bar); 1437 return Ok(device_bar); 1438 } 1439 1440 /// Information about a PCI device capability. 1441 /// PCI设备的capability的信息 1442 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1443 pub struct CapabilityInfo { 1444 /// The offset of the capability in the PCI configuration space of the device function. 1445 pub offset: u8, 1446 /// The ID of the capability. 1447 pub id: u8, 1448 /// The third and fourth bytes of the capability, to save reading them again. 1449 pub private_header: u16, 1450 } 1451 1452 /// Iterator over capabilities for a device. 1453 /// 创建迭代器以遍历PCI设备的capability 1454 #[derive(Debug)] 1455 pub struct CapabilityIterator { 1456 pub bus_device_function: BusDeviceFunction, 1457 pub next_capability_offset: Option<u8>, 1458 } 1459 1460 impl Iterator for CapabilityIterator { 1461 type Item = CapabilityInfo; 1462 fn next(&mut self) -> Option<Self::Item> { 1463 let offset = self.next_capability_offset?; 1464 1465 // Read the first 4 bytes of the capability. 1466 let capability_header = PciArch::read_config(&self.bus_device_function, offset); 1467 let id = capability_header as u8; 1468 let next_offset = (capability_header >> 8) as u8; 1469 let private_header = (capability_header >> 16) as u16; 1470 1471 self.next_capability_offset = if next_offset == 0 { 1472 None 1473 } else if next_offset < 64 || next_offset & 0x3 != 0 { 1474 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1475 None 1476 } else { 1477 Some(next_offset) 1478 }; 1479 1480 Some(CapabilityInfo { 1481 offset, 1482 id, 1483 private_header, 1484 }) 1485 } 1486 } 1487 1488 /// Information about a PCIe device capability. 1489 /// PCIe设备的external capability的信息 1490 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1491 pub struct ExternalCapabilityInfo { 1492 /// The offset of the capability in the PCI configuration space of the device function. 1493 pub offset: u16, 1494 /// The ID of the capability. 1495 pub id: u16, 1496 /// The third and fourth bytes of the capability, to save reading them again. 1497 pub capability_version: u8, 1498 } 1499 1500 /// Iterator over capabilities for a device. 1501 /// 创建迭代器以遍历PCIe设备的external capability 1502 #[derive(Debug)] 1503 pub struct ExternalCapabilityIterator<'a> { 1504 pub root: &'a PciRoot, 1505 pub bus_device_function: BusDeviceFunction, 1506 pub next_capability_offset: Option<u16>, 1507 } 1508 impl<'a> Iterator for ExternalCapabilityIterator<'a> { 1509 type Item = ExternalCapabilityInfo; 1510 fn next(&mut self) -> Option<Self::Item> { 1511 let offset = self.next_capability_offset?; 1512 1513 // Read the first 4 bytes of the capability. 1514 let capability_header = self.root.read_config(self.bus_device_function, offset); 1515 let id = capability_header as u16; 1516 let next_offset = (capability_header >> 20) as u16; 1517 let capability_version = ((capability_header >> 16) & 0xf) as u8; 1518 1519 self.next_capability_offset = if next_offset == 0 { 1520 None 1521 } else if next_offset < 0x100 || next_offset & 0x3 != 0 { 1522 kwarn!("Invalid next capability offset {:#04x}", next_offset); 1523 None 1524 } else { 1525 Some(next_offset) 1526 }; 1527 1528 Some(ExternalCapabilityInfo { 1529 offset, 1530 id, 1531 capability_version, 1532 }) 1533 } 1534 } 1535