1 #![allow(dead_code)] 2 // 目前仅支持单主桥单Segment 3 4 use super::device::pci_device_manager; 5 use super::pci_irq::{IrqType, PciIrqError}; 6 use super::raw_device::PciGeneralDevice; 7 use super::root::{pci_root_0, PciRoot}; 8 9 use crate::arch::{PciArch, TraitPciArch}; 10 use crate::driver::pci::subsys::pci_bus_subsys_init; 11 use crate::exception::IrqNumber; 12 use crate::libs::rwlock::{RwLock, RwLockReadGuard, RwLockWriteGuard}; 13 14 use crate::mm::mmio_buddy::{mmio_pool, MMIOSpaceGuard}; 15 16 use crate::mm::VirtAddr; 17 18 use alloc::string::String; 19 use alloc::sync::Arc; 20 use alloc::vec::Vec; 21 use alloc::{boxed::Box, collections::LinkedList}; 22 use bitflags::bitflags; 23 use log::{debug, error, info, warn}; 24 25 use core::{ 26 convert::TryFrom, 27 fmt::{self, Debug, Display, Formatter}, 28 }; 29 // PCI_DEVICE_LINKEDLIST 添加了读写锁的全局链表，里面存储了检索到的PCI设备结构体 30 lazy_static! { 31 pub static ref PCI_DEVICE_LINKEDLIST: PciDeviceLinkedList = PciDeviceLinkedList::new(); 32 } 33 34 /// PCI域地址 35 #[derive(Clone, Copy, Eq, Ord, PartialEq, PartialOrd)] 36 #[repr(transparent)] 37 pub struct PciAddr(usize); 38 39 impl PciAddr { 40 #[inline(always)] 41 pub const fn new(address: usize) -> Self { 42 Self(address) 43 } 44 45 /// @brief 获取PCI域地址的值 46 #[inline(always)] 47 pub fn data(&self) -> usize { 48 self.0 49 } 50 51 /// @brief 将PCI域地址加上一个偏移量 52 #[inline(always)] 53 pub fn add(self, offset: usize) -> Self { 54 Self(self.0 + offset) 55 } 56 57 /// @brief 判断PCI域地址是否按照指定要求对齐 58 #[inline(always)] 59 pub fn check_aligned(&self, align: usize) -> bool { 60 return self.0 & (align - 1) == 0; 61 } 62 } 63 impl Debug for PciAddr { 64 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result { 65 write!(f, "PciAddr({:#x})", self.0) 66 } 67 } 68 69 /// 添加了读写锁的链表，存储PCI设备结构体 70 pub struct PciDeviceLinkedList { 71 list: RwLock<LinkedList<Box<dyn PciDeviceStructure>>>, 72 } 73 74 impl PciDeviceLinkedList { 75 /// @brief 初始化结构体 76 fn new() -> Self { 77 PciDeviceLinkedList { 78 list: RwLock::new(LinkedList::new()), 79 } 80 } 81 /// @brief 获取可读的linkedlist(读锁守卫) 82 /// @return RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> 读锁守卫 83 pub fn read(&self) -> RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 84 self.list.read() 85 } 86 /// @brief 获取可写的linkedlist(写锁守卫) 87 /// @return RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> 写锁守卫 88 pub fn write(&self) -> RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 89 self.list.write() 90 } 91 /// @brief 获取链表中PCI结构体数目 92 /// @return usize 链表中PCI结构体数目 93 pub fn num(&self) -> usize { 94 let list = self.list.read(); 95 list.len() 96 } 97 /// @brief 添加Pci设备结构体到链表中 98 pub fn add(&self, device: Box<dyn PciDeviceStructure>) { 99 let mut list = self.list.write(); 100 list.push_back(device); 101 } 102 } 103 104 /// # 获取具有特定供应商ID的PCI设备结构的引用 105 /// 106 /// 这个函数通过供应商ID搜索PCI设备结构列表，并返回匹配该ID的所有设备结构的引用。 107 /// 108 /// ## 参数 109 /// 110 /// - list: 一个可变的PCI设备结构链表，类型为`&'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>`。 111 /// - vendor_id: 要查找的PCI供应商ID，类型为`u16`。 112 /// 113 /// ## 返回值 114 /// 115 /// - 返回匹配的供应商ID的PCI设备结构的引用。 116 pub fn get_pci_device_structures_mut_by_vendor_id<'a>( 117 list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 118 vendor_id: u16, 119 ) -> Vec<&'a mut Box<(dyn PciDeviceStructure)>> { 120 let mut result = Vec::new(); 121 for box_pci_device_structure in list.iter_mut() { 122 let common_header = (*box_pci_device_structure).common_header(); 123 if common_header.vendor_id == vendor_id { 124 result.push(box_pci_device_structure); 125 } 126 } 127 result 128 } 129 130 /// # get_pci_device_structure_mut - 在链表中寻找满足条件的PCI设备结构体并返回其可变引用 131 /// 132 /// 该函数遍历给定的PCI设备链表，寻找其common_header中class_code和subclass字段与给定值匹配的设备结构体。 133 /// 对于每一个匹配的设备结构体，函数返回一个可变引用。 134 /// 135 /// ## 参数 136 /// 137 /// - list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>> — 链表的写锁守卫，用于访问和遍历PCI设备链表。 138 /// - class_code: u8 — PCI设备class code寄存器值，用于分类设备的功能。 139 /// - subclass: u8 — PCI设备subclass寄存器值，与class_code一起确定设备的子类型。 140 /// 141 /// ## 返回值 142 /// - 包含链表中所有满足条件的PCI结构体的可变引用的容器。 143 pub fn get_pci_device_structure_mut<'a>( 144 list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 145 class_code: u8, 146 subclass: u8, 147 ) -> Vec<&'a mut Box<(dyn PciDeviceStructure)>> { 148 let mut result = Vec::new(); 149 for box_pci_device_structure in list.iter_mut() { 150 let common_header = (*box_pci_device_structure).common_header(); 151 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 152 result.push(box_pci_device_structure); 153 } 154 } 155 result 156 } 157 158 /// # get_pci_device_structure - 在链表中寻找满足条件的PCI设备结构体并返回其不可变引用 159 /// 160 /// 该函数遍历给定的PCI设备链表，寻找其common_header中class_code和subclass字段与给定值匹配的设备结构体。 161 /// 对于每一个匹配的设备结构体，函数返回一个可变引用。 162 /// 163 /// ## 参数 164 /// 165 /// - list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>> — 链表的写锁守卫，用于访问和遍历PCI设备链表。 166 /// - class_code: u8 — PCI设备class code寄存器值，用于分类设备的功能。 167 /// - subclass: u8 — PCI设备subclass寄存器值，与class_code一起确定设备的子类型。 168 /// 169 /// ## 返回值 170 /// - 包含链表中所有满足条件的PCI结构体的不可变引用的容器。 171 #[allow(clippy::borrowed_box)] 172 pub fn get_pci_device_structure<'a>( 173 list: &'a mut RwLockReadGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 174 class_code: u8, 175 subclass: u8, 176 ) -> Vec<&'a Box<(dyn PciDeviceStructure)>> { 177 let mut result = Vec::new(); 178 for box_pci_device_structure in list.iter() { 179 let common_header = (*box_pci_device_structure).common_header(); 180 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 181 result.push(box_pci_device_structure); 182 } 183 } 184 result 185 } 186 187 //Bar0寄存器的offset 188 const BAR0_OFFSET: u8 = 0x10; 189 //Status、Command寄存器的offset 190 const STATUS_COMMAND_OFFSET: u8 = 0x04; 191 /// ID for vendor-specific PCI capabilities.(Virtio Capabilities) 192 pub const PCI_CAP_ID_VNDR: u8 = 0x09; 193 pub const PCI_CAP_ID_MSI: u8 = 0x05; 194 pub const PCI_CAP_ID_MSIX: u8 = 0x11; 195 pub const PORT_PCI_CONFIG_ADDRESS: u16 = 0xcf8; 196 pub const PORT_PCI_CONFIG_DATA: u16 = 0xcfc; 197 // pci设备分组的id 198 pub type SegmentGroupNumber = u16; //理论上最多支持65535个Segment_Group 199 200 bitflags! { 201 /// The status register in PCI configuration space. 202 pub struct Status: u16 { 203 // Bits 0-2 are reserved. 204 /// The state of the device's INTx# signal. 205 const INTERRUPT_STATUS = 1 << 3; 206 /// The device has a linked list of capabilities. 207 const CAPABILITIES_LIST = 1 << 4; 208 /// The device is capabile of running at 66 MHz rather than 33 MHz. 209 const MHZ_66_CAPABLE = 1 << 5; 210 // Bit 6 is reserved. 211 /// The device can accept fast back-to-back transactions not from the same agent. 212 const FAST_BACK_TO_BACK_CAPABLE = 1 << 7; 213 /// The bus agent observed a parity error (if parity error handling is enabled). 214 const MASTER_DATA_PARITY_ERROR = 1 << 8; 215 // Bits 9-10 are DEVSEL timing. 216 /// A target device terminated a transaction with target-abort. 217 const SIGNALED_TARGET_ABORT = 1 << 11; 218 /// A master device transaction was terminated with target-abort. 219 const RECEIVED_TARGET_ABORT = 1 << 12; 220 /// A master device transaction was terminated with master-abort. 221 const RECEIVED_MASTER_ABORT = 1 << 13; 222 /// A device asserts SERR#. 223 const SIGNALED_SYSTEM_ERROR = 1 << 14; 224 /// The device detects a parity error, even if parity error handling is disabled. 225 const DETECTED_PARITY_ERROR = 1 << 15; 226 } 227 } 228 229 bitflags! { 230 /// The command register in PCI configuration space. 231 pub struct Command: u16 { 232 /// The device can respond to I/O Space accesses. 233 const IO_SPACE = 1 << 0; 234 /// The device can respond to Memory Space accesses. 235 const MEMORY_SPACE = 1 << 1; 236 /// The device can behave as a bus master. 237 const BUS_MASTER = 1 << 2; 238 /// The device can monitor Special Cycle operations. 239 const SPECIAL_CYCLES = 1 << 3; 240 /// The device can generate the Memory Write and Invalidate command. 241 const MEMORY_WRITE_AND_INVALIDATE_ENABLE = 1 << 4; 242 /// The device will snoop palette register data. 243 const VGA_PALETTE_SNOOP = 1 << 5; 244 /// The device should take its normal action when a parity error is detected. 245 const PARITY_ERROR_RESPONSE = 1 << 6; 246 // Bit 7 is reserved. 247 /// The SERR# driver is enabled. 248 const SERR_ENABLE = 1 << 8; 249 /// The device is allowed to generate fast back-to-back transactions. 250 const FAST_BACK_TO_BACK_ENABLE = 1 << 9; 251 /// Assertion of the device's INTx# signal is disabled. 252 const INTERRUPT_DISABLE = 1 << 10; 253 } 254 } 255 256 /// The type of a PCI device function header. 257 /// 标头类型/设备类型 258 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 259 pub enum HeaderType { 260 /// A normal PCI device. 261 Standard, 262 /// A PCI to PCI bridge. 263 PciPciBridge, 264 /// A PCI to CardBus bridge. 265 PciCardbusBridge, 266 /// Unrecognised header type. 267 Unrecognised(u8), 268 } 269 /// u8到HeaderType的转换 270 impl From<u8> for HeaderType { 271 fn from(value: u8) -> Self { 272 match value { 273 0x00 => Self::Standard, 274 0x01 => Self::PciPciBridge, 275 0x02 => Self::PciCardbusBridge, 276 _ => Self::Unrecognised(value), 277 } 278 } 279 } 280 /// Pci可能触发的各种错误 281 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 282 pub enum PciError { 283 /// The device reported an invalid BAR type. 284 InvalidBarType, 285 CreateMmioError, 286 InvalidBusDeviceFunction, 287 SegmentNotFound, 288 McfgTableNotFound, 289 GetWrongHeader, 290 UnrecognisedHeaderType, 291 PciDeviceStructureTransformError, 292 PciIrqError(PciIrqError), 293 } 294 ///实现PciError的Display trait，使其可以直接输出 295 impl Display for PciError { 296 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 297 match self { 298 Self::InvalidBarType => write!(f, "Invalid PCI BAR type."), 299 Self::CreateMmioError => write!(f, "Error occurred while creating mmio."), 300 Self::InvalidBusDeviceFunction => write!(f, "Found invalid BusDeviceFunction."), 301 Self::SegmentNotFound => write!(f, "Target segment not found"), 302 Self::McfgTableNotFound => write!(f, "ACPI MCFG Table not found"), 303 Self::GetWrongHeader => write!(f, "GetWrongHeader with vendor id 0xffff"), 304 Self::UnrecognisedHeaderType => write!(f, "Found device with unrecognised header type"), 305 Self::PciDeviceStructureTransformError => { 306 write!(f, "Found None When transform Pci device structure") 307 } 308 Self::PciIrqError(err) => write!(f, "Error occurred while setting irq :{:?}.", err), 309 } 310 } 311 } 312 313 /// trait类型Pci_Device_Structure表示pci设备，动态绑定三种具体设备类型：Pci_Device_Structure_General_Device、Pci_Device_Structure_Pci_to_Pci_Bridge、Pci_Device_Structure_Pci_to_Cardbus_Bridge 314 pub trait PciDeviceStructure: Send + Sync { 315 /// @brief 获取设备类型 316 /// @return HeaderType 设备类型 317 fn header_type(&self) -> HeaderType; 318 /// @brief 当其为standard设备时返回&Pci_Device_Structure_General_Device，其余情况返回None 319 #[inline(always)] 320 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 321 None 322 } 323 /// @brief 当其为pci to pci bridge设备时返回&Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 324 #[inline(always)] 325 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 326 None 327 } 328 /// @brief 当其为pci to cardbus bridge设备时返回&Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 329 #[inline(always)] 330 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 331 None 332 } 333 /// @brief 获取Pci设备共有的common_header 334 /// @return 返回其不可变引用 335 fn common_header(&self) -> &PciDeviceStructureHeader; 336 /// @brief 当其为standard设备时返回&mut Pci_Device_Structure_General_Device，其余情况返回None 337 #[inline(always)] 338 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 339 None 340 } 341 /// @brief 当其为pci to pci bridge设备时返回&mut Pci_Device_Structure_Pci_to_Pci_Bridge，其余情况返回None 342 #[inline(always)] 343 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 344 None 345 } 346 /// @brief 当其为pci to cardbus bridge设备时返回&mut Pci_Device_Structure_Pci_to_Cardbus_Bridge，其余情况返回None 347 #[inline(always)] 348 fn as_pci_to_carbus_bridge_device_mut( 349 &mut self, 350 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 351 None 352 } 353 /// @brief 返回迭代器，遍历capabilities 354 fn capabilities(&self) -> Option<CapabilityIterator> { 355 None 356 } 357 /// @brief 获取Status、Command寄存器的值 358 fn status_command(&self) -> (Status, Command) { 359 let common_header = self.common_header(); 360 let status = Status::from_bits_truncate(common_header.status); 361 let command = Command::from_bits_truncate(common_header.command); 362 (status, command) 363 } 364 /// @brief 设置Command寄存器的值 365 fn set_command(&mut self, command: Command) { 366 let common_header = self.common_header_mut(); 367 let command = command.bits(); 368 common_header.command = command; 369 pci_root_0().write_config( 370 common_header.bus_device_function, 371 STATUS_COMMAND_OFFSET.into(), 372 command as u32, 373 ); 374 } 375 /// @brief 获取Pci设备共有的common_header 376 /// @return 返回其可变引用 377 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader; 378 379 /// @brief 读取standard设备的bar寄存器，映射后将结果加入结构体的standard_device_bar变量 380 /// @return 只有standard设备才返回成功或者错误，其余返回None 381 #[inline(always)] 382 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 383 None 384 } 385 /// @brief 获取PCI设备的bar寄存器的引用 386 /// @return 387 #[inline(always)] 388 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 389 None 390 } 391 /// @brief 通过设置该pci设备的command 392 fn enable_master(&mut self) { 393 self.set_command(Command::IO_SPACE | Command::MEMORY_SPACE | Command::BUS_MASTER); 394 } 395 /// @brief 寻找设备的msix空间的offset 396 fn msix_capability_offset(&self) -> Option<u8> { 397 for capability in self.capabilities()? { 398 if capability.id == PCI_CAP_ID_MSIX { 399 return Some(capability.offset); 400 } 401 } 402 None 403 } 404 /// @brief 寻找设备的msi空间的offset 405 fn msi_capability_offset(&self) -> Option<u8> { 406 for capability in self.capabilities()? { 407 if capability.id == PCI_CAP_ID_MSI { 408 return Some(capability.offset); 409 } 410 } 411 None 412 } 413 /// @brief 返回结构体中的irq_type的可变引用 414 fn irq_type_mut(&mut self) -> Option<&mut IrqType>; 415 /// @brief 返回结构体中的irq_vector的可变引用 416 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>>; 417 } 418 419 /// Pci_Device_Structure_Header PCI设备结构体共有的头部 420 #[derive(Clone, Debug)] 421 pub struct PciDeviceStructureHeader { 422 // ==== busdevicefunction变量表示该结构体所处的位置 423 pub bus_device_function: BusDeviceFunction, 424 pub vendor_id: u16, // 供应商ID 0xffff是一个无效值，在读取访问不存在的设备的配置空间寄存器时返回 425 pub device_id: u16, // 设备ID，标志特定设备 426 pub command: u16, // 提供对设备生成和响应pci周期的能力的控制 向该寄存器写入0时，设备与pci总线断开除配置空间访问以外的所有连接 427 pub status: u16, // 用于记录pci总线相关时间的状态信息寄存器 428 pub revision_id: u8, // 修订ID，指定特定设备的修订标志符 429 pub prog_if: u8, // 编程接口字节，一个只读寄存器，指定设备具有的寄存器级别的编程接口（如果有的话） 430 pub subclass: u8, // 子类。指定设备执行的特定功能的只读寄存器 431 pub class_code: u8, // 类代码，一个只读寄存器，指定设备执行的功能类型 432 pub cache_line_size: u8, // 缓存线大小：以 32 位为单位指定系统缓存线大小。设备可以限制它可以支持的缓存线大小的数量，如果不支持的值写入该字段，设备将表现得好像写入了 0 值 433 pub latency_timer: u8, // 延迟计时器：以 PCI 总线时钟为单位指定延迟计时器。 434 pub header_type: u8, // 标头类型 a value of 0x0 specifies a general device, a value of 0x1 specifies a PCI-to-PCI bridge, and a value of 0x2 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device. 435 pub bist: u8, // Represents that status and allows control of a devices BIST (built-in self test). 436 // Here is the layout of the BIST register: 437 // | bit7 | bit6 | Bits 5-4 | Bits 3-0 | 438 // | BIST Capable | Start BIST | Reserved | Completion Code | 439 // for more details, please visit https://wiki.osdev.org/PCI 440 } 441 442 /// Pci_Device_Structure_General_Device PCI标准设备结构体 443 #[derive(Clone, Debug)] 444 pub struct PciDeviceStructureGeneralDevice { 445 pub common_header: PciDeviceStructureHeader, 446 // 中断结构体，包括legacy,msi,msix三种情况 447 pub irq_type: IrqType, 448 // 使用的中断号的vec集合 449 pub irq_vector: Vec<IrqNumber>, 450 pub standard_device_bar: PciStandardDeviceBar, 451 pub cardbus_cis_pointer: u32, // 指向卡信息结构，供在 CardBus 和 PCI 之间共享芯片的设备使用。 452 pub subsystem_vendor_id: u16, 453 pub subsystem_id: u16, 454 pub expansion_rom_base_address: u32, 455 pub capabilities_pointer: u8, 456 pub reserved0: u8, 457 pub reserved1: u16, 458 pub reserved2: u32, 459 pub interrupt_line: u8, // 指定设备的中断引脚连接到系统中断控制器的哪个输入，并由任何使用中断引脚的设备实现。对于 x86 架构，此寄存器对应于 PIC IRQ 编号 0-15（而不是 I/O APIC IRQ 编号），并且值0xFF定义为无连接。 460 pub interrupt_pin: u8, // 指定设备使用的中断引脚。其中值为0x1INTA#、0x2INTB#、0x3INTC#、0x4INTD#，0x0表示设备不使用中断引脚。 461 pub min_grant: u8, // 一个只读寄存器，用于指定设备所需的突发周期长度（以 1/4 微秒为单位）（假设时钟速率为 33 MHz） 462 pub max_latency: u8, // 一个只读寄存器，指定设备需要多长时间访问一次 PCI 总线（以 1/4 微秒为单位）。 463 } 464 impl PciDeviceStructure for PciDeviceStructureGeneralDevice { 465 #[inline(always)] 466 fn header_type(&self) -> HeaderType { 467 HeaderType::Standard 468 } 469 #[inline(always)] 470 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 471 Some(self) 472 } 473 #[inline(always)] 474 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 475 Some(self) 476 } 477 #[inline(always)] 478 fn common_header(&self) -> &PciDeviceStructureHeader { 479 &self.common_header 480 } 481 #[inline(always)] 482 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 483 &mut self.common_header 484 } 485 fn capabilities(&self) -> Option<CapabilityIterator> { 486 Some(CapabilityIterator { 487 bus_device_function: self.common_header.bus_device_function, 488 next_capability_offset: Some(self.capabilities_pointer), 489 }) 490 } 491 fn bar_ioremap(&mut self) -> Option<Result<u8, PciError>> { 492 let common_header = &self.common_header; 493 match pci_bar_init(common_header.bus_device_function) { 494 Ok(bar) => { 495 self.standard_device_bar = bar; 496 Some(Ok(0)) 497 } 498 Err(e) => Some(Err(e)), 499 } 500 } 501 fn bar(&mut self) -> Option<&PciStandardDeviceBar> { 502 Some(&self.standard_device_bar) 503 } 504 #[inline(always)] 505 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 506 Some(&mut self.irq_type) 507 } 508 #[inline(always)] 509 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>> { 510 Some(&mut self.irq_vector) 511 } 512 } 513 514 /// Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci桥设备结构体 515 #[derive(Clone, Debug)] 516 pub struct PciDeviceStructurePciToPciBridge { 517 pub common_header: PciDeviceStructureHeader, 518 // 中断结构体，包括legacy,msi,msix三种情况 519 pub irq_type: IrqType, 520 // 使用的中断号的vec集合 521 pub irq_vector: Vec<IrqNumber>, 522 pub bar0: u32, 523 pub bar1: u32, 524 pub primary_bus_number: u8, 525 pub secondary_bus_number: u8, 526 pub subordinate_bus_number: u8, 527 pub secondary_latency_timer: u8, 528 pub io_base: u8, 529 pub io_limit: u8, 530 pub secondary_status: u16, 531 pub memory_base: u16, 532 pub memory_limit: u16, 533 pub prefetchable_memory_base: u16, 534 pub prefetchable_memory_limit: u16, 535 pub prefetchable_base_upper_32_bits: u32, 536 pub prefetchable_limit_upper_32_bits: u32, 537 pub io_base_upper_16_bits: u16, 538 pub io_limit_upper_16_bits: u16, 539 pub capability_pointer: u8, 540 pub reserved0: u8, 541 pub reserved1: u16, 542 pub expansion_rom_base_address: u32, 543 pub interrupt_line: u8, 544 pub interrupt_pin: u8, 545 pub bridge_control: u16, 546 } 547 impl PciDeviceStructure for PciDeviceStructurePciToPciBridge { 548 #[inline(always)] 549 fn header_type(&self) -> HeaderType { 550 HeaderType::PciPciBridge 551 } 552 #[inline(always)] 553 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 554 Some(self) 555 } 556 #[inline(always)] 557 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 558 Some(self) 559 } 560 #[inline(always)] 561 fn common_header(&self) -> &PciDeviceStructureHeader { 562 &self.common_header 563 } 564 #[inline(always)] 565 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 566 &mut self.common_header 567 } 568 #[inline(always)] 569 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 570 Some(&mut self.irq_type) 571 } 572 #[inline(always)] 573 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>> { 574 Some(&mut self.irq_vector) 575 } 576 } 577 /// Pci_Device_Structure_Pci_to_Cardbus_Bridge Pci_to_Cardbus桥设备结构体 578 #[derive(Clone, Debug)] 579 pub struct PciDeviceStructurePciToCardbusBridge { 580 pub common_header: PciDeviceStructureHeader, 581 pub cardbus_socket_ex_ca_base_address: u32, 582 pub offset_of_capabilities_list: u8, 583 pub reserved: u8, 584 pub secondary_status: u16, 585 pub pci_bus_number: u8, 586 pub card_bus_bus_number: u8, 587 pub subordinate_bus_number: u8, 588 pub card_bus_latency_timer: u8, 589 pub memory_base_address0: u32, 590 pub memory_limit0: u32, 591 pub memory_base_address1: u32, 592 pub memory_limit1: u32, 593 pub io_base_address0: u32, 594 pub io_limit0: u32, 595 pub io_base_address1: u32, 596 pub io_limit1: u32, 597 pub interrupt_line: u8, 598 pub interrupt_pin: u8, 599 pub bridge_control: u16, 600 pub subsystem_device_id: u16, 601 pub subsystem_vendor_id: u16, 602 pub pc_card_legacy_mode_base_address_16_bit: u32, 603 } 604 impl PciDeviceStructure for PciDeviceStructurePciToCardbusBridge { 605 #[inline(always)] 606 fn header_type(&self) -> HeaderType { 607 HeaderType::PciCardbusBridge 608 } 609 #[inline(always)] 610 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 611 Some(self) 612 } 613 #[inline(always)] 614 fn as_pci_to_carbus_bridge_device_mut( 615 &mut self, 616 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 617 Some(self) 618 } 619 #[inline(always)] 620 fn common_header(&self) -> &PciDeviceStructureHeader { 621 &self.common_header 622 } 623 #[inline(always)] 624 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 625 &mut self.common_header 626 } 627 #[inline(always)] 628 fn irq_type_mut(&mut self) -> Option<&mut IrqType> { 629 None 630 } 631 #[inline(always)] 632 fn irq_vector_mut(&mut self) -> Option<&mut Vec<IrqNumber>> { 633 None 634 } 635 } 636 637 /// PCI配置空间访问机制 638 /// 639 /// 用于访问PCI设备的功能配置空间的一组机制。 640 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 641 pub enum PciCam { 642 /// PortIO配置访问机制 643 Portiocam, 644 /// PCI内存映射配置访问机制 645 /// 646 /// 为每个设备功能提供256字节的配置空间访问。 647 MmioCam, 648 /// PCIe内存映射增强配置访问机制 649 /// 650 /// 为每个设备功能提供4千字节（4096字节）的配置空间访问。 651 Ecam, 652 } 653 654 impl PciCam { 655 /// Returns the total size in bytes of the memory-mapped region. 656 pub const fn size(self) -> u32 { 657 match self { 658 Self::Portiocam => 0x100000, 659 Self::MmioCam => 0x1000000, 660 Self::Ecam => 0x10000000, 661 } 662 } 663 } 664 665 /// Gets the capabilities 'pointer' for the device function, if any. 666 /// @brief 获取第一个capability 的offset 667 /// @param bus_device_function PCI设备的唯一标识 668 /// @return Option<u8> offset 669 pub fn capabilities_offset(bus_device_function: BusDeviceFunction) -> Option<u8> { 670 let result = pci_root_0().read_config(bus_device_function, STATUS_COMMAND_OFFSET.into()); 671 let status: Status = Status::from_bits_truncate((result >> 16) as u16); 672 if status.contains(Status::CAPABILITIES_LIST) { 673 let cap_pointer = pci_root_0().read_config(bus_device_function, 0x34) as u8 & 0xFC; 674 Some(cap_pointer) 675 } else { 676 None 677 } 678 } 679 680 /// @brief 读取pci设备头部 681 /// @param bus_device_function PCI设备的唯一标识 682 /// @param add_to_list 是否添加到链表 683 /// @return 返回的header(trait 类型) 684 fn pci_read_header( 685 bus_device_function: BusDeviceFunction, 686 add_to_list: bool, 687 ) -> Result<Box<dyn PciDeviceStructure>, PciError> { 688 // 先读取公共header 689 let result = pci_root_0().read_config(bus_device_function, 0x00); 690 let vendor_id = result as u16; 691 let device_id = (result >> 16) as u16; 692 693 let result = pci_root_0().read_config(bus_device_function, 0x04); 694 let command = result as u16; 695 let status = (result >> 16) as u16; 696 697 let result = pci_root_0().read_config(bus_device_function, 0x08); 698 let revision_id = result as u8; 699 let prog_if = (result >> 8) as u8; 700 let subclass = (result >> 16) as u8; 701 let class_code = (result >> 24) as u8; 702 703 let result = pci_root_0().read_config(bus_device_function, 0x0c); 704 let cache_line_size = result as u8; 705 let latency_timer = (result >> 8) as u8; 706 let header_type = (result >> 16) as u8; 707 let bist = (result >> 24) as u8; 708 if vendor_id == 0xffff { 709 return Err(PciError::GetWrongHeader); 710 } 711 let header = PciDeviceStructureHeader { 712 bus_device_function, 713 vendor_id, 714 device_id, 715 command, 716 status, 717 revision_id, 718 prog_if, 719 subclass, 720 class_code, 721 cache_line_size, 722 latency_timer, 723 header_type, 724 bist, 725 }; 726 match HeaderType::from(header_type & 0x7f) { 727 HeaderType::Standard => { 728 let general_device: PciDeviceStructureGeneralDevice = 729 pci_read_general_device_header(header, &bus_device_function); 730 let box_general_device = Box::new(general_device.clone()); 731 let box_general_device_clone = box_general_device.clone(); 732 if add_to_list { 733 PCI_DEVICE_LINKEDLIST.add(box_general_device); 734 //这里实际上不应该使用clone，因为raw是用于sysfs的结构，但是实际上pci设备是在PCI_DEVICE_LINKEDLIST链表上的， 735 //这就导致sysfs呈现的对pci设备的操控接口实际上操控的是pci设备描述符是一个副本 736 //但是无奈这里没有使用Arc 737 //todo：修改pci设备描述符在静态链表中存在的方式，并修改这里的clone操作 738 let raw = PciGeneralDevice::from(&general_device); 739 let _ = pci_device_manager().device_add(Arc::new(raw)); 740 } 741 Ok(box_general_device_clone) 742 } 743 HeaderType::PciPciBridge => { 744 let pci_to_pci_bridge = pci_read_pci_to_pci_bridge_header(header, &bus_device_function); 745 let box_pci_to_pci_bridge = Box::new(pci_to_pci_bridge); 746 let box_pci_to_pci_bridge_clone = box_pci_to_pci_bridge.clone(); 747 if add_to_list { 748 PCI_DEVICE_LINKEDLIST.add(box_pci_to_pci_bridge); 749 } 750 Ok(box_pci_to_pci_bridge_clone) 751 } 752 HeaderType::PciCardbusBridge => { 753 let pci_cardbus_bridge = 754 pci_read_pci_to_cardbus_bridge_header(header, &bus_device_function); 755 let box_pci_cardbus_bridge = Box::new(pci_cardbus_bridge); 756 let box_pci_cardbus_bridge_clone = box_pci_cardbus_bridge.clone(); 757 if add_to_list { 758 PCI_DEVICE_LINKEDLIST.add(box_pci_cardbus_bridge); 759 } 760 Ok(box_pci_cardbus_bridge_clone) 761 } 762 HeaderType::Unrecognised(_) => Err(PciError::UnrecognisedHeaderType), 763 } 764 } 765 766 /// @brief 读取type为0x0的pci设备的header 767 /// 本函数只应被 pci_read_header()调用 768 /// @param common_header 共有头部 769 /// @param bus_device_function PCI设备的唯一标识 770 /// @return Pci_Device_Structure_General_Device 标准设备头部 771 fn pci_read_general_device_header( 772 common_header: PciDeviceStructureHeader, 773 bus_device_function: &BusDeviceFunction, 774 ) -> PciDeviceStructureGeneralDevice { 775 let standard_device_bar = PciStandardDeviceBar::default(); 776 let cardbus_cis_pointer = pci_root_0().read_config(*bus_device_function, 0x28); 777 778 let result = pci_root_0().read_config(*bus_device_function, 0x2c); 779 let subsystem_vendor_id = result as u16; 780 let subsystem_id = (result >> 16) as u16; 781 782 let expansion_rom_base_address = pci_root_0().read_config(*bus_device_function, 0x30); 783 784 let result = pci_root_0().read_config(*bus_device_function, 0x34); 785 let capabilities_pointer = result as u8; 786 let reserved0 = (result >> 8) as u8; 787 let reserved1 = (result >> 16) as u16; 788 789 let reserved2 = pci_root_0().read_config(*bus_device_function, 0x38); 790 791 let result = pci_root_0().read_config(*bus_device_function, 0x3c); 792 let interrupt_line = result as u8; 793 let interrupt_pin = (result >> 8) as u8; 794 let min_grant = (result >> 16) as u8; 795 let max_latency = (result >> 24) as u8; 796 PciDeviceStructureGeneralDevice { 797 common_header, 798 irq_type: IrqType::Unused, 799 irq_vector: Vec::new(), 800 standard_device_bar, 801 cardbus_cis_pointer, 802 subsystem_vendor_id, 803 subsystem_id, 804 expansion_rom_base_address, 805 capabilities_pointer, 806 reserved0, 807 reserved1, 808 reserved2, 809 interrupt_line, 810 interrupt_pin, 811 min_grant, 812 max_latency, 813 } 814 } 815 816 /// @brief 读取type为0x1的pci设备的header 817 /// 本函数只应被 pci_read_header()调用 818 /// @param common_header 共有头部 819 /// @param bus_device_function PCI设备的唯一标识 820 /// @return Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci 桥设备头部 821 fn pci_read_pci_to_pci_bridge_header( 822 common_header: PciDeviceStructureHeader, 823 bus_device_function: &BusDeviceFunction, 824 ) -> PciDeviceStructurePciToPciBridge { 825 let bar0 = pci_root_0().read_config(*bus_device_function, 0x10); 826 let bar1 = pci_root_0().read_config(*bus_device_function, 0x14); 827 828 let result = pci_root_0().read_config(*bus_device_function, 0x18); 829 830 let primary_bus_number = result as u8; 831 let secondary_bus_number = (result >> 8) as u8; 832 let subordinate_bus_number = (result >> 16) as u8; 833 let secondary_latency_timer = (result >> 24) as u8; 834 835 let result = pci_root_0().read_config(*bus_device_function, 0x1c); 836 let io_base = result as u8; 837 let io_limit = (result >> 8) as u8; 838 let secondary_status = (result >> 16) as u16; 839 840 let result = pci_root_0().read_config(*bus_device_function, 0x20); 841 let memory_base = result as u16; 842 let memory_limit = (result >> 16) as u16; 843 844 let result = pci_root_0().read_config(*bus_device_function, 0x24); 845 let prefetchable_memory_base = result as u16; 846 let prefetchable_memory_limit = (result >> 16) as u16; 847 848 let prefetchable_base_upper_32_bits = pci_root_0().read_config(*bus_device_function, 0x28); 849 let prefetchable_limit_upper_32_bits = pci_root_0().read_config(*bus_device_function, 0x2c); 850 851 let result = pci_root_0().read_config(*bus_device_function, 0x30); 852 let io_base_upper_16_bits = result as u16; 853 let io_limit_upper_16_bits = (result >> 16) as u16; 854 855 let result = pci_root_0().read_config(*bus_device_function, 0x34); 856 let capability_pointer = result as u8; 857 let reserved0 = (result >> 8) as u8; 858 let reserved1 = (result >> 16) as u16; 859 860 let expansion_rom_base_address = pci_root_0().read_config(*bus_device_function, 0x38); 861 862 let result = pci_root_0().read_config(*bus_device_function, 0x3c); 863 let interrupt_line = result as u8; 864 let interrupt_pin = (result >> 8) as u8; 865 let bridge_control = (result >> 16) as u16; 866 PciDeviceStructurePciToPciBridge { 867 common_header, 868 irq_type: IrqType::Unused, 869 irq_vector: Vec::new(), 870 bar0, 871 bar1, 872 primary_bus_number, 873 secondary_bus_number, 874 subordinate_bus_number, 875 secondary_latency_timer, 876 io_base, 877 io_limit, 878 secondary_status, 879 memory_base, 880 memory_limit, 881 prefetchable_memory_base, 882 prefetchable_memory_limit, 883 prefetchable_base_upper_32_bits, 884 prefetchable_limit_upper_32_bits, 885 io_base_upper_16_bits, 886 io_limit_upper_16_bits, 887 capability_pointer, 888 reserved0, 889 reserved1, 890 expansion_rom_base_address, 891 interrupt_line, 892 interrupt_pin, 893 bridge_control, 894 } 895 } 896 897 /// @brief 读取type为0x2的pci设备的header 898 /// 本函数只应被 pci_read_header()调用 899 /// @param common_header 共有头部 900 /// @param bus_device_function PCI设备的唯一标识 901 /// @return Pci_Device_Structure_Pci_to_Cardbus_Bridge pci-to-cardbus 桥设备头部 902 fn pci_read_pci_to_cardbus_bridge_header( 903 common_header: PciDeviceStructureHeader, 904 busdevicefunction: &BusDeviceFunction, 905 ) -> PciDeviceStructurePciToCardbusBridge { 906 let cardbus_socket_ex_ca_base_address = pci_root_0().read_config(*busdevicefunction, 0x10); 907 908 let result = pci_root_0().read_config(*busdevicefunction, 0x14); 909 let offset_of_capabilities_list = result as u8; 910 let reserved = (result >> 8) as u8; 911 let secondary_status = (result >> 16) as u16; 912 913 let result = pci_root_0().read_config(*busdevicefunction, 0x18); 914 let pci_bus_number = result as u8; 915 let card_bus_bus_number = (result >> 8) as u8; 916 let subordinate_bus_number = (result >> 16) as u8; 917 let card_bus_latency_timer = (result >> 24) as u8; 918 919 let memory_base_address0 = pci_root_0().read_config(*busdevicefunction, 0x1c); 920 let memory_limit0 = pci_root_0().read_config(*busdevicefunction, 0x20); 921 let memory_base_address1 = pci_root_0().read_config(*busdevicefunction, 0x24); 922 let memory_limit1 = pci_root_0().read_config(*busdevicefunction, 0x28); 923 924 let io_base_address0 = pci_root_0().read_config(*busdevicefunction, 0x2c); 925 let io_limit0 = pci_root_0().read_config(*busdevicefunction, 0x30); 926 let io_base_address1 = pci_root_0().read_config(*busdevicefunction, 0x34); 927 let io_limit1 = pci_root_0().read_config(*busdevicefunction, 0x38); 928 let result = pci_root_0().read_config(*busdevicefunction, 0x3c); 929 let interrupt_line = result as u8; 930 let interrupt_pin = (result >> 8) as u8; 931 let bridge_control = (result >> 16) as u16; 932 933 let result = pci_root_0().read_config(*busdevicefunction, 0x40); 934 let subsystem_device_id = result as u16; 935 let subsystem_vendor_id = (result >> 16) as u16; 936 937 let pc_card_legacy_mode_base_address_16_bit = 938 pci_root_0().read_config(*busdevicefunction, 0x44); 939 PciDeviceStructurePciToCardbusBridge { 940 common_header, 941 cardbus_socket_ex_ca_base_address, 942 offset_of_capabilities_list, 943 reserved, 944 secondary_status, 945 pci_bus_number, 946 card_bus_bus_number, 947 subordinate_bus_number, 948 card_bus_latency_timer, 949 memory_base_address0, 950 memory_limit0, 951 memory_base_address1, 952 memory_limit1, 953 io_base_address0, 954 io_limit0, 955 io_base_address1, 956 io_limit1, 957 interrupt_line, 958 interrupt_pin, 959 bridge_control, 960 subsystem_device_id, 961 subsystem_vendor_id, 962 pc_card_legacy_mode_base_address_16_bit, 963 } 964 } 965 966 /// @brief 检查所有bus上的设备并将其加入链表 967 /// @return 成功返回ok(),失败返回失败原因 968 fn pci_check_all_buses() -> Result<u8, PciError> { 969 info!("Checking all devices in PCI bus..."); 970 let busdevicefunction = BusDeviceFunction { 971 bus: 0, 972 device: 0, 973 function: 0, 974 }; 975 let header = pci_read_header(busdevicefunction, false)?; 976 let common_header = header.common_header(); 977 pci_check_bus(0)?; 978 if common_header.header_type & 0x80 != 0 { 979 for function in 1..8 { 980 pci_check_bus(function)?; 981 } 982 } 983 Ok(0) 984 } 985 /// @brief 检查特定设备并将其加入链表 986 /// @return 成功返回ok(),失败返回失败原因 987 fn pci_check_function(busdevicefunction: BusDeviceFunction) -> Result<u8, PciError> { 988 //debug!("PCI check function {}", busdevicefunction.function); 989 let header = match pci_read_header(busdevicefunction, true) { 990 Ok(header) => header, 991 Err(PciError::GetWrongHeader) => { 992 return Ok(255); 993 } 994 Err(e) => { 995 return Err(e); 996 } 997 }; 998 let common_header = header.common_header(); 999 if (common_header.class_code == 0x06) 1000 && (common_header.subclass == 0x04 || common_header.subclass == 0x09) 1001 { 1002 let pci_to_pci_bridge = header 1003 .as_pci_to_pci_bridge_device() 1004 .ok_or(PciError::PciDeviceStructureTransformError)?; 1005 let secondary_bus = pci_to_pci_bridge.secondary_bus_number; 1006 pci_check_bus(secondary_bus)?; 1007 } 1008 Ok(0) 1009 } 1010 1011 /// @brief 检查device上的设备并将其加入链表 1012 /// @return 成功返回ok(),失败返回失败原因 1013 fn pci_check_device(bus: u8, device: u8) -> Result<u8, PciError> { 1014 //debug!("PCI check device {}", device); 1015 let busdevicefunction = BusDeviceFunction { 1016 bus, 1017 device, 1018 function: 0, 1019 }; 1020 let header = match pci_read_header(busdevicefunction, false) { 1021 Ok(header) => header, 1022 Err(PciError::GetWrongHeader) => { 1023 //设备不存在，直接返回即可，不用终止遍历 1024 return Ok(255); 1025 } 1026 Err(e) => { 1027 return Err(e); 1028 } 1029 }; 1030 pci_check_function(busdevicefunction)?; 1031 let common_header = header.common_header(); 1032 if common_header.header_type & 0x80 != 0 { 1033 debug!( 1034 "Detected multi func device in bus{},device{}", 1035 busdevicefunction.bus, busdevicefunction.device 1036 ); 1037 // 这是一个多function的设备，因此查询剩余的function 1038 for function in 1..8 { 1039 let busdevicefunction = BusDeviceFunction { 1040 bus, 1041 device, 1042 function, 1043 }; 1044 pci_check_function(busdevicefunction)?; 1045 } 1046 } 1047 Ok(0) 1048 } 1049 /// @brief 检查该bus上的设备并将其加入链表 1050 /// @return 成功返回ok(),失败返回失败原因 1051 fn pci_check_bus(bus: u8) -> Result<u8, PciError> { 1052 //debug!("PCI check bus {}", bus); 1053 for device in 0..32 { 1054 pci_check_device(bus, device)?; 1055 } 1056 Ok(0) 1057 } 1058 1059 /// pci初始化函数 1060 #[inline(never)] 1061 pub fn pci_init() { 1062 info!("Initializing PCI bus..."); 1063 pci_bus_subsys_init().expect("Failed to init pci bus subsystem"); 1064 if let Err(e) = pci_check_all_buses() { 1065 error!("pci init failed when checking bus because of error: {}", e); 1066 return; 1067 } 1068 info!( 1069 "Total pci device and function num = {}", 1070 PCI_DEVICE_LINKEDLIST.num() 1071 ); 1072 let list = PCI_DEVICE_LINKEDLIST.read(); 1073 for box_pci_device in list.iter() { 1074 let common_header = box_pci_device.common_header(); 1075 match box_pci_device.header_type() { 1076 HeaderType::Standard if common_header.status & 0x10 != 0 => { 1077 info!("Found pci standard device with class code ={} subclass={} status={:#x} cap_pointer={:#x} vendor={:#x}, device id={:#x},bdf={}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer,common_header.vendor_id, common_header.device_id,common_header.bus_device_function); 1078 } 1079 HeaderType::Standard => { 1080 info!( 1081 "Found pci standard device with class code ={} subclass={} status={:#x} ", 1082 common_header.class_code, common_header.subclass, common_header.status 1083 ); 1084 } 1085 HeaderType::PciPciBridge if common_header.status & 0x10 != 0 => { 1086 info!("Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} cap_pointer={:#x}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_pci_to_pci_bridge_device().unwrap().capability_pointer); 1087 } 1088 HeaderType::PciPciBridge => { 1089 info!( 1090 "Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} ", 1091 common_header.class_code, common_header.subclass, common_header.status 1092 ); 1093 } 1094 HeaderType::PciCardbusBridge => { 1095 info!( 1096 "Found pcicardbus bridge device with class code ={} subclass={} status={:#x} ", 1097 common_header.class_code, common_header.subclass, common_header.status 1098 ); 1099 } 1100 HeaderType::Unrecognised(_) => {} 1101 } 1102 } 1103 1104 info!("PCI bus initialized."); 1105 } 1106 1107 /// An identifier for a PCI bus, device and function. 1108 /// PCI设备的唯一标识 1109 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1110 pub struct BusDeviceFunction { 1111 /// The PCI bus number, between 0 and 255. 1112 pub bus: u8, 1113 /// The device number on the bus, between 0 and 31. 1114 pub device: u8, 1115 /// The function number of the device, between 0 and 7. 1116 pub function: u8, 1117 } 1118 impl BusDeviceFunction { 1119 /// Returns whether the device and function numbers are valid, i.e. the device is between 0 and 1120 ///@brief 检测BusDeviceFunction实例是否有效 1121 ///@param self 1122 ///@return bool 是否有效 1123 #[allow(dead_code)] 1124 pub fn valid(&self) -> bool { 1125 self.device < 32 && self.function < 8 1126 } 1127 } 1128 1129 impl From<BusDeviceFunction> for String { 1130 /// # 函数的功能 1131 /// 这里提供一个由BusDeviceFunction到dddd:bb:vv.f字符串的转换函数，主要用于转换成设备的名称（pci设备的名称一般是诸如0000:00:00.1这种) 1132 fn from(value: BusDeviceFunction) -> Self { 1133 //需要注意，这里的0000应该是所谓的“域号”（Domain ID），但是尚不知道是如何获得的，故硬编码在这里 1134 //todo：实现域号的获取 1135 format!( 1136 "0000:{:02x}:{:02x}.{}", 1137 value.bus, value.device, value.function 1138 ) 1139 } 1140 } 1141 ///实现BusDeviceFunction的Display trait，使其可以直接输出 1142 impl Display for BusDeviceFunction { 1143 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 1144 write!( 1145 f, 1146 "bus {} device {} function{}", 1147 self.bus, self.device, self.function 1148 ) 1149 } 1150 } 1151 /// The location allowed for a memory BAR. 1152 /// memory BAR的三种情况 1153 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 1154 pub enum MemoryBarType { 1155 /// The BAR has a 32-bit address and can be mapped anywhere in 32-bit address space. 1156 Width32, 1157 /// The BAR must be mapped below 1MiB. 1158 Below1MiB, 1159 /// The BAR has a 64-bit address and can be mapped anywhere in 64-bit address space. 1160 Width64, 1161 } 1162 ///实现MemoryBarType与u8的类型转换 1163 impl From<MemoryBarType> for u8 { 1164 fn from(bar_type: MemoryBarType) -> Self { 1165 match bar_type { 1166 MemoryBarType::Width32 => 0, 1167 MemoryBarType::Below1MiB => 1, 1168 MemoryBarType::Width64 => 2, 1169 } 1170 } 1171 } 1172 ///实现MemoryBarType与u8的类型转换 1173 impl TryFrom<u8> for MemoryBarType { 1174 type Error = PciError; 1175 fn try_from(value: u8) -> Result<Self, Self::Error> { 1176 match value { 1177 0 => Ok(Self::Width32), 1178 1 => Ok(Self::Below1MiB), 1179 2 => Ok(Self::Width64), 1180 _ => Err(PciError::InvalidBarType), 1181 } 1182 } 1183 } 1184 1185 /// Information about a PCI Base Address Register. 1186 /// BAR的三种类型 Memory/IO/Unused 1187 #[derive(Clone, Debug)] 1188 pub enum BarInfo { 1189 /// The BAR is for a memory region. 1190 Memory { 1191 /// The size of the BAR address and where it can be located. 1192 address_type: MemoryBarType, 1193 /// If true, then reading from the region doesn't have side effects. The CPU may cache reads 1194 /// and merge repeated stores. 1195 prefetchable: bool, 1196 /// The memory address, always 16-byte aligned. 1197 address: u64, 1198 /// The size of the BAR in bytes. 1199 size: u32, 1200 /// The virtaddress for a memory bar(mapped). 1201 mmio_guard: Arc<MMIOSpaceGuard>, 1202 }, 1203 /// The BAR is for an I/O region. 1204 IO { 1205 /// The I/O address, always 4-byte aligned. 1206 address: u32, 1207 /// The size of the BAR in bytes. 1208 size: u32, 1209 }, 1210 Unused, 1211 } 1212 1213 impl BarInfo { 1214 /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO 1215 /// BAR. 1216 ///@brief 得到某个bar的memory_address与size(前提是他的类型为Memory Bar) 1217 ///@param self 1218 ///@return Option<(u64, u32) 是Memory Bar返回内存地址与大小，不是则返回None 1219 pub fn memory_address_size(&self) -> Option<(u64, u32)> { 1220 if let Self::Memory { address, size, .. } = self { 1221 Some((*address, *size)) 1222 } else { 1223 None 1224 } 1225 } 1226 ///@brief 得到某个bar的virtaddress(前提是他的类型为Memory Bar) 1227 ///@param self 1228 ///@return Option<(u64) 是Memory Bar返回映射的虚拟地址，不是则返回None 1229 pub fn virtual_address(&self) -> Option<VirtAddr> { 1230 if let Self::Memory { mmio_guard, .. } = self { 1231 Some(mmio_guard.vaddr()) 1232 } else { 1233 None 1234 } 1235 } 1236 } 1237 ///实现BarInfo的Display trait，自定义输出 1238 impl Display for BarInfo { 1239 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1240 match self { 1241 Self::Memory { 1242 address_type, 1243 prefetchable, 1244 address, 1245 size, 1246 mmio_guard, 1247 } => write!( 1248 f, 1249 "Memory space at {:#010x}, size {}, type {:?}, prefetchable {}, mmio_guard: {:?}", 1250 address, size, address_type, prefetchable, mmio_guard 1251 ), 1252 Self::IO { address, size } => { 1253 write!(f, "I/O space at {:#010x}, size {}", address, size) 1254 } 1255 Self::Unused => { 1256 write!(f, "Unused bar") 1257 } 1258 } 1259 } 1260 } 1261 // todo 增加对桥的bar的支持 1262 pub trait PciDeviceBar {} 1263 1264 ///一个普通PCI设备（非桥）有6个BAR寄存器，PciStandardDeviceBar存储其全部信息 1265 #[derive(Clone, Debug)] 1266 pub struct PciStandardDeviceBar { 1267 bar0: BarInfo, 1268 bar1: BarInfo, 1269 bar2: BarInfo, 1270 bar3: BarInfo, 1271 bar4: BarInfo, 1272 bar5: BarInfo, 1273 } 1274 1275 impl PciStandardDeviceBar { 1276 ///@brief 得到某个bar的barinfo 1277 ///@param self ，bar_index(0-5) 1278 ///@return Result<&BarInfo, PciError> bar_index在0-5则返回对应的bar_info结构体，超出范围则返回错误 1279 pub fn get_bar(&self, bar_index: u8) -> Result<&BarInfo, PciError> { 1280 match bar_index { 1281 0 => Ok(&self.bar0), 1282 1 => Ok(&self.bar1), 1283 2 => Ok(&self.bar2), 1284 3 => Ok(&self.bar3), 1285 4 => Ok(&self.bar4), 1286 5 => Ok(&self.bar5), 1287 _ => Err(PciError::InvalidBarType), 1288 } 1289 } 1290 } 1291 ///实现PciStandardDeviceBar的Display trait，使其可以直接输出 1292 impl Display for PciStandardDeviceBar { 1293 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 1294 write!( 1295 f, 1296 "\r\nBar0:{}\r\nBar1:{}\r\nBar2:{}\r\nBar3:{}\r\nBar4:{}\r\nBar5:{}", 1297 self.bar0, self.bar1, self.bar2, self.bar3, self.bar4, self.bar5 1298 ) 1299 } 1300 } 1301 ///实现PciStandardDeviceBar的Default trait，使其可以简单初始化 1302 impl Default for PciStandardDeviceBar { 1303 fn default() -> Self { 1304 PciStandardDeviceBar { 1305 bar0: BarInfo::Unused, 1306 bar1: BarInfo::Unused, 1307 bar2: BarInfo::Unused, 1308 bar3: BarInfo::Unused, 1309 bar4: BarInfo::Unused, 1310 bar5: BarInfo::Unused, 1311 } 1312 } 1313 } 1314 1315 ///@brief 将某个pci设备的bar寄存器读取值后映射到虚拟地址 1316 ///@param self ，bus_device_function PCI设备的唯一标识符 1317 ///@return Result<PciStandardDeviceBar, PciError> 成功则返回对应的PciStandardDeviceBar结构体，失败则返回错误类型 1318 pub fn pci_bar_init( 1319 bus_device_function: BusDeviceFunction, 1320 ) -> Result<PciStandardDeviceBar, PciError> { 1321 let mut device_bar: PciStandardDeviceBar = PciStandardDeviceBar::default(); 1322 let mut bar_index_ignore: u8 = 255; 1323 for bar_index in 0..6 { 1324 if bar_index == bar_index_ignore { 1325 continue; 1326 } 1327 let bar_info; 1328 let bar_orig = 1329 pci_root_0().read_config(bus_device_function, (BAR0_OFFSET + 4 * bar_index).into()); 1330 pci_root_0().write_config( 1331 bus_device_function, 1332 (BAR0_OFFSET + 4 * bar_index).into(), 1333 0xffffffff, 1334 ); 1335 let size_mask = 1336 pci_root_0().read_config(bus_device_function, (BAR0_OFFSET + 4 * bar_index).into()); 1337 // A wrapping add is necessary to correctly handle the case of unused BARs, which read back 1338 // as 0, and should be treated as size 0. 1339 let size = (!(size_mask & 0xfffffff0)).wrapping_add(1); 1340 //debug!("bar_orig:{:#x},size: {:#x}", bar_orig,size); 1341 // Restore the original value. 1342 pci_root_0().write_config( 1343 bus_device_function, 1344 (BAR0_OFFSET + 4 * bar_index).into(), 1345 bar_orig, 1346 ); 1347 if size == 0 { 1348 continue; 1349 } 1350 if bar_orig & 0x00000001 == 0x00000001 { 1351 // I/O space 1352 let address = bar_orig & 0xfffffffc; 1353 bar_info = BarInfo::IO { address, size }; 1354 } else { 1355 // Memory space 1356 let mut address = u64::from(bar_orig & 0xfffffff0); 1357 let prefetchable = bar_orig & 0x00000008 != 0; 1358 let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?; 1359 if address_type == MemoryBarType::Width64 { 1360 if bar_index >= 5 { 1361 return Err(PciError::InvalidBarType); 1362 } 1363 let address_top = pci_root_0().read_config( 1364 bus_device_function, 1365 (BAR0_OFFSET + 4 * (bar_index + 1)).into(), 1366 ); 1367 address |= u64::from(address_top) << 32; 1368 bar_index_ignore = bar_index + 1; //下个bar跳过，因为64位的memory bar覆盖了两个bar 1369 } 1370 let pci_address = PciAddr::new(address as usize); 1371 let paddr = PciArch::address_pci_to_physical(pci_address); //PCI总线域物理地址转换为存储器域物理地址 1372 1373 let space_guard: Arc<MMIOSpaceGuard>; 1374 unsafe { 1375 let size_want = size as usize; 1376 let tmp = mmio_pool() 1377 .create_mmio(size_want) 1378 .map_err(|_| PciError::CreateMmioError)?; 1379 space_guard = Arc::new(tmp); 1380 //debug!("Pci bar init: mmio space: {space_guard:?}, paddr={paddr:?}, size_want={size_want}"); 1381 assert!( 1382 space_guard.map_phys(paddr, size_want).is_ok(), 1383 "pci_bar_init: map_phys failed" 1384 ); 1385 } 1386 bar_info = BarInfo::Memory { 1387 address_type, 1388 prefetchable, 1389 address, 1390 size, 1391 mmio_guard: space_guard, 1392 }; 1393 } 1394 match bar_index { 1395 0 => { 1396 device_bar.bar0 = bar_info; 1397 } 1398 1 => { 1399 device_bar.bar1 = bar_info; 1400 } 1401 2 => { 1402 device_bar.bar2 = bar_info; 1403 } 1404 3 => { 1405 device_bar.bar3 = bar_info; 1406 } 1407 4 => { 1408 device_bar.bar4 = bar_info; 1409 } 1410 5 => { 1411 device_bar.bar5 = bar_info; 1412 } 1413 _ => {} 1414 } 1415 } 1416 //debug!("pci_device_bar:{}", device_bar); 1417 return Ok(device_bar); 1418 } 1419 1420 /// Information about a PCI device capability. 1421 /// PCI设备的capability的信息 1422 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1423 pub struct CapabilityInfo { 1424 /// The offset of the capability in the PCI configuration space of the device function. 1425 pub offset: u8, 1426 /// The ID of the capability. 1427 pub id: u8, 1428 /// The third and fourth bytes of the capability, to save reading them again. 1429 pub private_header: u16, 1430 } 1431 1432 /// Iterator over capabilities for a device. 1433 /// 创建迭代器以遍历PCI设备的capability 1434 #[derive(Debug)] 1435 pub struct CapabilityIterator { 1436 pub bus_device_function: BusDeviceFunction, 1437 pub next_capability_offset: Option<u8>, 1438 } 1439 1440 impl Iterator for CapabilityIterator { 1441 type Item = CapabilityInfo; 1442 fn next(&mut self) -> Option<Self::Item> { 1443 let offset = self.next_capability_offset?; 1444 1445 // Read the first 4 bytes of the capability. 1446 let capability_header = pci_root_0().read_config(self.bus_device_function, offset.into()); 1447 let id = capability_header as u8; 1448 let next_offset = (capability_header >> 8) as u8; 1449 let private_header = (capability_header >> 16) as u16; 1450 1451 self.next_capability_offset = if next_offset == 0 { 1452 None 1453 } else if next_offset < 64 || next_offset & 0x3 != 0 { 1454 warn!("Invalid next capability offset {:#04x}", next_offset); 1455 None 1456 } else { 1457 Some(next_offset) 1458 }; 1459 1460 Some(CapabilityInfo { 1461 offset, 1462 id, 1463 private_header, 1464 }) 1465 } 1466 } 1467 1468 /// Information about a PCIe device capability. 1469 /// PCIe设备的external capability的信息 1470 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 1471 pub struct ExternalCapabilityInfo { 1472 /// The offset of the capability in the PCI configuration space of the device function. 1473 pub offset: u16, 1474 /// The ID of the capability. 1475 pub id: u16, 1476 /// The third and fourth bytes of the capability, to save reading them again. 1477 pub capability_version: u8, 1478 } 1479 1480 /// Iterator over capabilities for a device. 1481 /// 创建迭代器以遍历PCIe设备的external capability 1482 #[derive(Debug)] 1483 pub struct ExternalCapabilityIterator<'a> { 1484 pub root: &'a PciRoot, 1485 pub bus_device_function: BusDeviceFunction, 1486 pub next_capability_offset: Option<u16>, 1487 } 1488 impl<'a> Iterator for ExternalCapabilityIterator<'a> { 1489 type Item = ExternalCapabilityInfo; 1490 fn next(&mut self) -> Option<Self::Item> { 1491 let offset = self.next_capability_offset?; 1492 1493 // Read the first 4 bytes of the capability. 1494 let capability_header = self.root.read_config(self.bus_device_function, offset); 1495 let id = capability_header as u16; 1496 let next_offset = (capability_header >> 20) as u16; 1497 let capability_version = ((capability_header >> 16) & 0xf) as u8; 1498 1499 self.next_capability_offset = if next_offset == 0 { 1500 None 1501 } else if next_offset < 0x100 || next_offset & 0x3 != 0 { 1502 warn!("Invalid next capability offset {:#04x}", next_offset); 1503 None 1504 } else { 1505 Some(next_offset) 1506 }; 1507 1508 Some(ExternalCapabilityInfo { 1509 offset, 1510 id, 1511 capability_version, 1512 }) 1513 } 1514 } 1515