178bf93f0SYJwu2023 #![allow(dead_code)] 278bf93f0SYJwu2023 // 目前仅支持单主桥单Segment 378bf93f0SYJwu2023 478bf93f0SYJwu2023 use crate::arch::{PciArch, TraitPciArch}; 526d84a31SYJwu2023 use crate::include::bindings::bindings::{ 678bf93f0SYJwu2023 initial_mm, mm_map, mm_struct, PAGE_2M_SIZE, VM_DONTCOPY, VM_IO, 726d84a31SYJwu2023 }; 878bf93f0SYJwu2023 use crate::libs::rwlock::{RwLock, RwLockReadGuard, RwLockWriteGuard}; 926d84a31SYJwu2023 use crate::mm::mmio_buddy::MMIO_POOL; 1078bf93f0SYJwu2023 use crate::{kdebug, kerror, kinfo, kwarn}; 1178bf93f0SYJwu2023 use alloc::vec::Vec; 1278bf93f0SYJwu2023 use alloc::{boxed::Box, collections::LinkedList}; 1326d84a31SYJwu2023 use bitflags::bitflags; 1426d84a31SYJwu2023 use core::{ 1526d84a31SYJwu2023 convert::TryFrom, 1626d84a31SYJwu2023 fmt::{self, Display, Formatter}, 1726d84a31SYJwu2023 }; 1878bf93f0SYJwu2023 // PCI_DEVICE_LINKEDLIST 添加了读写锁的全局链表,里面存储了检索到的PCI设备结构体 1978bf93f0SYJwu2023 // PCI_ROOT_0 Segment为0的全局PciRoot 2078bf93f0SYJwu2023 lazy_static! { 2178bf93f0SYJwu2023 pub static ref PCI_DEVICE_LINKEDLIST: PciDeviceLinkedList = PciDeviceLinkedList::new(); 2278bf93f0SYJwu2023 pub static ref PCI_ROOT_0: Option<PciRoot> = { 2378bf93f0SYJwu2023 match PciRoot::new(0) { 2478bf93f0SYJwu2023 Ok(root) => Some(root), 2578bf93f0SYJwu2023 Err(err) => { 2678bf93f0SYJwu2023 kerror!("Pci_root init failed because of error: {}", err); 2778bf93f0SYJwu2023 None 2878bf93f0SYJwu2023 } 2978bf93f0SYJwu2023 } 3078bf93f0SYJwu2023 }; 3178bf93f0SYJwu2023 } 3278bf93f0SYJwu2023 3378bf93f0SYJwu2023 /// 添加了读写锁的链表,存储PCI设备结构体 3478bf93f0SYJwu2023 pub struct PciDeviceLinkedList { 3578bf93f0SYJwu2023 list: RwLock<LinkedList<Box<dyn PciDeviceStructure>>>, 3678bf93f0SYJwu2023 } 3778bf93f0SYJwu2023 3878bf93f0SYJwu2023 impl PciDeviceLinkedList { 3978bf93f0SYJwu2023 /// @brief 初始化结构体 4078bf93f0SYJwu2023 fn new() -> Self { 4178bf93f0SYJwu2023 PciDeviceLinkedList { 4278bf93f0SYJwu2023 list: RwLock::new(LinkedList::new()), 4378bf93f0SYJwu2023 } 4478bf93f0SYJwu2023 } 4578bf93f0SYJwu2023 /// @brief 获取可读的linkedlist(读锁守卫) 4678bf93f0SYJwu2023 /// @return RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> 读锁守卫 47*13776c11Slogin pub fn read(&self) -> RwLockReadGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 4878bf93f0SYJwu2023 self.list.read() 4978bf93f0SYJwu2023 } 5078bf93f0SYJwu2023 /// @brief 获取可写的linkedlist(写锁守卫) 5178bf93f0SYJwu2023 /// @return RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> 写锁守卫 52*13776c11Slogin pub fn write(&self) -> RwLockWriteGuard<LinkedList<Box<dyn PciDeviceStructure>>> { 5378bf93f0SYJwu2023 self.list.write() 5478bf93f0SYJwu2023 } 5578bf93f0SYJwu2023 /// @brief 获取链表中PCI结构体数目 5678bf93f0SYJwu2023 /// @return usize 链表中PCI结构体数目 5778bf93f0SYJwu2023 pub fn num(&self) -> usize { 5878bf93f0SYJwu2023 let list = self.list.read(); 5978bf93f0SYJwu2023 list.len() 6078bf93f0SYJwu2023 } 6178bf93f0SYJwu2023 /// @brief 添加Pci设备结构体到链表中 6278bf93f0SYJwu2023 pub fn add(&self, device: Box<dyn PciDeviceStructure>) { 6378bf93f0SYJwu2023 let mut list = self.list.write(); 6478bf93f0SYJwu2023 list.push_back(device); 6578bf93f0SYJwu2023 } 6678bf93f0SYJwu2023 } 6778bf93f0SYJwu2023 6878bf93f0SYJwu2023 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其可变引用 6978bf93f0SYJwu2023 /// @param list 链表的写锁守卫 7078bf93f0SYJwu2023 /// @param class_code 寄存器值 7178bf93f0SYJwu2023 /// @param subclass 寄存器值,与class_code一起确定设备类型 7278bf93f0SYJwu2023 /// @return Vec<&'a mut Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的可变引用的容器 7378bf93f0SYJwu2023 pub fn get_pci_device_structure_mut<'a>( 7478bf93f0SYJwu2023 list: &'a mut RwLockWriteGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 7578bf93f0SYJwu2023 class_code: u8, 7678bf93f0SYJwu2023 subclass: u8, 7778bf93f0SYJwu2023 ) -> Vec<&'a mut Box<(dyn PciDeviceStructure)>> { 7878bf93f0SYJwu2023 let mut result = Vec::new(); 7978bf93f0SYJwu2023 for box_pci_device_structure in list.iter_mut() { 8078bf93f0SYJwu2023 let common_header = (*box_pci_device_structure).common_header(); 8178bf93f0SYJwu2023 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 8278bf93f0SYJwu2023 result.push(box_pci_device_structure); 8378bf93f0SYJwu2023 } 8478bf93f0SYJwu2023 } 8578bf93f0SYJwu2023 result 8678bf93f0SYJwu2023 } 8778bf93f0SYJwu2023 /// @brief 在链表中寻找满足条件的PCI设备结构体并返回其不可变引用 8878bf93f0SYJwu2023 /// @param list 链表的读锁守卫 8978bf93f0SYJwu2023 /// @param class_code 寄存器值 9078bf93f0SYJwu2023 /// @param subclass 寄存器值,与class_code一起确定设备类型 9178bf93f0SYJwu2023 /// @return Vec<&'a Box<(dyn PciDeviceStructure) 包含链表中所有满足条件的PCI结构体的不可变引用的容器 9278bf93f0SYJwu2023 pub fn get_pci_device_structure<'a>( 9378bf93f0SYJwu2023 list: &'a mut RwLockReadGuard<'_, LinkedList<Box<dyn PciDeviceStructure>>>, 9478bf93f0SYJwu2023 class_code: u8, 9578bf93f0SYJwu2023 subclass: u8, 9678bf93f0SYJwu2023 ) -> Vec<&'a Box<(dyn PciDeviceStructure)>> { 9778bf93f0SYJwu2023 let mut result = Vec::new(); 9878bf93f0SYJwu2023 for box_pci_device_structure in list.iter() { 9978bf93f0SYJwu2023 let common_header = (*box_pci_device_structure).common_header(); 10078bf93f0SYJwu2023 if (common_header.class_code == class_code) && (common_header.subclass == subclass) { 10178bf93f0SYJwu2023 result.push(box_pci_device_structure); 10278bf93f0SYJwu2023 } 10378bf93f0SYJwu2023 } 10478bf93f0SYJwu2023 result 10578bf93f0SYJwu2023 } 10678bf93f0SYJwu2023 10726d84a31SYJwu2023 //Bar0寄存器的offset 10826d84a31SYJwu2023 const BAR0_OFFSET: u8 = 0x10; 10926d84a31SYJwu2023 //Status、Command寄存器的offset 11026d84a31SYJwu2023 const STATUS_COMMAND_OFFSET: u8 = 0x04; 11126d84a31SYJwu2023 /// ID for vendor-specific PCI capabilities.(Virtio Capabilities) 11226d84a31SYJwu2023 pub const PCI_CAP_ID_VNDR: u8 = 0x09; 11378bf93f0SYJwu2023 pub const PORT_PCI_CONFIG_ADDRESS: u16 = 0xcf8; 11478bf93f0SYJwu2023 pub const PORT_PCI_CONFIG_DATA: u16 = 0xcfc; 11578bf93f0SYJwu2023 // pci设备分组的id 11678bf93f0SYJwu2023 pub type SegmentGroupNumber = u16; //理论上最多支持65535个Segment_Group 11726d84a31SYJwu2023 11826d84a31SYJwu2023 bitflags! { 11926d84a31SYJwu2023 /// The status register in PCI configuration space. 12026d84a31SYJwu2023 pub struct Status: u16 { 12126d84a31SYJwu2023 // Bits 0-2 are reserved. 12226d84a31SYJwu2023 /// The state of the device's INTx# signal. 12326d84a31SYJwu2023 const INTERRUPT_STATUS = 1 << 3; 12426d84a31SYJwu2023 /// The device has a linked list of capabilities. 12526d84a31SYJwu2023 const CAPABILITIES_LIST = 1 << 4; 12626d84a31SYJwu2023 /// The device is capabile of running at 66 MHz rather than 33 MHz. 12726d84a31SYJwu2023 const MHZ_66_CAPABLE = 1 << 5; 12826d84a31SYJwu2023 // Bit 6 is reserved. 12926d84a31SYJwu2023 /// The device can accept fast back-to-back transactions not from the same agent. 13026d84a31SYJwu2023 const FAST_BACK_TO_BACK_CAPABLE = 1 << 7; 13126d84a31SYJwu2023 /// The bus agent observed a parity error (if parity error handling is enabled). 13226d84a31SYJwu2023 const MASTER_DATA_PARITY_ERROR = 1 << 8; 13326d84a31SYJwu2023 // Bits 9-10 are DEVSEL timing. 13426d84a31SYJwu2023 /// A target device terminated a transaction with target-abort. 13526d84a31SYJwu2023 const SIGNALED_TARGET_ABORT = 1 << 11; 13626d84a31SYJwu2023 /// A master device transaction was terminated with target-abort. 13726d84a31SYJwu2023 const RECEIVED_TARGET_ABORT = 1 << 12; 13826d84a31SYJwu2023 /// A master device transaction was terminated with master-abort. 13926d84a31SYJwu2023 const RECEIVED_MASTER_ABORT = 1 << 13; 14026d84a31SYJwu2023 /// A device asserts SERR#. 14126d84a31SYJwu2023 const SIGNALED_SYSTEM_ERROR = 1 << 14; 14226d84a31SYJwu2023 /// The device detects a parity error, even if parity error handling is disabled. 14326d84a31SYJwu2023 const DETECTED_PARITY_ERROR = 1 << 15; 14426d84a31SYJwu2023 } 14526d84a31SYJwu2023 } 14626d84a31SYJwu2023 14726d84a31SYJwu2023 bitflags! { 14826d84a31SYJwu2023 /// The command register in PCI configuration space. 14978bf93f0SYJwu2023 pub struct Command: u16 { 15026d84a31SYJwu2023 /// The device can respond to I/O Space accesses. 15126d84a31SYJwu2023 const IO_SPACE = 1 << 0; 15226d84a31SYJwu2023 /// The device can respond to Memory Space accesses. 15326d84a31SYJwu2023 const MEMORY_SPACE = 1 << 1; 15426d84a31SYJwu2023 /// The device can behave as a bus master. 15526d84a31SYJwu2023 const BUS_MASTER = 1 << 2; 15626d84a31SYJwu2023 /// The device can monitor Special Cycle operations. 15726d84a31SYJwu2023 const SPECIAL_CYCLES = 1 << 3; 15826d84a31SYJwu2023 /// The device can generate the Memory Write and Invalidate command. 15926d84a31SYJwu2023 const MEMORY_WRITE_AND_INVALIDATE_ENABLE = 1 << 4; 16026d84a31SYJwu2023 /// The device will snoop palette register data. 16126d84a31SYJwu2023 const VGA_PALETTE_SNOOP = 1 << 5; 16226d84a31SYJwu2023 /// The device should take its normal action when a parity error is detected. 16326d84a31SYJwu2023 const PARITY_ERROR_RESPONSE = 1 << 6; 16426d84a31SYJwu2023 // Bit 7 is reserved. 16526d84a31SYJwu2023 /// The SERR# driver is enabled. 16626d84a31SYJwu2023 const SERR_ENABLE = 1 << 8; 16726d84a31SYJwu2023 /// The device is allowed to generate fast back-to-back transactions. 16826d84a31SYJwu2023 const FAST_BACK_TO_BACK_ENABLE = 1 << 9; 16926d84a31SYJwu2023 /// Assertion of the device's INTx# signal is disabled. 17026d84a31SYJwu2023 const INTERRUPT_DISABLE = 1 << 10; 17126d84a31SYJwu2023 } 17226d84a31SYJwu2023 } 17326d84a31SYJwu2023 17478bf93f0SYJwu2023 /// The type of a PCI device function header. 17578bf93f0SYJwu2023 /// 标头类型/设备类型 17678bf93f0SYJwu2023 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 17778bf93f0SYJwu2023 pub enum HeaderType { 17878bf93f0SYJwu2023 /// A normal PCI device. 17978bf93f0SYJwu2023 Standard, 18078bf93f0SYJwu2023 /// A PCI to PCI bridge. 18178bf93f0SYJwu2023 PciPciBridge, 18278bf93f0SYJwu2023 /// A PCI to CardBus bridge. 18378bf93f0SYJwu2023 PciCardbusBridge, 18478bf93f0SYJwu2023 /// Unrecognised header type. 18578bf93f0SYJwu2023 Unrecognised(u8), 18678bf93f0SYJwu2023 } 18778bf93f0SYJwu2023 /// u8到HeaderType的转换 18878bf93f0SYJwu2023 impl From<u8> for HeaderType { 18978bf93f0SYJwu2023 fn from(value: u8) -> Self { 19078bf93f0SYJwu2023 match value { 19178bf93f0SYJwu2023 0x00 => Self::Standard, 19278bf93f0SYJwu2023 0x01 => Self::PciPciBridge, 19378bf93f0SYJwu2023 0x02 => Self::PciCardbusBridge, 19478bf93f0SYJwu2023 _ => Self::Unrecognised(value), 19578bf93f0SYJwu2023 } 19678bf93f0SYJwu2023 } 19778bf93f0SYJwu2023 } 19878bf93f0SYJwu2023 /// Pci可能触发的各种错误 19978bf93f0SYJwu2023 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 20078bf93f0SYJwu2023 pub enum PciError { 20178bf93f0SYJwu2023 /// The device reported an invalid BAR type. 20278bf93f0SYJwu2023 InvalidBarType, 20378bf93f0SYJwu2023 CreateMmioError, 20478bf93f0SYJwu2023 InvalidBusDeviceFunction, 20578bf93f0SYJwu2023 SegmentNotFound, 20678bf93f0SYJwu2023 GetWrongHeader, 20778bf93f0SYJwu2023 UnrecognisedHeaderType, 20878bf93f0SYJwu2023 PciDeviceStructureTransformError, 20978bf93f0SYJwu2023 } 21078bf93f0SYJwu2023 ///实现PciError的Display trait,使其可以直接输出 21178bf93f0SYJwu2023 impl Display for PciError { 21278bf93f0SYJwu2023 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 21378bf93f0SYJwu2023 match self { 21478bf93f0SYJwu2023 Self::InvalidBarType => write!(f, "Invalid PCI BAR type."), 21578bf93f0SYJwu2023 Self::CreateMmioError => write!(f, "Error occurred while creating mmio."), 21678bf93f0SYJwu2023 Self::InvalidBusDeviceFunction => write!(f, "Found invalid BusDeviceFunction."), 21778bf93f0SYJwu2023 Self::SegmentNotFound => write!(f, "Target segment not found"), 21878bf93f0SYJwu2023 Self::GetWrongHeader => write!(f, "GetWrongHeader with vendor id 0xffff"), 21978bf93f0SYJwu2023 Self::UnrecognisedHeaderType => write!(f, "Found device with unrecognised header type"), 22078bf93f0SYJwu2023 Self::PciDeviceStructureTransformError => { 22178bf93f0SYJwu2023 write!(f, "Found None When transform Pci device structure") 22278bf93f0SYJwu2023 } 22378bf93f0SYJwu2023 } 22478bf93f0SYJwu2023 } 22578bf93f0SYJwu2023 } 22678bf93f0SYJwu2023 22778bf93f0SYJwu2023 /// trait类型Pci_Device_Structure表示pci设备,动态绑定三种具体设备类型:Pci_Device_Structure_General_Device、Pci_Device_Structure_Pci_to_Pci_Bridge、Pci_Device_Structure_Pci_to_Cardbus_Bridge 22878bf93f0SYJwu2023 pub trait PciDeviceStructure: Send + Sync { 22978bf93f0SYJwu2023 /// @brief 获取设备类型 23078bf93f0SYJwu2023 /// @return HeaderType 设备类型 23178bf93f0SYJwu2023 fn header_type(&self) -> HeaderType; 23278bf93f0SYJwu2023 /// @brief 当其为standard设备时返回&Pci_Device_Structure_General_Device,其余情况返回None 23378bf93f0SYJwu2023 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 23478bf93f0SYJwu2023 None 23578bf93f0SYJwu2023 } 23678bf93f0SYJwu2023 /// @brief 当其为pci to pci bridge设备时返回&Pci_Device_Structure_Pci_to_Pci_Bridge,其余情况返回None 23778bf93f0SYJwu2023 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 23878bf93f0SYJwu2023 None 23978bf93f0SYJwu2023 } 24078bf93f0SYJwu2023 /// @brief 当其为pci to cardbus bridge设备时返回&Pci_Device_Structure_Pci_to_Cardbus_Bridge,其余情况返回None 24178bf93f0SYJwu2023 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 24278bf93f0SYJwu2023 None 24378bf93f0SYJwu2023 } 24478bf93f0SYJwu2023 /// @brief 获取Pci设备共有的common_header 24578bf93f0SYJwu2023 /// @return 返回其不可变引用 24678bf93f0SYJwu2023 fn common_header(&self) -> &PciDeviceStructureHeader; 24778bf93f0SYJwu2023 /// @brief 当其为standard设备时返回&mut Pci_Device_Structure_General_Device,其余情况返回None 24878bf93f0SYJwu2023 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 24978bf93f0SYJwu2023 None 25078bf93f0SYJwu2023 } 25178bf93f0SYJwu2023 /// @brief 当其为pci to pci bridge设备时返回&mut Pci_Device_Structure_Pci_to_Pci_Bridge,其余情况返回None 25278bf93f0SYJwu2023 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 25378bf93f0SYJwu2023 None 25478bf93f0SYJwu2023 } 25578bf93f0SYJwu2023 /// @brief 当其为pci to cardbus bridge设备时返回&mut Pci_Device_Structure_Pci_to_Cardbus_Bridge,其余情况返回None 25678bf93f0SYJwu2023 fn as_pci_to_carbus_bridge_device_mut( 25778bf93f0SYJwu2023 &mut self, 25878bf93f0SYJwu2023 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 25978bf93f0SYJwu2023 None 26078bf93f0SYJwu2023 } 26178bf93f0SYJwu2023 /// @brief 返回迭代器,遍历capabilities 26278bf93f0SYJwu2023 fn capabilities(&self) -> Option<CapabilityIterator> { 26378bf93f0SYJwu2023 None 26478bf93f0SYJwu2023 } 26578bf93f0SYJwu2023 /// @brief 获取Status、Command寄存器的值 26678bf93f0SYJwu2023 fn status_command(&self) -> (Status, Command) { 26778bf93f0SYJwu2023 let common_header = self.common_header(); 26878bf93f0SYJwu2023 let status = Status::from_bits_truncate(common_header.status); 26978bf93f0SYJwu2023 let command = Command::from_bits_truncate(common_header.command); 27078bf93f0SYJwu2023 (status, command) 27178bf93f0SYJwu2023 } 27278bf93f0SYJwu2023 /// @brief 设置Command寄存器的值 27378bf93f0SYJwu2023 fn set_command(&mut self, command: Command) { 27478bf93f0SYJwu2023 let common_header = self.common_header_mut(); 27578bf93f0SYJwu2023 let command = command.bits(); 27678bf93f0SYJwu2023 common_header.command = command; 27778bf93f0SYJwu2023 PciArch::write_config( 27878bf93f0SYJwu2023 &common_header.bus_device_function, 27978bf93f0SYJwu2023 STATUS_COMMAND_OFFSET, 28078bf93f0SYJwu2023 command as u32, 28178bf93f0SYJwu2023 ); 28278bf93f0SYJwu2023 } 28378bf93f0SYJwu2023 /// @brief 获取Pci设备共有的common_header 28478bf93f0SYJwu2023 /// @return 返回其可变引用 28578bf93f0SYJwu2023 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader; 28678bf93f0SYJwu2023 /// @brief 读取standard设备的bar寄存器,映射后将结果加入结构体的standard_device_bar变量 28778bf93f0SYJwu2023 /// @return 只有standard设备才返回成功或者错误,其余返回None 28878bf93f0SYJwu2023 fn bar_init(&mut self) -> Option<Result<u8, PciError>> { 28978bf93f0SYJwu2023 None 29078bf93f0SYJwu2023 } 29178bf93f0SYJwu2023 /// todo 29278bf93f0SYJwu2023 fn msix_init(&mut self) -> Option<Result<u8, PciError>> { 29378bf93f0SYJwu2023 None 29478bf93f0SYJwu2023 } 29578bf93f0SYJwu2023 fn enable_master(&mut self) { 29678bf93f0SYJwu2023 self.set_command(Command::IO_SPACE | Command::MEMORY_SPACE | Command::BUS_MASTER); 29778bf93f0SYJwu2023 } 29878bf93f0SYJwu2023 } 29978bf93f0SYJwu2023 30078bf93f0SYJwu2023 /// Pci_Device_Structure_Header PCI设备结构体共有的头部 30178bf93f0SYJwu2023 #[derive(Clone, Debug)] 30278bf93f0SYJwu2023 pub struct PciDeviceStructureHeader { 30378bf93f0SYJwu2023 // 包含msix table地址的bar的mmio基地址 todo:以下四个作为一个结构体统一管理 30478bf93f0SYJwu2023 pub msix_mmio_vaddr: u64, 30578bf93f0SYJwu2023 pub msix_mmio_size: u64, // msix映射长度 30678bf93f0SYJwu2023 pub msix_offset: u32, // msix表的offset 30778bf93f0SYJwu2023 pub msix_table_size: u16, // msix表的表项数量 30878bf93f0SYJwu2023 // ==== busdevicefunction变量表示该结构体所处的位置 30978bf93f0SYJwu2023 pub bus_device_function: BusDeviceFunction, 31078bf93f0SYJwu2023 pub vendor_id: u16, // 供应商ID 0xffff是一个无效值,在读取访问不存在的设备的配置空间寄存器时返回 31178bf93f0SYJwu2023 pub device_id: u16, // 设备ID,标志特定设备 31278bf93f0SYJwu2023 pub command: u16, // 提供对设备生成和响应pci周期的能力的控制 向该寄存器写入0时,设备与pci总线断开除配置空间访问以外的所有连接 31378bf93f0SYJwu2023 pub status: u16, // 用于记录pci总线相关时间的状态信息寄存器 31478bf93f0SYJwu2023 pub revision_id: u8, // 修订ID,指定特定设备的修订标志符 31578bf93f0SYJwu2023 pub prog_if: u8, // 编程接口字节,一个只读寄存器,指定设备具有的寄存器级别的编程接口(如果有的话) 31678bf93f0SYJwu2023 pub subclass: u8, // 子类。指定设备执行的特定功能的只读寄存器 31778bf93f0SYJwu2023 pub class_code: u8, // 类代码,一个只读寄存器,指定设备执行的功能类型 31878bf93f0SYJwu2023 pub cache_line_size: u8, // 缓存线大小:以 32 位为单位指定系统缓存线大小。设备可以限制它可以支持的缓存线大小的数量,如果不支持的值写入该字段,设备将表现得好像写入了 0 值 31978bf93f0SYJwu2023 pub latency_timer: u8, // 延迟计时器:以 PCI 总线时钟为单位指定延迟计时器。 32078bf93f0SYJwu2023 pub header_type: u8, // 标头类型 a value of 0x0 specifies a general device, a value of 0x1 specifies a PCI-to-PCI bridge, and a value of 0x2 specifies a CardBus bridge. If bit 7 of this register is set, the device has multiple functions; otherwise, it is a single function device. 32178bf93f0SYJwu2023 pub bist: u8, // Represents that status and allows control of a devices BIST (built-in self test). 32278bf93f0SYJwu2023 // Here is the layout of the BIST register: 32378bf93f0SYJwu2023 // | bit7 | bit6 | Bits 5-4 | Bits 3-0 | 32478bf93f0SYJwu2023 // | BIST Capable | Start BIST | Reserved | Completion Code | 32578bf93f0SYJwu2023 // for more details, please visit https://wiki.osdev.org/PCI 32678bf93f0SYJwu2023 } 32778bf93f0SYJwu2023 32878bf93f0SYJwu2023 /// Pci_Device_Structure_General_Device PCI标准设备结构体 32978bf93f0SYJwu2023 #[derive(Clone, Debug)] 33078bf93f0SYJwu2023 pub struct PciDeviceStructureGeneralDevice { 33178bf93f0SYJwu2023 pub common_header: PciDeviceStructureHeader, 33278bf93f0SYJwu2023 pub standard_device_bar: PciStandardDeviceBar, 33378bf93f0SYJwu2023 pub cardbus_cis_pointer: u32, // 指向卡信息结构,供在 CardBus 和 PCI 之间共享芯片的设备使用。 33478bf93f0SYJwu2023 pub subsystem_vendor_id: u16, 33578bf93f0SYJwu2023 pub subsystem_id: u16, 33678bf93f0SYJwu2023 pub expansion_rom_base_address: u32, 33778bf93f0SYJwu2023 pub capabilities_pointer: u8, 33878bf93f0SYJwu2023 pub reserved0: u8, 33978bf93f0SYJwu2023 pub reserved1: u16, 34078bf93f0SYJwu2023 pub reserved2: u32, 34178bf93f0SYJwu2023 pub interrupt_line: u8, // 指定设备的中断引脚连接到系统中断控制器的哪个输入,并由任何使用中断引脚的设备实现。对于 x86 架构,此寄存器对应于 PIC IRQ 编号 0-15(而不是 I/O APIC IRQ 编号),并且值0xFF定义为无连接。 34278bf93f0SYJwu2023 pub interrupt_pin: u8, // 指定设备使用的中断引脚。其中值为0x1INTA#、0x2INTB#、0x3INTC#、0x4INTD#,0x0表示设备不使用中断引脚。 34378bf93f0SYJwu2023 pub min_grant: u8, // 一个只读寄存器,用于指定设备所需的突发周期长度(以 1/4 微秒为单位)(假设时钟速率为 33 MHz) 34478bf93f0SYJwu2023 pub max_latency: u8, // 一个只读寄存器,指定设备需要多长时间访问一次 PCI 总线(以 1/4 微秒为单位)。 34578bf93f0SYJwu2023 } 34678bf93f0SYJwu2023 impl PciDeviceStructure for PciDeviceStructureGeneralDevice { 34778bf93f0SYJwu2023 fn header_type(&self) -> HeaderType { 34878bf93f0SYJwu2023 HeaderType::Standard 34978bf93f0SYJwu2023 } 35078bf93f0SYJwu2023 fn as_standard_device(&self) -> Option<&PciDeviceStructureGeneralDevice> { 35178bf93f0SYJwu2023 Some(self) 35278bf93f0SYJwu2023 } 35378bf93f0SYJwu2023 fn as_standard_device_mut(&mut self) -> Option<&mut PciDeviceStructureGeneralDevice> { 35478bf93f0SYJwu2023 Some(self) 35578bf93f0SYJwu2023 } 35678bf93f0SYJwu2023 fn common_header(&self) -> &PciDeviceStructureHeader { 35778bf93f0SYJwu2023 &self.common_header 35878bf93f0SYJwu2023 } 35978bf93f0SYJwu2023 36078bf93f0SYJwu2023 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 36178bf93f0SYJwu2023 &mut self.common_header 36278bf93f0SYJwu2023 } 36378bf93f0SYJwu2023 fn capabilities(&self) -> Option<CapabilityIterator> { 36478bf93f0SYJwu2023 Some(CapabilityIterator { 36578bf93f0SYJwu2023 bus_device_function: self.common_header.bus_device_function, 36678bf93f0SYJwu2023 next_capability_offset: Some(self.capabilities_pointer), 36778bf93f0SYJwu2023 }) 36878bf93f0SYJwu2023 } 36978bf93f0SYJwu2023 fn bar_init(&mut self) -> Option<Result<u8, PciError>> { 37078bf93f0SYJwu2023 let common_header = &self.common_header; 37178bf93f0SYJwu2023 match pci_bar_init(common_header.bus_device_function) { 37278bf93f0SYJwu2023 Ok(bar) => { 37378bf93f0SYJwu2023 self.standard_device_bar = bar; 37478bf93f0SYJwu2023 Some(Ok(0)) 37578bf93f0SYJwu2023 } 37678bf93f0SYJwu2023 Err(e) => Some(Err(e)), 37778bf93f0SYJwu2023 } 37878bf93f0SYJwu2023 } 37978bf93f0SYJwu2023 } 38078bf93f0SYJwu2023 /// Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci桥设备结构体 38178bf93f0SYJwu2023 #[derive(Clone, Debug)] 38278bf93f0SYJwu2023 pub struct PciDeviceStructurePciToPciBridge { 38378bf93f0SYJwu2023 pub common_header: PciDeviceStructureHeader, 38478bf93f0SYJwu2023 pub bar0: u32, 38578bf93f0SYJwu2023 pub bar1: u32, 38678bf93f0SYJwu2023 pub primary_bus_number: u8, 38778bf93f0SYJwu2023 pub secondary_bus_number: u8, 38878bf93f0SYJwu2023 pub subordinate_bus_number: u8, 38978bf93f0SYJwu2023 pub secondary_latency_timer: u8, 39078bf93f0SYJwu2023 pub io_base: u8, 39178bf93f0SYJwu2023 pub io_limit: u8, 39278bf93f0SYJwu2023 pub secondary_status: u16, 39378bf93f0SYJwu2023 pub memory_base: u16, 39478bf93f0SYJwu2023 pub memory_limit: u16, 39578bf93f0SYJwu2023 pub prefetchable_memory_base: u16, 39678bf93f0SYJwu2023 pub prefetchable_memory_limit: u16, 39778bf93f0SYJwu2023 pub prefetchable_base_upper_32_bits: u32, 39878bf93f0SYJwu2023 pub prefetchable_limit_upper_32_bits: u32, 39978bf93f0SYJwu2023 pub io_base_upper_16_bits: u16, 40078bf93f0SYJwu2023 pub io_limit_upper_16_bits: u16, 40178bf93f0SYJwu2023 pub capability_pointer: u8, 40278bf93f0SYJwu2023 pub reserved0: u8, 40378bf93f0SYJwu2023 pub reserved1: u16, 40478bf93f0SYJwu2023 pub expansion_rom_base_address: u32, 40578bf93f0SYJwu2023 pub interrupt_line: u8, 40678bf93f0SYJwu2023 pub interrupt_pin: u8, 40778bf93f0SYJwu2023 pub bridge_control: u16, 40878bf93f0SYJwu2023 } 40978bf93f0SYJwu2023 impl PciDeviceStructure for PciDeviceStructurePciToPciBridge { 41078bf93f0SYJwu2023 fn header_type(&self) -> HeaderType { 41178bf93f0SYJwu2023 HeaderType::PciPciBridge 41278bf93f0SYJwu2023 } 41378bf93f0SYJwu2023 fn as_pci_to_pci_bridge_device(&self) -> Option<&PciDeviceStructurePciToPciBridge> { 41478bf93f0SYJwu2023 Some(self) 41578bf93f0SYJwu2023 } 41678bf93f0SYJwu2023 fn as_pci_to_pci_bridge_device_mut(&mut self) -> Option<&mut PciDeviceStructurePciToPciBridge> { 41778bf93f0SYJwu2023 Some(self) 41878bf93f0SYJwu2023 } 41978bf93f0SYJwu2023 fn common_header(&self) -> &PciDeviceStructureHeader { 42078bf93f0SYJwu2023 &self.common_header 42178bf93f0SYJwu2023 } 42278bf93f0SYJwu2023 42378bf93f0SYJwu2023 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 42478bf93f0SYJwu2023 &mut self.common_header 42578bf93f0SYJwu2023 } 42678bf93f0SYJwu2023 } 42778bf93f0SYJwu2023 /// Pci_Device_Structure_Pci_to_Cardbus_Bridge Pci_to_Cardbus桥设备结构体 42878bf93f0SYJwu2023 #[derive(Clone, Debug)] 42978bf93f0SYJwu2023 pub struct PciDeviceStructurePciToCardbusBridge { 43078bf93f0SYJwu2023 pub common_header: PciDeviceStructureHeader, 43178bf93f0SYJwu2023 pub cardbus_socket_ex_ca_base_address: u32, 43278bf93f0SYJwu2023 pub offset_of_capabilities_list: u8, 43378bf93f0SYJwu2023 pub reserved: u8, 43478bf93f0SYJwu2023 pub secondary_status: u16, 43578bf93f0SYJwu2023 pub pci_bus_number: u8, 43678bf93f0SYJwu2023 pub card_bus_bus_number: u8, 43778bf93f0SYJwu2023 pub subordinate_bus_number: u8, 43878bf93f0SYJwu2023 pub card_bus_latency_timer: u8, 43978bf93f0SYJwu2023 pub memory_base_address0: u32, 44078bf93f0SYJwu2023 pub memory_limit0: u32, 44178bf93f0SYJwu2023 pub memory_base_address1: u32, 44278bf93f0SYJwu2023 pub memory_limit1: u32, 44378bf93f0SYJwu2023 pub io_base_address0: u32, 44478bf93f0SYJwu2023 pub io_limit0: u32, 44578bf93f0SYJwu2023 pub io_base_address1: u32, 44678bf93f0SYJwu2023 pub io_limit1: u32, 44778bf93f0SYJwu2023 pub interrupt_line: u8, 44878bf93f0SYJwu2023 pub interrupt_pin: u8, 44978bf93f0SYJwu2023 pub bridge_control: u16, 45078bf93f0SYJwu2023 pub subsystem_device_id: u16, 45178bf93f0SYJwu2023 pub subsystem_vendor_id: u16, 45278bf93f0SYJwu2023 pub pc_card_legacy_mode_base_address_16_bit: u32, 45378bf93f0SYJwu2023 } 45478bf93f0SYJwu2023 impl PciDeviceStructure for PciDeviceStructurePciToCardbusBridge { 45578bf93f0SYJwu2023 fn header_type(&self) -> HeaderType { 45678bf93f0SYJwu2023 HeaderType::PciCardbusBridge 45778bf93f0SYJwu2023 } 45878bf93f0SYJwu2023 fn as_pci_to_carbus_bridge_device(&self) -> Option<&PciDeviceStructurePciToCardbusBridge> { 45978bf93f0SYJwu2023 Some(&self) 46078bf93f0SYJwu2023 } 46178bf93f0SYJwu2023 fn as_pci_to_carbus_bridge_device_mut( 46278bf93f0SYJwu2023 &mut self, 46378bf93f0SYJwu2023 ) -> Option<&mut PciDeviceStructurePciToCardbusBridge> { 46478bf93f0SYJwu2023 Some(self) 46578bf93f0SYJwu2023 } 46678bf93f0SYJwu2023 fn common_header(&self) -> &PciDeviceStructureHeader { 46778bf93f0SYJwu2023 &self.common_header 46878bf93f0SYJwu2023 } 46978bf93f0SYJwu2023 47078bf93f0SYJwu2023 fn common_header_mut(&mut self) -> &mut PciDeviceStructureHeader { 47178bf93f0SYJwu2023 &mut self.common_header 47278bf93f0SYJwu2023 } 47378bf93f0SYJwu2023 } 47478bf93f0SYJwu2023 47578bf93f0SYJwu2023 /// 代表一个PCI segement greoup. 47678bf93f0SYJwu2023 #[derive(Copy, Clone, Debug, PartialEq)] 47778bf93f0SYJwu2023 pub struct PciRoot { 47878bf93f0SYJwu2023 pub physical_address_base: u64, //物理地址,acpi获取 47978bf93f0SYJwu2023 pub mmio_base: Option<*mut u32>, //映射后的虚拟地址,为方便访问数据这里转化成指针 48078bf93f0SYJwu2023 pub segement_group_number: SegmentGroupNumber, //segement greoup的id 48178bf93f0SYJwu2023 pub bus_begin: u8, //该分组中的最小bus 48278bf93f0SYJwu2023 pub bus_end: u8, //该分组中的最大bus 48378bf93f0SYJwu2023 } 48478bf93f0SYJwu2023 ///线程间共享需要,该结构体只需要在初始化时写入数据,无需读写锁保证线程安全 48578bf93f0SYJwu2023 unsafe impl Send for PciRoot {} 48678bf93f0SYJwu2023 unsafe impl Sync for PciRoot {} 48778bf93f0SYJwu2023 ///实现PciRoot的Display trait,自定义输出 48878bf93f0SYJwu2023 impl Display for PciRoot { 48978bf93f0SYJwu2023 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 49078bf93f0SYJwu2023 write!( 49178bf93f0SYJwu2023 f, 49278bf93f0SYJwu2023 "PCI Root with segement:{}, bus begin at {}, bus end at {}, physical address at {},mapped at {:#x}", 49378bf93f0SYJwu2023 self.segement_group_number, self.bus_begin, self.bus_end, self.physical_address_base, self.mmio_base.unwrap() as usize 49478bf93f0SYJwu2023 ) 49578bf93f0SYJwu2023 } 49678bf93f0SYJwu2023 } 49778bf93f0SYJwu2023 49878bf93f0SYJwu2023 impl PciRoot { 49978bf93f0SYJwu2023 /// @brief 初始化结构体,获取ecam root所在物理地址后map到虚拟地址,再将该虚拟地址加入mmio_base变量 50078bf93f0SYJwu2023 /// @return 成功返回结果,错误返回错误类型 50178bf93f0SYJwu2023 pub fn new(segment_group_number: SegmentGroupNumber) -> Result<Self, PciError> { 50278bf93f0SYJwu2023 let mut pci_root = PciArch::ecam_root(segment_group_number)?; 50378bf93f0SYJwu2023 pci_root.map()?; 50478bf93f0SYJwu2023 Ok(pci_root) 50578bf93f0SYJwu2023 } 50678bf93f0SYJwu2023 /// @brief 完成物理地址到虚拟地址的映射,并将虚拟地址加入mmio_base变量 50778bf93f0SYJwu2023 /// @return 返回错误或Ok(0) 50878bf93f0SYJwu2023 fn map(&mut self) -> Result<u8, PciError> { 50978bf93f0SYJwu2023 let bus_number = self.bus_end - self.bus_begin + 1; 51078bf93f0SYJwu2023 let bus_number_double = (bus_number + 1) / 2; 51178bf93f0SYJwu2023 let mut virtaddress: u64 = 0; 51278bf93f0SYJwu2023 let vaddr_ptr = &mut virtaddress as *mut u64; 51378bf93f0SYJwu2023 let mut virtsize: u64 = 0; 51478bf93f0SYJwu2023 let virtsize_ptr = &mut virtsize as *mut u64; 51578bf93f0SYJwu2023 let size = bus_number_double as u32 * PAGE_2M_SIZE; 51678bf93f0SYJwu2023 unsafe { 51778bf93f0SYJwu2023 let initial_mm_ptr = &mut initial_mm as *mut mm_struct; 51878bf93f0SYJwu2023 if let Err(_) = 51978bf93f0SYJwu2023 MMIO_POOL.create_mmio(size, (VM_IO | VM_DONTCOPY) as u64, vaddr_ptr, virtsize_ptr) 52078bf93f0SYJwu2023 { 52178bf93f0SYJwu2023 kerror!("Create mmio failed when initing ecam"); 52278bf93f0SYJwu2023 return Err(PciError::CreateMmioError); 52378bf93f0SYJwu2023 }; 52478bf93f0SYJwu2023 //kdebug!("virtaddress={:#x},virtsize={:#x}",virtaddress,virtsize); 52578bf93f0SYJwu2023 mm_map( 52678bf93f0SYJwu2023 initial_mm_ptr, 52778bf93f0SYJwu2023 virtaddress, 52878bf93f0SYJwu2023 size as u64, 52978bf93f0SYJwu2023 self.physical_address_base, 53078bf93f0SYJwu2023 ); 53178bf93f0SYJwu2023 } 53278bf93f0SYJwu2023 self.mmio_base = Some(virtaddress as *mut u32); 53378bf93f0SYJwu2023 Ok(0) 53478bf93f0SYJwu2023 } 53578bf93f0SYJwu2023 /// @brief 获得要操作的寄存器相对于mmio_offset的偏移量 53678bf93f0SYJwu2023 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 53778bf93f0SYJwu2023 /// @param register_offset 寄存器在设备中的offset 53878bf93f0SYJwu2023 /// @return u32 要操作的寄存器相对于mmio_offset的偏移量 53978bf93f0SYJwu2023 fn cam_offset(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 54078bf93f0SYJwu2023 assert!(bus_device_function.valid()); 54178bf93f0SYJwu2023 let bdf = ((bus_device_function.bus - self.bus_begin) as u32) << 8 54278bf93f0SYJwu2023 | (bus_device_function.device as u32) << 3 54378bf93f0SYJwu2023 | bus_device_function.function as u32; 54478bf93f0SYJwu2023 let address = bdf << 12 | register_offset as u32; 54578bf93f0SYJwu2023 // Ensure that address is word-aligned. 54678bf93f0SYJwu2023 assert!(address & 0x3 == 0); 54778bf93f0SYJwu2023 address 54878bf93f0SYJwu2023 } 54978bf93f0SYJwu2023 /// @brief 通过bus_device_function和offset读取相应位置寄存器的值(32位) 55078bf93f0SYJwu2023 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 55178bf93f0SYJwu2023 /// @param register_offset 寄存器在设备中的offset 55278bf93f0SYJwu2023 /// @return u32 寄存器读值结果 553*13776c11Slogin pub fn read_config(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 { 55478bf93f0SYJwu2023 let address = self.cam_offset(bus_device_function, register_offset); 55578bf93f0SYJwu2023 unsafe { 55678bf93f0SYJwu2023 // Right shift to convert from byte offset to word offset. 55778bf93f0SYJwu2023 (self.mmio_base.unwrap().add((address >> 2) as usize)).read_volatile() 55878bf93f0SYJwu2023 } 55978bf93f0SYJwu2023 } 56078bf93f0SYJwu2023 56178bf93f0SYJwu2023 /// @brief 通过bus_device_function和offset写入相应位置寄存器值(32位) 56278bf93f0SYJwu2023 /// @param bus_device_function 在同一个group中pci设备的唯一标识符 56378bf93f0SYJwu2023 /// @param register_offset 寄存器在设备中的offset 56478bf93f0SYJwu2023 /// @param data 要写入的值 56578bf93f0SYJwu2023 pub fn write_config( 56678bf93f0SYJwu2023 &mut self, 56778bf93f0SYJwu2023 bus_device_function: BusDeviceFunction, 56878bf93f0SYJwu2023 register_offset: u16, 56978bf93f0SYJwu2023 data: u32, 57078bf93f0SYJwu2023 ) { 57178bf93f0SYJwu2023 let address = self.cam_offset(bus_device_function, register_offset); 57278bf93f0SYJwu2023 // Safe because both the `mmio_base` and the address offset are properly aligned, and the 57378bf93f0SYJwu2023 // resulting pointer is within the MMIO range of the CAM. 57478bf93f0SYJwu2023 unsafe { 57578bf93f0SYJwu2023 // Right shift to convert from byte offset to word offset. 57678bf93f0SYJwu2023 (self.mmio_base.unwrap().add((address >> 2) as usize)).write_volatile(data) 57778bf93f0SYJwu2023 } 57878bf93f0SYJwu2023 } 57978bf93f0SYJwu2023 /// @brief 返回迭代器,遍历pcie设备的external_capabilities 58078bf93f0SYJwu2023 pub fn external_capabilities( 58178bf93f0SYJwu2023 &self, 58278bf93f0SYJwu2023 bus_device_function: BusDeviceFunction, 58378bf93f0SYJwu2023 ) -> ExternalCapabilityIterator { 58478bf93f0SYJwu2023 ExternalCapabilityIterator { 58578bf93f0SYJwu2023 root: self, 58678bf93f0SYJwu2023 bus_device_function, 58778bf93f0SYJwu2023 next_capability_offset: Some(0x100), 58878bf93f0SYJwu2023 } 58978bf93f0SYJwu2023 } 59078bf93f0SYJwu2023 } 59126d84a31SYJwu2023 /// Gets the capabilities 'pointer' for the device function, if any. 59226d84a31SYJwu2023 /// @brief 获取第一个capability 的offset 59378bf93f0SYJwu2023 /// @param bus_device_function PCI设备的唯一标识 59426d84a31SYJwu2023 /// @return Option<u8> offset 59578bf93f0SYJwu2023 pub fn capabilities_offset(bus_device_function: BusDeviceFunction) -> Option<u8> { 59678bf93f0SYJwu2023 let result = PciArch::read_config(&bus_device_function, STATUS_COMMAND_OFFSET); 59778bf93f0SYJwu2023 let status: Status = Status::from_bits_truncate((result >> 16) as u16); 59826d84a31SYJwu2023 if status.contains(Status::CAPABILITIES_LIST) { 59978bf93f0SYJwu2023 let cap_pointer = PciArch::read_config(&bus_device_function, 0x34) as u8 & 0xFC; 60026d84a31SYJwu2023 Some(cap_pointer) 60126d84a31SYJwu2023 } else { 60226d84a31SYJwu2023 None 60326d84a31SYJwu2023 } 60426d84a31SYJwu2023 } 60578bf93f0SYJwu2023 60678bf93f0SYJwu2023 /// @brief 读取pci设备头部 60778bf93f0SYJwu2023 /// @param bus_device_function PCI设备的唯一标识 60878bf93f0SYJwu2023 /// @param add_to_list 是否添加到链表 60978bf93f0SYJwu2023 /// @return 返回的header(trait 类型) 61078bf93f0SYJwu2023 fn pci_read_header( 61178bf93f0SYJwu2023 bus_device_function: BusDeviceFunction, 61278bf93f0SYJwu2023 add_to_list: bool, 61378bf93f0SYJwu2023 ) -> Result<Box<dyn PciDeviceStructure>, PciError> { 61478bf93f0SYJwu2023 // 先读取公共header 61578bf93f0SYJwu2023 let result = PciArch::read_config(&bus_device_function, 0x00); 61678bf93f0SYJwu2023 let vendor_id = result as u16; 61778bf93f0SYJwu2023 let device_id = (result >> 16) as u16; 61878bf93f0SYJwu2023 61978bf93f0SYJwu2023 let result = PciArch::read_config(&bus_device_function, 0x04); 62078bf93f0SYJwu2023 let command = result as u16; 62178bf93f0SYJwu2023 let status = (result >> 16) as u16; 62278bf93f0SYJwu2023 62378bf93f0SYJwu2023 let result = PciArch::read_config(&bus_device_function, 0x08); 62478bf93f0SYJwu2023 let revision_id = result as u8; 62578bf93f0SYJwu2023 let prog_if = (result >> 8) as u8; 62678bf93f0SYJwu2023 let subclass = (result >> 16) as u8; 62778bf93f0SYJwu2023 let class_code = (result >> 24) as u8; 62878bf93f0SYJwu2023 62978bf93f0SYJwu2023 let result = PciArch::read_config(&bus_device_function, 0x0c); 63078bf93f0SYJwu2023 let cache_line_size = result as u8; 63178bf93f0SYJwu2023 let latency_timer = (result >> 8) as u8; 63278bf93f0SYJwu2023 let header_type = (result >> 16) as u8; 63378bf93f0SYJwu2023 let bist = (result >> 24) as u8; 63478bf93f0SYJwu2023 if vendor_id == 0xffff { 63578bf93f0SYJwu2023 return Err(PciError::GetWrongHeader); 63678bf93f0SYJwu2023 } 63778bf93f0SYJwu2023 let header = PciDeviceStructureHeader { 63878bf93f0SYJwu2023 msix_mmio_vaddr: 0, 63978bf93f0SYJwu2023 msix_mmio_size: 0, 64078bf93f0SYJwu2023 msix_offset: 0, 64178bf93f0SYJwu2023 msix_table_size: 0, 64278bf93f0SYJwu2023 bus_device_function, 64378bf93f0SYJwu2023 vendor_id, 64478bf93f0SYJwu2023 device_id, 64578bf93f0SYJwu2023 command, 64678bf93f0SYJwu2023 status, 64778bf93f0SYJwu2023 revision_id, 64878bf93f0SYJwu2023 prog_if, 64978bf93f0SYJwu2023 subclass, 65078bf93f0SYJwu2023 class_code, 65178bf93f0SYJwu2023 cache_line_size, 65278bf93f0SYJwu2023 latency_timer, 65378bf93f0SYJwu2023 header_type, 65478bf93f0SYJwu2023 bist, 65578bf93f0SYJwu2023 }; 65678bf93f0SYJwu2023 match HeaderType::from(header_type & 0x7f) { 65778bf93f0SYJwu2023 HeaderType::Standard => { 65878bf93f0SYJwu2023 let general_device = pci_read_general_device_header(header, &bus_device_function); 65978bf93f0SYJwu2023 let box_general_device = Box::new(general_device); 66078bf93f0SYJwu2023 let box_general_device_clone = box_general_device.clone(); 66178bf93f0SYJwu2023 if add_to_list { 66278bf93f0SYJwu2023 PCI_DEVICE_LINKEDLIST.add(box_general_device); 66378bf93f0SYJwu2023 } 66478bf93f0SYJwu2023 Ok(box_general_device_clone) 66578bf93f0SYJwu2023 } 66678bf93f0SYJwu2023 HeaderType::PciPciBridge => { 66778bf93f0SYJwu2023 let pci_to_pci_bridge = pci_read_pci_to_pci_bridge_header(header, &bus_device_function); 66878bf93f0SYJwu2023 let box_pci_to_pci_bridge = Box::new(pci_to_pci_bridge); 66978bf93f0SYJwu2023 let box_pci_to_pci_bridge_clone = box_pci_to_pci_bridge.clone(); 67078bf93f0SYJwu2023 if add_to_list { 67178bf93f0SYJwu2023 PCI_DEVICE_LINKEDLIST.add(box_pci_to_pci_bridge); 67278bf93f0SYJwu2023 } 67378bf93f0SYJwu2023 Ok(box_pci_to_pci_bridge_clone) 67478bf93f0SYJwu2023 } 67578bf93f0SYJwu2023 HeaderType::PciCardbusBridge => { 67678bf93f0SYJwu2023 let pci_cardbus_bridge = 67778bf93f0SYJwu2023 pci_read_pci_to_cardbus_bridge_header(header, &bus_device_function); 67878bf93f0SYJwu2023 let box_pci_cardbus_bridge = Box::new(pci_cardbus_bridge); 67978bf93f0SYJwu2023 let box_pci_cardbus_bridge_clone = box_pci_cardbus_bridge.clone(); 68078bf93f0SYJwu2023 if add_to_list { 68178bf93f0SYJwu2023 PCI_DEVICE_LINKEDLIST.add(box_pci_cardbus_bridge); 68278bf93f0SYJwu2023 } 68378bf93f0SYJwu2023 Ok(box_pci_cardbus_bridge_clone) 68478bf93f0SYJwu2023 } 68578bf93f0SYJwu2023 HeaderType::Unrecognised(_) => Err(PciError::UnrecognisedHeaderType), 68678bf93f0SYJwu2023 } 68778bf93f0SYJwu2023 } 68878bf93f0SYJwu2023 68978bf93f0SYJwu2023 /// @brief 读取type为0x0的pci设备的header 69078bf93f0SYJwu2023 /// 本函数只应被 pci_read_header()调用 69178bf93f0SYJwu2023 /// @param common_header 共有头部 69278bf93f0SYJwu2023 /// @param bus_device_function PCI设备的唯一标识 69378bf93f0SYJwu2023 /// @return Pci_Device_Structure_General_Device 标准设备头部 69478bf93f0SYJwu2023 fn pci_read_general_device_header( 69578bf93f0SYJwu2023 common_header: PciDeviceStructureHeader, 69678bf93f0SYJwu2023 bus_device_function: &BusDeviceFunction, 69778bf93f0SYJwu2023 ) -> PciDeviceStructureGeneralDevice { 69878bf93f0SYJwu2023 let standard_device_bar = PciStandardDeviceBar::default(); 69978bf93f0SYJwu2023 let cardbus_cis_pointer = PciArch::read_config(bus_device_function, 0x28); 70078bf93f0SYJwu2023 70178bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x2c); 70278bf93f0SYJwu2023 let subsystem_vendor_id = result as u16; 70378bf93f0SYJwu2023 let subsystem_id = (result >> 16) as u16; 70478bf93f0SYJwu2023 70578bf93f0SYJwu2023 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x30); 70678bf93f0SYJwu2023 70778bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x34); 70878bf93f0SYJwu2023 let capabilities_pointer = result as u8; 70978bf93f0SYJwu2023 let reserved0 = (result >> 8) as u8; 71078bf93f0SYJwu2023 let reserved1 = (result >> 16) as u16; 71178bf93f0SYJwu2023 71278bf93f0SYJwu2023 let reserved2 = PciArch::read_config(bus_device_function, 0x38); 71378bf93f0SYJwu2023 71478bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x3c); 71578bf93f0SYJwu2023 let interrupt_line = result as u8; 71678bf93f0SYJwu2023 let interrupt_pin = (result >> 8) as u8; 71778bf93f0SYJwu2023 let min_grant = (result >> 16) as u8; 71878bf93f0SYJwu2023 let max_latency = (result >> 24) as u8; 71978bf93f0SYJwu2023 PciDeviceStructureGeneralDevice { 72078bf93f0SYJwu2023 common_header, 72178bf93f0SYJwu2023 standard_device_bar, 72278bf93f0SYJwu2023 cardbus_cis_pointer, 72378bf93f0SYJwu2023 subsystem_vendor_id, 72478bf93f0SYJwu2023 subsystem_id, 72578bf93f0SYJwu2023 expansion_rom_base_address, 72678bf93f0SYJwu2023 capabilities_pointer, 72778bf93f0SYJwu2023 reserved0, 72878bf93f0SYJwu2023 reserved1, 72978bf93f0SYJwu2023 reserved2, 73078bf93f0SYJwu2023 interrupt_line, 73178bf93f0SYJwu2023 interrupt_pin, 73278bf93f0SYJwu2023 min_grant, 73378bf93f0SYJwu2023 max_latency, 73478bf93f0SYJwu2023 } 73578bf93f0SYJwu2023 } 73678bf93f0SYJwu2023 73778bf93f0SYJwu2023 /// @brief 读取type为0x1的pci设备的header 73878bf93f0SYJwu2023 /// 本函数只应被 pci_read_header()调用 73978bf93f0SYJwu2023 /// @param common_header 共有头部 74078bf93f0SYJwu2023 /// @param bus_device_function PCI设备的唯一标识 74178bf93f0SYJwu2023 /// @return Pci_Device_Structure_Pci_to_Pci_Bridge pci-to-pci 桥设备头部 74278bf93f0SYJwu2023 fn pci_read_pci_to_pci_bridge_header( 74378bf93f0SYJwu2023 common_header: PciDeviceStructureHeader, 74478bf93f0SYJwu2023 bus_device_function: &BusDeviceFunction, 74578bf93f0SYJwu2023 ) -> PciDeviceStructurePciToPciBridge { 74678bf93f0SYJwu2023 let bar0 = PciArch::read_config(bus_device_function, 0x10); 74778bf93f0SYJwu2023 let bar1 = PciArch::read_config(bus_device_function, 0x14); 74878bf93f0SYJwu2023 74978bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x18); 75078bf93f0SYJwu2023 75178bf93f0SYJwu2023 let primary_bus_number = result as u8; 75278bf93f0SYJwu2023 let secondary_bus_number = (result >> 8) as u8; 75378bf93f0SYJwu2023 let subordinate_bus_number = (result >> 16) as u8; 75478bf93f0SYJwu2023 let secondary_latency_timer = (result >> 24) as u8; 75578bf93f0SYJwu2023 75678bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x1c); 75778bf93f0SYJwu2023 let io_base = result as u8; 75878bf93f0SYJwu2023 let io_limit = (result >> 8) as u8; 75978bf93f0SYJwu2023 let secondary_status = (result >> 16) as u16; 76078bf93f0SYJwu2023 76178bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x20); 76278bf93f0SYJwu2023 let memory_base = result as u16; 76378bf93f0SYJwu2023 let memory_limit = (result >> 16) as u16; 76478bf93f0SYJwu2023 76578bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x24); 76678bf93f0SYJwu2023 let prefetchable_memory_base = result as u16; 76778bf93f0SYJwu2023 let prefetchable_memory_limit = (result >> 16) as u16; 76878bf93f0SYJwu2023 76978bf93f0SYJwu2023 let prefetchable_base_upper_32_bits = PciArch::read_config(bus_device_function, 0x28); 77078bf93f0SYJwu2023 let prefetchable_limit_upper_32_bits = PciArch::read_config(bus_device_function, 0x2c); 77178bf93f0SYJwu2023 77278bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x30); 77378bf93f0SYJwu2023 let io_base_upper_16_bits = result as u16; 77478bf93f0SYJwu2023 let io_limit_upper_16_bits = (result >> 16) as u16; 77578bf93f0SYJwu2023 77678bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x34); 77778bf93f0SYJwu2023 let capability_pointer = result as u8; 77878bf93f0SYJwu2023 let reserved0 = (result >> 8) as u8; 77978bf93f0SYJwu2023 let reserved1 = (result >> 16) as u16; 78078bf93f0SYJwu2023 78178bf93f0SYJwu2023 let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x38); 78278bf93f0SYJwu2023 78378bf93f0SYJwu2023 let result = PciArch::read_config(bus_device_function, 0x3c); 78478bf93f0SYJwu2023 let interrupt_line = result as u8; 78578bf93f0SYJwu2023 let interrupt_pin = (result >> 8) as u8; 78678bf93f0SYJwu2023 let bridge_control = (result >> 16) as u16; 78778bf93f0SYJwu2023 PciDeviceStructurePciToPciBridge { 78878bf93f0SYJwu2023 common_header, 78978bf93f0SYJwu2023 bar0, 79078bf93f0SYJwu2023 bar1, 79178bf93f0SYJwu2023 primary_bus_number, 79278bf93f0SYJwu2023 secondary_bus_number, 79378bf93f0SYJwu2023 subordinate_bus_number, 79478bf93f0SYJwu2023 secondary_latency_timer, 79578bf93f0SYJwu2023 io_base, 79678bf93f0SYJwu2023 io_limit, 79778bf93f0SYJwu2023 secondary_status, 79878bf93f0SYJwu2023 memory_base, 79978bf93f0SYJwu2023 memory_limit, 80078bf93f0SYJwu2023 prefetchable_memory_base, 80178bf93f0SYJwu2023 prefetchable_memory_limit, 80278bf93f0SYJwu2023 prefetchable_base_upper_32_bits, 80378bf93f0SYJwu2023 prefetchable_limit_upper_32_bits, 80478bf93f0SYJwu2023 io_base_upper_16_bits, 80578bf93f0SYJwu2023 io_limit_upper_16_bits, 80678bf93f0SYJwu2023 capability_pointer, 80778bf93f0SYJwu2023 reserved0, 80878bf93f0SYJwu2023 reserved1, 80978bf93f0SYJwu2023 expansion_rom_base_address, 81078bf93f0SYJwu2023 interrupt_line, 81178bf93f0SYJwu2023 interrupt_pin, 81278bf93f0SYJwu2023 bridge_control, 81378bf93f0SYJwu2023 } 81478bf93f0SYJwu2023 } 81578bf93f0SYJwu2023 81678bf93f0SYJwu2023 /// @brief 读取type为0x2的pci设备的header 81778bf93f0SYJwu2023 /// 本函数只应被 pci_read_header()调用 81878bf93f0SYJwu2023 /// @param common_header 共有头部 81978bf93f0SYJwu2023 /// @param bus_device_function PCI设备的唯一标识 82078bf93f0SYJwu2023 /// @return ) -> Pci_Device_Structure_Pci_to_Cardbus_Bridge pci-to-cardbus 桥设备头部 82178bf93f0SYJwu2023 fn pci_read_pci_to_cardbus_bridge_header( 82278bf93f0SYJwu2023 common_header: PciDeviceStructureHeader, 82378bf93f0SYJwu2023 busdevicefunction: &BusDeviceFunction, 82478bf93f0SYJwu2023 ) -> PciDeviceStructurePciToCardbusBridge { 82578bf93f0SYJwu2023 let cardbus_socket_ex_ca_base_address = PciArch::read_config(busdevicefunction, 0x10); 82678bf93f0SYJwu2023 82778bf93f0SYJwu2023 let result = PciArch::read_config(busdevicefunction, 0x14); 82878bf93f0SYJwu2023 let offset_of_capabilities_list = result as u8; 82978bf93f0SYJwu2023 let reserved = (result >> 8) as u8; 83078bf93f0SYJwu2023 let secondary_status = (result >> 16) as u16; 83178bf93f0SYJwu2023 83278bf93f0SYJwu2023 let result = PciArch::read_config(busdevicefunction, 0x18); 83378bf93f0SYJwu2023 let pci_bus_number = result as u8; 83478bf93f0SYJwu2023 let card_bus_bus_number = (result >> 8) as u8; 83578bf93f0SYJwu2023 let subordinate_bus_number = (result >> 16) as u8; 83678bf93f0SYJwu2023 let card_bus_latency_timer = (result >> 24) as u8; 83778bf93f0SYJwu2023 83878bf93f0SYJwu2023 let memory_base_address0 = PciArch::read_config(busdevicefunction, 0x1c); 83978bf93f0SYJwu2023 let memory_limit0 = PciArch::read_config(busdevicefunction, 0x20); 84078bf93f0SYJwu2023 let memory_base_address1 = PciArch::read_config(busdevicefunction, 0x24); 84178bf93f0SYJwu2023 let memory_limit1 = PciArch::read_config(busdevicefunction, 0x28); 84278bf93f0SYJwu2023 84378bf93f0SYJwu2023 let io_base_address0 = PciArch::read_config(busdevicefunction, 0x2c); 84478bf93f0SYJwu2023 let io_limit0 = PciArch::read_config(busdevicefunction, 0x30); 84578bf93f0SYJwu2023 let io_base_address1 = PciArch::read_config(busdevicefunction, 0x34); 84678bf93f0SYJwu2023 let io_limit1 = PciArch::read_config(busdevicefunction, 0x38); 84778bf93f0SYJwu2023 let result = PciArch::read_config(busdevicefunction, 0x3c); 84878bf93f0SYJwu2023 let interrupt_line = result as u8; 84978bf93f0SYJwu2023 let interrupt_pin = (result >> 8) as u8; 85078bf93f0SYJwu2023 let bridge_control = (result >> 16) as u16; 85178bf93f0SYJwu2023 85278bf93f0SYJwu2023 let result = PciArch::read_config(busdevicefunction, 0x40); 85378bf93f0SYJwu2023 let subsystem_device_id = result as u16; 85478bf93f0SYJwu2023 let subsystem_vendor_id = (result >> 16) as u16; 85578bf93f0SYJwu2023 85678bf93f0SYJwu2023 let pc_card_legacy_mode_base_address_16_bit = PciArch::read_config(busdevicefunction, 0x44); 85778bf93f0SYJwu2023 PciDeviceStructurePciToCardbusBridge { 85878bf93f0SYJwu2023 common_header, 85978bf93f0SYJwu2023 cardbus_socket_ex_ca_base_address, 86078bf93f0SYJwu2023 offset_of_capabilities_list, 86178bf93f0SYJwu2023 reserved, 86278bf93f0SYJwu2023 secondary_status, 86378bf93f0SYJwu2023 pci_bus_number, 86478bf93f0SYJwu2023 card_bus_bus_number, 86578bf93f0SYJwu2023 subordinate_bus_number, 86678bf93f0SYJwu2023 card_bus_latency_timer, 86778bf93f0SYJwu2023 memory_base_address0, 86878bf93f0SYJwu2023 memory_limit0, 86978bf93f0SYJwu2023 memory_base_address1, 87078bf93f0SYJwu2023 memory_limit1, 87178bf93f0SYJwu2023 io_base_address0, 87278bf93f0SYJwu2023 io_limit0, 87378bf93f0SYJwu2023 io_base_address1, 87478bf93f0SYJwu2023 io_limit1, 87578bf93f0SYJwu2023 interrupt_line, 87678bf93f0SYJwu2023 interrupt_pin, 87778bf93f0SYJwu2023 bridge_control, 87878bf93f0SYJwu2023 subsystem_device_id, 87978bf93f0SYJwu2023 subsystem_vendor_id, 88078bf93f0SYJwu2023 pc_card_legacy_mode_base_address_16_bit, 88178bf93f0SYJwu2023 } 88278bf93f0SYJwu2023 } 88378bf93f0SYJwu2023 88478bf93f0SYJwu2023 /// @brief 检查所有bus上的设备并将其加入链表 88578bf93f0SYJwu2023 /// @return 成功返回ok(),失败返回失败原因 88678bf93f0SYJwu2023 fn pci_check_all_buses() -> Result<u8, PciError> { 88778bf93f0SYJwu2023 kinfo!("Checking all devices in PCI bus..."); 88878bf93f0SYJwu2023 let busdevicefunction = BusDeviceFunction { 88978bf93f0SYJwu2023 bus: 0, 89078bf93f0SYJwu2023 device: 0, 89178bf93f0SYJwu2023 function: 0, 89278bf93f0SYJwu2023 }; 89378bf93f0SYJwu2023 let header = pci_read_header(busdevicefunction, false)?; 89478bf93f0SYJwu2023 let common_header = header.common_header(); 89578bf93f0SYJwu2023 pci_check_bus(0)?; 89678bf93f0SYJwu2023 if common_header.header_type & 0x80 != 0 { 89778bf93f0SYJwu2023 for function in 1..8 { 89878bf93f0SYJwu2023 pci_check_bus(function)?; 89978bf93f0SYJwu2023 } 90078bf93f0SYJwu2023 } 90178bf93f0SYJwu2023 Ok(0) 90278bf93f0SYJwu2023 } 90378bf93f0SYJwu2023 /// @brief 检查特定设备并将其加入链表 90478bf93f0SYJwu2023 /// @return 成功返回ok(),失败返回失败原因 90578bf93f0SYJwu2023 fn pci_check_function(busdevicefunction: BusDeviceFunction) -> Result<u8, PciError> { 90678bf93f0SYJwu2023 //kdebug!("PCI check function {}", busdevicefunction.function); 90778bf93f0SYJwu2023 let header = match pci_read_header(busdevicefunction, true) { 90878bf93f0SYJwu2023 Ok(header) => header, 90978bf93f0SYJwu2023 Err(PciError::GetWrongHeader) => { 91078bf93f0SYJwu2023 return Ok(255); 91178bf93f0SYJwu2023 } 91278bf93f0SYJwu2023 Err(e) => { 91378bf93f0SYJwu2023 return Err(e); 91478bf93f0SYJwu2023 } 91578bf93f0SYJwu2023 }; 91678bf93f0SYJwu2023 let common_header = header.common_header(); 91778bf93f0SYJwu2023 if (common_header.class_code == 0x06) 91878bf93f0SYJwu2023 && (common_header.subclass == 0x04 || common_header.subclass == 0x09) 91978bf93f0SYJwu2023 { 92078bf93f0SYJwu2023 let pci_to_pci_bridge = header 92178bf93f0SYJwu2023 .as_pci_to_pci_bridge_device() 92278bf93f0SYJwu2023 .ok_or(PciError::PciDeviceStructureTransformError)?; 92378bf93f0SYJwu2023 let secondary_bus = pci_to_pci_bridge.secondary_bus_number; 92478bf93f0SYJwu2023 pci_check_bus(secondary_bus)?; 92578bf93f0SYJwu2023 } 92678bf93f0SYJwu2023 Ok(0) 92778bf93f0SYJwu2023 } 92878bf93f0SYJwu2023 92978bf93f0SYJwu2023 /// @brief 检查device上的设备并将其加入链表 93078bf93f0SYJwu2023 /// @return 成功返回ok(),失败返回失败原因 93178bf93f0SYJwu2023 fn pci_check_device(bus: u8, device: u8) -> Result<u8, PciError> { 93278bf93f0SYJwu2023 //kdebug!("PCI check device {}", device); 93378bf93f0SYJwu2023 let busdevicefunction = BusDeviceFunction { 93478bf93f0SYJwu2023 bus, 93578bf93f0SYJwu2023 device, 93678bf93f0SYJwu2023 function: 0, 93778bf93f0SYJwu2023 }; 93878bf93f0SYJwu2023 let header = match pci_read_header(busdevicefunction, false) { 93978bf93f0SYJwu2023 Ok(header) => header, 94078bf93f0SYJwu2023 Err(PciError::GetWrongHeader) => { 94178bf93f0SYJwu2023 //设备不存在,直接返回即可,不用终止遍历 94278bf93f0SYJwu2023 return Ok(255); 94378bf93f0SYJwu2023 } 94478bf93f0SYJwu2023 Err(e) => { 94578bf93f0SYJwu2023 return Err(e); 94678bf93f0SYJwu2023 } 94778bf93f0SYJwu2023 }; 94878bf93f0SYJwu2023 pci_check_function(busdevicefunction)?; 94978bf93f0SYJwu2023 let common_header = header.common_header(); 95078bf93f0SYJwu2023 if common_header.header_type & 0x80 != 0 { 95178bf93f0SYJwu2023 kdebug!( 95278bf93f0SYJwu2023 "Detected multi func device in bus{},device{}", 95378bf93f0SYJwu2023 busdevicefunction.bus, 95478bf93f0SYJwu2023 busdevicefunction.device 95578bf93f0SYJwu2023 ); 95678bf93f0SYJwu2023 // 这是一个多function的设备,因此查询剩余的function 95778bf93f0SYJwu2023 for function in 1..8 { 95878bf93f0SYJwu2023 let busdevicefunction = BusDeviceFunction { 95978bf93f0SYJwu2023 bus, 96078bf93f0SYJwu2023 device, 96178bf93f0SYJwu2023 function, 96278bf93f0SYJwu2023 }; 96378bf93f0SYJwu2023 pci_check_function(busdevicefunction)?; 96478bf93f0SYJwu2023 } 96578bf93f0SYJwu2023 } 96678bf93f0SYJwu2023 Ok(0) 96778bf93f0SYJwu2023 } 96878bf93f0SYJwu2023 /// @brief 检查该bus上的设备并将其加入链表 96978bf93f0SYJwu2023 /// @return 成功返回ok(),失败返回失败原因 97078bf93f0SYJwu2023 fn pci_check_bus(bus: u8) -> Result<u8, PciError> { 97178bf93f0SYJwu2023 //kdebug!("PCI check bus {}", bus); 97278bf93f0SYJwu2023 for device in 0..32 { 97378bf93f0SYJwu2023 pci_check_device(bus, device)?; 97478bf93f0SYJwu2023 } 97578bf93f0SYJwu2023 Ok(0) 97678bf93f0SYJwu2023 } 97778bf93f0SYJwu2023 /// @brief pci初始化函数(for c) 97878bf93f0SYJwu2023 #[no_mangle] 97978bf93f0SYJwu2023 pub extern "C" fn rs_pci_init() { 98078bf93f0SYJwu2023 pci_init(); 98178bf93f0SYJwu2023 //kdebug!("{}",PCI_ROOT_0.unwrap()); 98278bf93f0SYJwu2023 } 98378bf93f0SYJwu2023 /// @brief pci初始化函数 98478bf93f0SYJwu2023 pub fn pci_init() { 98578bf93f0SYJwu2023 kinfo!("Initializing PCI bus..."); 98678bf93f0SYJwu2023 if let Err(e) = pci_check_all_buses() { 98778bf93f0SYJwu2023 kerror!("pci init failed when checking bus because of error: {}", e); 98878bf93f0SYJwu2023 return; 98978bf93f0SYJwu2023 } 99078bf93f0SYJwu2023 kinfo!( 99178bf93f0SYJwu2023 "Total pci device and function num = {}", 99278bf93f0SYJwu2023 PCI_DEVICE_LINKEDLIST.num() 99378bf93f0SYJwu2023 ); 99478bf93f0SYJwu2023 let list = PCI_DEVICE_LINKEDLIST.read(); 99578bf93f0SYJwu2023 for box_pci_device in list.iter() { 99678bf93f0SYJwu2023 let common_header = box_pci_device.common_header(); 99778bf93f0SYJwu2023 match box_pci_device.header_type() { 99878bf93f0SYJwu2023 HeaderType::Standard if common_header.status & 0x10 != 0 => { 99978bf93f0SYJwu2023 kinfo!("Found pci standard device with class code ={} subclass={} status={:#x} cap_pointer={:#x} vendor={:#x}, device id={:#x}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer,common_header.vendor_id, common_header.device_id); 100078bf93f0SYJwu2023 } 100178bf93f0SYJwu2023 HeaderType::Standard => { 100278bf93f0SYJwu2023 kinfo!( 100378bf93f0SYJwu2023 "Found pci standard device with class code ={} subclass={} status={:#x} ", 100478bf93f0SYJwu2023 common_header.class_code, 100578bf93f0SYJwu2023 common_header.subclass, 100678bf93f0SYJwu2023 common_header.status 100778bf93f0SYJwu2023 ); 100878bf93f0SYJwu2023 } 100978bf93f0SYJwu2023 HeaderType::PciPciBridge if common_header.status & 0x10 != 0 => { 101078bf93f0SYJwu2023 kinfo!("Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} cap_pointer={:#x}", common_header.class_code, common_header.subclass, common_header.status, box_pci_device.as_standard_device().unwrap().capabilities_pointer); 101178bf93f0SYJwu2023 } 101278bf93f0SYJwu2023 HeaderType::PciPciBridge => { 101378bf93f0SYJwu2023 kinfo!( 101478bf93f0SYJwu2023 "Found pci-to-pci bridge device with class code ={} subclass={} status={:#x} ", 101578bf93f0SYJwu2023 common_header.class_code, 101678bf93f0SYJwu2023 common_header.subclass, 101778bf93f0SYJwu2023 common_header.status 101878bf93f0SYJwu2023 ); 101978bf93f0SYJwu2023 } 102078bf93f0SYJwu2023 HeaderType::PciCardbusBridge => { 102178bf93f0SYJwu2023 kinfo!( 102278bf93f0SYJwu2023 "Found pcicardbus bridge device with class code ={} subclass={} status={:#x} ", 102378bf93f0SYJwu2023 common_header.class_code, 102478bf93f0SYJwu2023 common_header.subclass, 102578bf93f0SYJwu2023 common_header.status 102678bf93f0SYJwu2023 ); 102778bf93f0SYJwu2023 } 102878bf93f0SYJwu2023 HeaderType::Unrecognised(_) => {} 102978bf93f0SYJwu2023 } 103078bf93f0SYJwu2023 } 103178bf93f0SYJwu2023 kinfo!("PCI bus initialized."); 103278bf93f0SYJwu2023 } 103378bf93f0SYJwu2023 103426d84a31SYJwu2023 /// An identifier for a PCI bus, device and function. 103526d84a31SYJwu2023 /// PCI设备的唯一标识 103626d84a31SYJwu2023 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 103778bf93f0SYJwu2023 pub struct BusDeviceFunction { 103826d84a31SYJwu2023 /// The PCI bus number, between 0 and 255. 103926d84a31SYJwu2023 pub bus: u8, 104026d84a31SYJwu2023 /// The device number on the bus, between 0 and 31. 104126d84a31SYJwu2023 pub device: u8, 104226d84a31SYJwu2023 /// The function number of the device, between 0 and 7. 104326d84a31SYJwu2023 pub function: u8, 104426d84a31SYJwu2023 } 104578bf93f0SYJwu2023 impl BusDeviceFunction { 104626d84a31SYJwu2023 /// Returns whether the device and function numbers are valid, i.e. the device is between 0 and 104778bf93f0SYJwu2023 ///@brief 检测BusDeviceFunction实例是否有效 104826d84a31SYJwu2023 ///@param self 104926d84a31SYJwu2023 ///@return bool 是否有效 105073c607aaSYJwu2023 #[allow(dead_code)] 105126d84a31SYJwu2023 pub fn valid(&self) -> bool { 105226d84a31SYJwu2023 self.device < 32 && self.function < 8 105326d84a31SYJwu2023 } 105426d84a31SYJwu2023 } 105578bf93f0SYJwu2023 ///实现BusDeviceFunction的Display trait,使其可以直接输出 105678bf93f0SYJwu2023 impl Display for BusDeviceFunction { 105726d84a31SYJwu2023 fn fmt(&self, f: &mut Formatter) -> fmt::Result { 105826d84a31SYJwu2023 write!(f, "{:02x}:{:02x}.{}", self.bus, self.device, self.function) 105926d84a31SYJwu2023 } 106026d84a31SYJwu2023 } 106126d84a31SYJwu2023 /// The location allowed for a memory BAR. 106226d84a31SYJwu2023 /// memory BAR的三种情况 106326d84a31SYJwu2023 #[derive(Copy, Clone, Debug, Eq, PartialEq)] 106426d84a31SYJwu2023 pub enum MemoryBarType { 106526d84a31SYJwu2023 /// The BAR has a 32-bit address and can be mapped anywhere in 32-bit address space. 106626d84a31SYJwu2023 Width32, 106726d84a31SYJwu2023 /// The BAR must be mapped below 1MiB. 106826d84a31SYJwu2023 Below1MiB, 106926d84a31SYJwu2023 /// The BAR has a 64-bit address and can be mapped anywhere in 64-bit address space. 107026d84a31SYJwu2023 Width64, 107126d84a31SYJwu2023 } 107226d84a31SYJwu2023 ///实现MemoryBarType与u8的类型转换 107326d84a31SYJwu2023 impl From<MemoryBarType> for u8 { 107426d84a31SYJwu2023 fn from(bar_type: MemoryBarType) -> Self { 107526d84a31SYJwu2023 match bar_type { 107626d84a31SYJwu2023 MemoryBarType::Width32 => 0, 107726d84a31SYJwu2023 MemoryBarType::Below1MiB => 1, 107826d84a31SYJwu2023 MemoryBarType::Width64 => 2, 107926d84a31SYJwu2023 } 108026d84a31SYJwu2023 } 108126d84a31SYJwu2023 } 108226d84a31SYJwu2023 ///实现MemoryBarType与u8的类型转换 108326d84a31SYJwu2023 impl TryFrom<u8> for MemoryBarType { 108426d84a31SYJwu2023 type Error = PciError; 108526d84a31SYJwu2023 fn try_from(value: u8) -> Result<Self, Self::Error> { 108626d84a31SYJwu2023 match value { 108726d84a31SYJwu2023 0 => Ok(Self::Width32), 108826d84a31SYJwu2023 1 => Ok(Self::Below1MiB), 108926d84a31SYJwu2023 2 => Ok(Self::Width64), 109026d84a31SYJwu2023 _ => Err(PciError::InvalidBarType), 109126d84a31SYJwu2023 } 109226d84a31SYJwu2023 } 109326d84a31SYJwu2023 } 109426d84a31SYJwu2023 109526d84a31SYJwu2023 /// Information about a PCI Base Address Register. 109626d84a31SYJwu2023 /// BAR的三种类型 Memory/IO/Unused 109726d84a31SYJwu2023 #[derive(Clone, Debug, Eq, PartialEq)] 109826d84a31SYJwu2023 pub enum BarInfo { 109926d84a31SYJwu2023 /// The BAR is for a memory region. 110026d84a31SYJwu2023 Memory { 110126d84a31SYJwu2023 /// The size of the BAR address and where it can be located. 110226d84a31SYJwu2023 address_type: MemoryBarType, 110326d84a31SYJwu2023 /// If true, then reading from the region doesn't have side effects. The CPU may cache reads 110426d84a31SYJwu2023 /// and merge repeated stores. 110526d84a31SYJwu2023 prefetchable: bool, 110626d84a31SYJwu2023 /// The memory address, always 16-byte aligned. 110726d84a31SYJwu2023 address: u64, 110826d84a31SYJwu2023 /// The size of the BAR in bytes. 110926d84a31SYJwu2023 size: u32, 111026d84a31SYJwu2023 /// The virtaddress for a memory bar(mapped). 111126d84a31SYJwu2023 virtaddress: u64, 111226d84a31SYJwu2023 }, 111326d84a31SYJwu2023 /// The BAR is for an I/O region. 111426d84a31SYJwu2023 IO { 111526d84a31SYJwu2023 /// The I/O address, always 4-byte aligned. 111626d84a31SYJwu2023 address: u32, 111726d84a31SYJwu2023 /// The size of the BAR in bytes. 111826d84a31SYJwu2023 size: u32, 111926d84a31SYJwu2023 }, 112026d84a31SYJwu2023 Unused, 112126d84a31SYJwu2023 } 112226d84a31SYJwu2023 112326d84a31SYJwu2023 impl BarInfo { 112426d84a31SYJwu2023 /// Returns the address and size of this BAR if it is a memory bar, or `None` if it is an IO 112526d84a31SYJwu2023 /// BAR. 112626d84a31SYJwu2023 ///@brief 得到某个bar的memory_address与size(前提是他的类型为Memory Bar) 112726d84a31SYJwu2023 ///@param self 112826d84a31SYJwu2023 ///@return Option<(u64, u32) 是Memory Bar返回内存地址与大小,不是则返回None 112926d84a31SYJwu2023 pub fn memory_address_size(&self) -> Option<(u64, u32)> { 113026d84a31SYJwu2023 if let Self::Memory { address, size, .. } = self { 113126d84a31SYJwu2023 Some((*address, *size)) 113226d84a31SYJwu2023 } else { 113326d84a31SYJwu2023 None 113426d84a31SYJwu2023 } 113526d84a31SYJwu2023 } 113626d84a31SYJwu2023 ///@brief 得到某个bar的virtaddress(前提是他的类型为Memory Bar) 113726d84a31SYJwu2023 ///@param self 113826d84a31SYJwu2023 ///@return Option<(u64) 是Memory Bar返回映射的虚拟地址,不是则返回None 113926d84a31SYJwu2023 pub fn virtual_address(&self) -> Option<u64> { 114026d84a31SYJwu2023 if let Self::Memory { virtaddress, .. } = self { 114126d84a31SYJwu2023 Some(*virtaddress) 114226d84a31SYJwu2023 } else { 114326d84a31SYJwu2023 None 114426d84a31SYJwu2023 } 114526d84a31SYJwu2023 } 114626d84a31SYJwu2023 } 114778bf93f0SYJwu2023 ///实现BarInfo的Display trait,自定义输出 114826d84a31SYJwu2023 impl Display for BarInfo { 114926d84a31SYJwu2023 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 115026d84a31SYJwu2023 match self { 115126d84a31SYJwu2023 Self::Memory { 115226d84a31SYJwu2023 address_type, 115326d84a31SYJwu2023 prefetchable, 115426d84a31SYJwu2023 address, 115526d84a31SYJwu2023 size, 115626d84a31SYJwu2023 virtaddress, 115726d84a31SYJwu2023 } => write!( 115826d84a31SYJwu2023 f, 115926d84a31SYJwu2023 "Memory space at {:#010x}, size {}, type {:?}, prefetchable {},mapped at {:#x}", 116026d84a31SYJwu2023 address, size, address_type, prefetchable, virtaddress 116126d84a31SYJwu2023 ), 116226d84a31SYJwu2023 Self::IO { address, size } => { 116326d84a31SYJwu2023 write!(f, "I/O space at {:#010x}, size {}", address, size) 116426d84a31SYJwu2023 } 116526d84a31SYJwu2023 Self::Unused => { 116626d84a31SYJwu2023 write!(f, "Unused bar") 116726d84a31SYJwu2023 } 116826d84a31SYJwu2023 } 116926d84a31SYJwu2023 } 117026d84a31SYJwu2023 } 117178bf93f0SYJwu2023 ///一个普通PCI设备(非桥)有6个BAR寄存器,PciStandardDeviceBar存储其全部信息 117226d84a31SYJwu2023 #[derive(Clone, Debug, Eq, PartialEq)] 117378bf93f0SYJwu2023 pub struct PciStandardDeviceBar { 117426d84a31SYJwu2023 bar0: BarInfo, 117526d84a31SYJwu2023 bar1: BarInfo, 117626d84a31SYJwu2023 bar2: BarInfo, 117726d84a31SYJwu2023 bar3: BarInfo, 117826d84a31SYJwu2023 bar4: BarInfo, 117926d84a31SYJwu2023 bar5: BarInfo, 118026d84a31SYJwu2023 } 118126d84a31SYJwu2023 118278bf93f0SYJwu2023 impl PciStandardDeviceBar { 118326d84a31SYJwu2023 ///@brief 得到某个bar的barinfo 118426d84a31SYJwu2023 ///@param self ,bar_index(0-5) 118526d84a31SYJwu2023 ///@return Result<&BarInfo, PciError> bar_index在0-5则返回对应的bar_info结构体,超出范围则返回错误 118626d84a31SYJwu2023 pub fn get_bar(&self, bar_index: u8) -> Result<&BarInfo, PciError> { 118726d84a31SYJwu2023 match bar_index { 118826d84a31SYJwu2023 0 => Ok(&self.bar0), 118926d84a31SYJwu2023 1 => Ok(&self.bar1), 119026d84a31SYJwu2023 2 => Ok(&self.bar2), 119126d84a31SYJwu2023 3 => Ok(&self.bar3), 119226d84a31SYJwu2023 4 => Ok(&self.bar4), 119378bf93f0SYJwu2023 5 => Ok(&self.bar5), 119426d84a31SYJwu2023 _ => Err(PciError::InvalidBarType), 119526d84a31SYJwu2023 } 119626d84a31SYJwu2023 } 119726d84a31SYJwu2023 } 119878bf93f0SYJwu2023 ///实现PciStandardDeviceBar的Display trait,使其可以直接输出 119978bf93f0SYJwu2023 impl Display for PciStandardDeviceBar { 120026d84a31SYJwu2023 fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { 120126d84a31SYJwu2023 write!( 120226d84a31SYJwu2023 f, 120326d84a31SYJwu2023 "\r\nBar0:{}\r\n Bar1:{}\r\n Bar2:{}\r\n Bar3:{}\r\nBar4:{}\r\nBar5:{}", 120426d84a31SYJwu2023 self.bar0, self.bar1, self.bar2, self.bar3, self.bar4, self.bar5 120526d84a31SYJwu2023 ) 120626d84a31SYJwu2023 } 120726d84a31SYJwu2023 } 120878bf93f0SYJwu2023 ///实现PciStandardDeviceBar的Default trait,使其可以简单初始化 120978bf93f0SYJwu2023 impl Default for PciStandardDeviceBar { 121026d84a31SYJwu2023 fn default() -> Self { 121178bf93f0SYJwu2023 PciStandardDeviceBar { 121226d84a31SYJwu2023 bar0: BarInfo::Unused, 121326d84a31SYJwu2023 bar1: BarInfo::Unused, 121426d84a31SYJwu2023 bar2: BarInfo::Unused, 121526d84a31SYJwu2023 bar3: BarInfo::Unused, 121626d84a31SYJwu2023 bar4: BarInfo::Unused, 121726d84a31SYJwu2023 bar5: BarInfo::Unused, 121826d84a31SYJwu2023 } 121926d84a31SYJwu2023 } 122026d84a31SYJwu2023 } 122126d84a31SYJwu2023 122278bf93f0SYJwu2023 ///@brief 将某个pci设备的bar寄存器读取值后映射到虚拟地址 122378bf93f0SYJwu2023 ///@param self ,bus_device_function PCI设备的唯一标识符 122478bf93f0SYJwu2023 ///@return Result<PciStandardDeviceBar, PciError> 成功则返回对应的PciStandardDeviceBar结构体,失败则返回错误类型 122578bf93f0SYJwu2023 pub fn pci_bar_init( 122678bf93f0SYJwu2023 bus_device_function: BusDeviceFunction, 122778bf93f0SYJwu2023 ) -> Result<PciStandardDeviceBar, PciError> { 122878bf93f0SYJwu2023 let mut device_bar: PciStandardDeviceBar = PciStandardDeviceBar::default(); 122926d84a31SYJwu2023 let mut bar_index_ignore: u8 = 255; 123026d84a31SYJwu2023 for bar_index in 0..6 { 123126d84a31SYJwu2023 if bar_index == bar_index_ignore { 123226d84a31SYJwu2023 continue; 123326d84a31SYJwu2023 } 123426d84a31SYJwu2023 let bar_info; 123526d84a31SYJwu2023 let mut virtaddress: u64 = 0; 123678bf93f0SYJwu2023 let bar_orig = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 123778bf93f0SYJwu2023 PciArch::write_config( 123878bf93f0SYJwu2023 &bus_device_function, 123926d84a31SYJwu2023 BAR0_OFFSET + 4 * bar_index, 124026d84a31SYJwu2023 0xffffffff, 124126d84a31SYJwu2023 ); 124278bf93f0SYJwu2023 let size_mask = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index); 124326d84a31SYJwu2023 // A wrapping add is necessary to correctly handle the case of unused BARs, which read back 124426d84a31SYJwu2023 // as 0, and should be treated as size 0. 124526d84a31SYJwu2023 let size = (!(size_mask & 0xfffffff0)).wrapping_add(1); 124626d84a31SYJwu2023 //kdebug!("bar_orig:{:#x},size: {:#x}", bar_orig,size); 124726d84a31SYJwu2023 // Restore the original value. 124878bf93f0SYJwu2023 PciArch::write_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index, bar_orig); 124926d84a31SYJwu2023 if size == 0 { 125026d84a31SYJwu2023 continue; 125126d84a31SYJwu2023 } 125226d84a31SYJwu2023 if bar_orig & 0x00000001 == 0x00000001 { 125326d84a31SYJwu2023 // I/O space 125426d84a31SYJwu2023 let address = bar_orig & 0xfffffffc; 125526d84a31SYJwu2023 bar_info = BarInfo::IO { address, size }; 125626d84a31SYJwu2023 } else { 125726d84a31SYJwu2023 // Memory space 125826d84a31SYJwu2023 let mut address = u64::from(bar_orig & 0xfffffff0); 125926d84a31SYJwu2023 let prefetchable = bar_orig & 0x00000008 != 0; 126026d84a31SYJwu2023 let address_type = MemoryBarType::try_from(((bar_orig & 0x00000006) >> 1) as u8)?; 126126d84a31SYJwu2023 if address_type == MemoryBarType::Width64 { 126226d84a31SYJwu2023 if bar_index >= 5 { 126326d84a31SYJwu2023 return Err(PciError::InvalidBarType); 126426d84a31SYJwu2023 } 126578bf93f0SYJwu2023 let address_top = 126678bf93f0SYJwu2023 PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * (bar_index + 1)); 126726d84a31SYJwu2023 address |= u64::from(address_top) << 32; 126826d84a31SYJwu2023 bar_index_ignore = bar_index + 1; //下个bar跳过,因为64位的memory bar覆盖了两个bar 126926d84a31SYJwu2023 } 127026d84a31SYJwu2023 //kdebug!("address={:#x},size={:#x}",address,size); 127126d84a31SYJwu2023 unsafe { 127226d84a31SYJwu2023 let vaddr_ptr = &mut virtaddress as *mut u64; 127326d84a31SYJwu2023 let mut virtsize: u64 = 0; 127426d84a31SYJwu2023 let virtsize_ptr = &mut virtsize as *mut u64; 127526d84a31SYJwu2023 let initial_mm_ptr = &mut initial_mm as *mut mm_struct; 127626d84a31SYJwu2023 //kdebug!("size want={:#x}", size); 127726d84a31SYJwu2023 if let Err(_) = MMIO_POOL.create_mmio( 127826d84a31SYJwu2023 size, 127926d84a31SYJwu2023 (VM_IO | VM_DONTCOPY) as u64, 128026d84a31SYJwu2023 vaddr_ptr, 128126d84a31SYJwu2023 virtsize_ptr, 128226d84a31SYJwu2023 ) { 128326d84a31SYJwu2023 kerror!("Create mmio failed when initing pci bar"); 128426d84a31SYJwu2023 return Err(PciError::CreateMmioError); 128526d84a31SYJwu2023 }; 128626d84a31SYJwu2023 //kdebug!("virtaddress={:#x},virtsize={:#x}",virtaddress,virtsize); 128726d84a31SYJwu2023 mm_map(initial_mm_ptr, virtaddress, size as u64, address); 128826d84a31SYJwu2023 } 128926d84a31SYJwu2023 bar_info = BarInfo::Memory { 129026d84a31SYJwu2023 address_type, 129126d84a31SYJwu2023 prefetchable, 129226d84a31SYJwu2023 address, 129326d84a31SYJwu2023 size, 129426d84a31SYJwu2023 virtaddress, 129526d84a31SYJwu2023 }; 129626d84a31SYJwu2023 } 129726d84a31SYJwu2023 match bar_index { 129826d84a31SYJwu2023 0 => { 129926d84a31SYJwu2023 device_bar.bar0 = bar_info; 130026d84a31SYJwu2023 } 130126d84a31SYJwu2023 1 => { 130226d84a31SYJwu2023 device_bar.bar1 = bar_info; 130326d84a31SYJwu2023 } 130426d84a31SYJwu2023 2 => { 130526d84a31SYJwu2023 device_bar.bar2 = bar_info; 130626d84a31SYJwu2023 } 130726d84a31SYJwu2023 3 => { 130826d84a31SYJwu2023 device_bar.bar3 = bar_info; 130926d84a31SYJwu2023 } 131026d84a31SYJwu2023 4 => { 131126d84a31SYJwu2023 device_bar.bar4 = bar_info; 131226d84a31SYJwu2023 } 131326d84a31SYJwu2023 5 => { 131426d84a31SYJwu2023 device_bar.bar5 = bar_info; 131526d84a31SYJwu2023 } 131626d84a31SYJwu2023 _ => {} 131726d84a31SYJwu2023 } 131826d84a31SYJwu2023 } 131926d84a31SYJwu2023 kdebug!("pci_device_bar:{}", device_bar); 132026d84a31SYJwu2023 return Ok(device_bar); 132126d84a31SYJwu2023 } 132226d84a31SYJwu2023 132326d84a31SYJwu2023 /// Information about a PCI device capability. 132426d84a31SYJwu2023 /// PCI设备的capability的信息 132526d84a31SYJwu2023 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 132626d84a31SYJwu2023 pub struct CapabilityInfo { 132726d84a31SYJwu2023 /// The offset of the capability in the PCI configuration space of the device function. 132826d84a31SYJwu2023 pub offset: u8, 132926d84a31SYJwu2023 /// The ID of the capability. 133026d84a31SYJwu2023 pub id: u8, 133126d84a31SYJwu2023 /// The third and fourth bytes of the capability, to save reading them again. 133226d84a31SYJwu2023 pub private_header: u16, 133326d84a31SYJwu2023 } 133473c607aaSYJwu2023 133526d84a31SYJwu2023 /// Iterator over capabilities for a device. 133626d84a31SYJwu2023 /// 创建迭代器以遍历PCI设备的capability 133726d84a31SYJwu2023 #[derive(Debug)] 133826d84a31SYJwu2023 pub struct CapabilityIterator { 133978bf93f0SYJwu2023 pub bus_device_function: BusDeviceFunction, 134026d84a31SYJwu2023 pub next_capability_offset: Option<u8>, 134126d84a31SYJwu2023 } 134226d84a31SYJwu2023 134326d84a31SYJwu2023 impl Iterator for CapabilityIterator { 134426d84a31SYJwu2023 type Item = CapabilityInfo; 134526d84a31SYJwu2023 fn next(&mut self) -> Option<Self::Item> { 134626d84a31SYJwu2023 let offset = self.next_capability_offset?; 134726d84a31SYJwu2023 134826d84a31SYJwu2023 // Read the first 4 bytes of the capability. 134978bf93f0SYJwu2023 let capability_header = PciArch::read_config(&self.bus_device_function, offset); 135026d84a31SYJwu2023 let id = capability_header as u8; 135126d84a31SYJwu2023 let next_offset = (capability_header >> 8) as u8; 135226d84a31SYJwu2023 let private_header = (capability_header >> 16) as u16; 135326d84a31SYJwu2023 135426d84a31SYJwu2023 self.next_capability_offset = if next_offset == 0 { 135526d84a31SYJwu2023 None 135626d84a31SYJwu2023 } else if next_offset < 64 || next_offset & 0x3 != 0 { 135726d84a31SYJwu2023 kwarn!("Invalid next capability offset {:#04x}", next_offset); 135826d84a31SYJwu2023 None 135926d84a31SYJwu2023 } else { 136026d84a31SYJwu2023 Some(next_offset) 136126d84a31SYJwu2023 }; 136226d84a31SYJwu2023 136326d84a31SYJwu2023 Some(CapabilityInfo { 136426d84a31SYJwu2023 offset, 136526d84a31SYJwu2023 id, 136626d84a31SYJwu2023 private_header, 136726d84a31SYJwu2023 }) 136826d84a31SYJwu2023 } 136926d84a31SYJwu2023 } 137073c607aaSYJwu2023 137178bf93f0SYJwu2023 /// Information about a PCIe device capability. 137278bf93f0SYJwu2023 /// PCIe设备的external capability的信息 137378bf93f0SYJwu2023 #[derive(Debug, Copy, Clone, Eq, PartialEq)] 137478bf93f0SYJwu2023 pub struct ExternalCapabilityInfo { 137578bf93f0SYJwu2023 /// The offset of the capability in the PCI configuration space of the device function. 137678bf93f0SYJwu2023 pub offset: u16, 137778bf93f0SYJwu2023 /// The ID of the capability. 137878bf93f0SYJwu2023 pub id: u16, 137978bf93f0SYJwu2023 /// The third and fourth bytes of the capability, to save reading them again. 138078bf93f0SYJwu2023 pub capability_version: u8, 138173c607aaSYJwu2023 } 138278bf93f0SYJwu2023 138378bf93f0SYJwu2023 /// Iterator over capabilities for a device. 138478bf93f0SYJwu2023 /// 创建迭代器以遍历PCIe设备的external capability 138578bf93f0SYJwu2023 #[derive(Debug)] 138678bf93f0SYJwu2023 pub struct ExternalCapabilityIterator<'a> { 138778bf93f0SYJwu2023 pub root: &'a PciRoot, 138878bf93f0SYJwu2023 pub bus_device_function: BusDeviceFunction, 138978bf93f0SYJwu2023 pub next_capability_offset: Option<u16>, 139073c607aaSYJwu2023 } 139178bf93f0SYJwu2023 impl<'a> Iterator for ExternalCapabilityIterator<'a> { 139278bf93f0SYJwu2023 type Item = ExternalCapabilityInfo; 139378bf93f0SYJwu2023 fn next(&mut self) -> Option<Self::Item> { 139478bf93f0SYJwu2023 let offset = self.next_capability_offset?; 139578bf93f0SYJwu2023 139678bf93f0SYJwu2023 // Read the first 4 bytes of the capability. 139778bf93f0SYJwu2023 let capability_header = self.root.read_config(self.bus_device_function, offset); 139878bf93f0SYJwu2023 let id = capability_header as u16; 139978bf93f0SYJwu2023 let next_offset = (capability_header >> 20) as u16; 140078bf93f0SYJwu2023 let capability_version = ((capability_header >> 16) & 0xf) as u8; 140178bf93f0SYJwu2023 140278bf93f0SYJwu2023 self.next_capability_offset = if next_offset == 0 { 140378bf93f0SYJwu2023 None 140478bf93f0SYJwu2023 } else if next_offset < 0x100 || next_offset & 0x3 != 0 { 140578bf93f0SYJwu2023 kwarn!("Invalid next capability offset {:#04x}", next_offset); 140678bf93f0SYJwu2023 None 140778bf93f0SYJwu2023 } else { 140878bf93f0SYJwu2023 Some(next_offset) 140978bf93f0SYJwu2023 }; 141078bf93f0SYJwu2023 141178bf93f0SYJwu2023 Some(ExternalCapabilityInfo { 141278bf93f0SYJwu2023 offset, 141378bf93f0SYJwu2023 id, 141478bf93f0SYJwu2023 capability_version, 141578bf93f0SYJwu2023 }) 141678bf93f0SYJwu2023 } 141773c607aaSYJwu2023 } 1418