1 // 参考手册: PCIe* GbE Controllers Open Source Software Developer’s Manual 2 // Refernce: PCIe* GbE Controllers Open Source Software Developer’s Manual 3 4 use alloc::string::ToString; 5 use alloc::sync::Arc; 6 use alloc::vec::Vec; 7 use core::intrinsics::unlikely; 8 use core::mem::size_of; 9 use core::ptr::NonNull; 10 use core::slice::{from_raw_parts, from_raw_parts_mut}; 11 use core::sync::atomic::{compiler_fence, Ordering}; 12 use log::{debug, info}; 13 14 use super::e1000e_driver::e1000e_driver_init; 15 use crate::driver::base::device::DeviceId; 16 use crate::driver::net::dma::{dma_alloc, dma_dealloc}; 17 use crate::driver::net::irq_handle::DefaultNetIrqHandler; 18 use crate::driver::pci::pci::{ 19 get_pci_device_structure_mut, PciDeviceStructure, PciDeviceStructureGeneralDevice, PciError, 20 PCI_DEVICE_LINKEDLIST, 21 }; 22 use crate::driver::pci::pci_irq::{IrqCommonMsg, IrqSpecificMsg, PciInterrupt, PciIrqMsg, IRQ}; 23 use crate::exception::IrqNumber; 24 25 use crate::libs::volatile::{ReadOnly, Volatile, WriteOnly}; 26 27 const PAGE_SIZE: usize = 4096; 28 const NETWORK_CLASS: u8 = 0x2; 29 const ETHERNET_SUBCLASS: u8 = 0x0; 30 // e1000e系列网卡的device id列表，来源：https://admin.pci-ids.ucw.cz/read/PC/8086 31 const E1000E_DEVICE_ID: [u16; 14] = [ 32 0x10d3, // 8574L, qemu default 33 0x10cc, // 82567LM-2 34 0x10cd, // 82567LF-2 35 0x105f, // 82571EB 36 0x1060, // 82571EB 37 0x107f, // 82572EI 38 0x109a, // 82573L 39 0x10ea, // 82577LM 40 0x10eb, // 82577LC 41 0x10ef, // 82578DM 42 0x10f0, // 82578DC 43 0x1502, // 82579LM 44 0x1503, // 82579V 45 0x150c, // 82583V 46 ]; 47 48 // e1000e网卡与BAR有关的常量 49 // BAR0空间大小(128KB) 50 const E1000E_BAR_REG_SIZE: u32 = 128 * 1024; 51 // BAR0空间对齐(64bit) 52 #[allow(dead_code)] 53 const E1000E_BAR_REG_ALIGN: u8 = 64; 54 // 单个寄存器大小(32bit, 4字节) 55 #[allow(dead_code)] 56 const E1000E_REG_SIZE: u8 = 4; 57 58 // TxBuffer和RxBuffer的大小(DMA页) 59 const E1000E_DMA_PAGES: usize = 1; 60 61 // 中断相关 62 const E1000E_RECV_VECTOR: IrqNumber = IrqNumber::new(57); 63 64 // napi队列中暂时存储的buffer个数 65 const E1000E_RECV_NAPI: usize = 1024; 66 67 // 收/发包的描述符结构 pp.24 Table 3-1 68 #[repr(C)] 69 #[derive(Copy, Clone, Debug)] 70 struct E1000ETransDesc { 71 addr: u64, 72 len: u16, 73 cso: u8, 74 cmd: u8, 75 status: u8, 76 css: u8, 77 special: u8, 78 } 79 // pp.54 Table 3-12 80 #[repr(C)] 81 #[derive(Copy, Clone, Debug)] 82 struct E1000ERecvDesc { 83 addr: u64, 84 len: u16, 85 chksum: u16, 86 status: u16, 87 error: u8, 88 special: u8, 89 } 90 #[derive(Copy, Clone)] 91 // Buffer的Copy只是指针操作，不涉及实际数据的复制，因此要小心使用，确保不同的buffer不会使用同一块内存 92 pub struct E1000EBuffer { 93 buffer: NonNull<u8>, 94 paddr: usize, 95 // length字段为0则表示这个buffer是一个占位符，不指向实际内存 96 // the buffer is empty and no page is allocated if length field is set 0 97 length: usize, 98 } 99 100 impl E1000EBuffer { 101 pub fn new(length: usize) -> Self { 102 assert!(length <= PAGE_SIZE); 103 if unlikely(length == 0) { 104 // 在某些情况下，我们并不需要实际分配buffer，只需要提供一个占位符即可 105 // we dont need to allocate dma pages for buffer in some cases 106 E1000EBuffer { 107 buffer: NonNull::dangling(), 108 paddr: 0, 109 length: 0, 110 } 111 } else { 112 let (paddr, vaddr) = dma_alloc(E1000E_DMA_PAGES); 113 E1000EBuffer { 114 buffer: vaddr, 115 paddr, 116 length, 117 } 118 } 119 } 120 121 #[allow(dead_code)] 122 pub fn as_addr(&self) -> NonNull<u8> { 123 assert!(self.length != 0); 124 return self.buffer; 125 } 126 127 #[allow(dead_code)] 128 pub fn as_addr_u64(&self) -> u64 { 129 assert!(self.length != 0); 130 return self.buffer.as_ptr() as u64; 131 } 132 133 pub fn as_paddr(&self) -> usize { 134 assert!(self.length != 0); 135 return self.paddr; 136 } 137 138 #[allow(dead_code)] 139 pub fn as_slice(&self) -> &[u8] { 140 assert!(self.length != 0); 141 return unsafe { from_raw_parts(self.buffer.as_ptr(), self.length) }; 142 } 143 144 pub fn as_mut_slice(&mut self) -> &mut [u8] { 145 assert!(self.length != 0); 146 return unsafe { from_raw_parts_mut(self.buffer.as_ptr(), self.length) }; 147 } 148 149 pub fn set_length(&mut self, length: usize) { 150 self.length = length; 151 } 152 153 pub fn len(&self) -> usize { 154 return self.length; 155 } 156 // 释放buffer内部的dma_pages，需要小心使用 157 pub fn free_buffer(self) { 158 if self.length != 0 { 159 unsafe { dma_dealloc(self.paddr, self.buffer, E1000E_DMA_PAGES) }; 160 } 161 } 162 } 163 164 #[allow(dead_code)] 165 pub struct E1000EDevice { 166 // 设备寄存器 167 // device registers 168 general_regs: NonNull<GeneralRegs>, 169 interrupt_regs: NonNull<InterruptRegs>, 170 rctl_regs: NonNull<ReceiveCtrlRegs>, 171 receive_regs: NonNull<ReceiveRegs>, 172 tctl_regs: NonNull<TransmitCtrlRegs>, 173 transimit_regs: NonNull<TransimitRegs>, 174 pcie_regs: NonNull<PCIeRegs>, 175 176 // descriptor环形队列，在操作系统与设备之间共享 177 // descriptor rings are shared between os and device 178 recv_desc_ring: &'static mut [E1000ERecvDesc], 179 trans_desc_ring: &'static mut [E1000ETransDesc], 180 recv_ring_pa: usize, 181 trans_ring_pa: usize, 182 183 // 设备收/发包缓冲区数组 184 // buffers of receive/transmit packets 185 recv_buffers: Vec<E1000EBuffer>, 186 trans_buffers: Vec<E1000EBuffer>, 187 mac: [u8; 6], 188 first_trans: bool, 189 // napi队列，用于存放在中断关闭期间通过轮询收取的buffer 190 // the napi queue is designed to save buffer/packet when the interrupt is close 191 // NOTE: this feature is not completely implemented and not used in the current version 192 napi_buffers: Vec<E1000EBuffer>, 193 napi_buffer_head: usize, 194 napi_buffer_tail: usize, 195 napi_buffer_empty: bool, 196 } 197 198 impl E1000EDevice { 199 // 从PCI标准设备进行驱动初始化 200 // init the device for PCI standard device struct 201 #[allow(unused_assignments)] 202 pub fn new( 203 device: &mut PciDeviceStructureGeneralDevice, 204 device_id: Arc<DeviceId>, 205 ) -> Result<Self, E1000EPciError> { 206 // 从BAR0获取我们需要的寄存器 207 // Build registers sturcts from BAR0 208 device.bar_ioremap().unwrap()?; 209 device.enable_master(); 210 let bar = device.bar().ok_or(E1000EPciError::BarGetFailed)?; 211 let bar0 = bar.get_bar(0)?; 212 let (address, size) = bar0 213 .memory_address_size() 214 .ok_or(E1000EPciError::UnexpectedBarType)?; 215 if address == 0 { 216 return Err(E1000EPciError::BarNotAllocated); 217 } 218 if size != E1000E_BAR_REG_SIZE { 219 return Err(E1000EPciError::UnexpectedBarSize); 220 } 221 let vaddress = bar0 222 .virtual_address() 223 .ok_or(E1000EPciError::BarGetVaddrFailed)? 224 .data() as u64; 225 226 // 初始化msi中断 227 // initialize msi interupt 228 let irq_vector = device.irq_vector_mut().unwrap(); 229 irq_vector.push(E1000E_RECV_VECTOR); 230 device.irq_init(IRQ::PCI_IRQ_MSI).expect("IRQ Init Failed"); 231 let msg = PciIrqMsg { 232 irq_common_message: IrqCommonMsg::init_from( 233 0, 234 "E1000E_RECV_IRQ".to_string(), 235 &DefaultNetIrqHandler, 236 device_id, 237 ), 238 irq_specific_message: IrqSpecificMsg::msi_default(), 239 }; 240 device.irq_install(msg)?; 241 device.irq_enable(true)?; 242 243 let general_regs: NonNull<GeneralRegs> = 244 get_register_ptr(vaddress, E1000E_GENERAL_REGS_OFFSET); 245 let interrupt_regs: NonNull<InterruptRegs> = 246 get_register_ptr(vaddress, E1000E_INTERRRUPT_REGS_OFFSET); 247 let rctl_regs: NonNull<ReceiveCtrlRegs> = 248 get_register_ptr(vaddress, E1000E_RECEIVE_CTRL_REG_OFFSET); 249 let receive_regs: NonNull<ReceiveRegs> = 250 get_register_ptr(vaddress, E1000E_RECEIVE_REGS_OFFSET); 251 let tctl_regs: NonNull<TransmitCtrlRegs> = 252 get_register_ptr(vaddress, E1000E_TRANSMIT_CTRL_REG_OFFSET); 253 let transimit_regs: NonNull<TransimitRegs> = 254 get_register_ptr(vaddress, E1000E_TRANSMIT_REGS_OFFSET); 255 let pcie_regs: NonNull<PCIeRegs> = get_register_ptr(vaddress, E1000E_PCIE_REGS_OFFSET); 256 let ra_regs: NonNull<ReceiveAddressRegs> = 257 get_register_ptr(vaddress, E1000E_RECEIVE_ADDRESS_REGS_OFFSET); 258 // 开始设备初始化 14.3 259 // Initialization Sequence 260 unsafe { 261 let mut ctrl = volread!(general_regs, ctrl); 262 // 关闭中断 263 // close the interrupt 264 volwrite!(interrupt_regs, imc, E1000E_IMC_CLEAR); 265 //SW RESET 266 volwrite!(general_regs, ctrl, ctrl | E1000E_CTRL_RST); 267 compiler_fence(Ordering::AcqRel); 268 // PHY RESET 269 ctrl = volread!(general_regs, ctrl); 270 volwrite!(general_regs, ctrl, ctrl | E1000E_CTRL_PHY_RST); 271 volwrite!(general_regs, ctrl, ctrl); 272 // 关闭中断 273 // close the interrupt 274 volwrite!(interrupt_regs, imc, E1000E_IMC_CLEAR); 275 let mut gcr = volread!(pcie_regs, gcr); 276 gcr |= 1 << 22; 277 volwrite!(pcie_regs, gcr, gcr); 278 compiler_fence(Ordering::AcqRel); 279 // PHY Initialization 14.8.1 280 // MAC/PHY Link Setup 14.8.2 281 ctrl = volread!(general_regs, ctrl); 282 ctrl &= !(E1000E_CTRL_FRCSPD | E1000E_CTRL_FRCDPLX); 283 volwrite!(general_regs, ctrl, ctrl | E1000E_CTRL_SLU); 284 } 285 let status = unsafe { volread!(general_regs, status) }; 286 debug!("Status: {status:#X}"); 287 288 // 读取设备的mac地址 289 // Read mac address 290 let ral = unsafe { volread!(ra_regs, ral0) }; 291 let rah = unsafe { volread!(ra_regs, rah0) }; 292 let mac: [u8; 6] = [ 293 (ral & 0xFF) as u8, 294 ((ral >> 8) & 0xFF) as u8, 295 ((ral >> 16) & 0xFF) as u8, 296 ((ral >> 24) & 0xFF) as u8, 297 (rah & 0xFF) as u8, 298 ((rah >> 8) & 0xFF) as u8, 299 ]; 300 // 初始化receive和transimit descriptor环形队列 301 // initialize receive and transimit desciptor ring 302 let (recv_ring_pa, recv_ring_va) = dma_alloc(E1000E_DMA_PAGES); 303 let (trans_ring_pa, trans_ring_va) = dma_alloc(E1000E_DMA_PAGES); 304 let recv_ring_length = PAGE_SIZE / size_of::<E1000ERecvDesc>(); 305 let trans_ring_length = PAGE_SIZE / size_of::<E1000ETransDesc>(); 306 307 let recv_desc_ring = unsafe { 308 from_raw_parts_mut::<E1000ERecvDesc>(recv_ring_va.as_ptr().cast(), recv_ring_length) 309 }; 310 let trans_desc_ring = unsafe { 311 from_raw_parts_mut::<E1000ETransDesc>(trans_ring_va.as_ptr().cast(), trans_ring_length) 312 }; 313 314 // 初始化receive和transmit packet的缓冲区 315 // initialzie receive and transmit buffers 316 let mut recv_buffers: Vec<E1000EBuffer> = Vec::with_capacity(recv_ring_length); 317 let mut trans_buffers: Vec<E1000EBuffer> = Vec::with_capacity(trans_ring_length); 318 319 // 初始化缓冲区与descriptor，descriptor 中的addr字典应当指向buffer的物理地址 320 // Receive buffers of appropriate size should be allocated and pointers to these buffers should be stored in the descriptor ring. 321 for ring in recv_desc_ring.iter_mut().take(recv_ring_length) { 322 let buffer = E1000EBuffer::new(PAGE_SIZE); 323 ring.addr = buffer.as_paddr() as u64; 324 ring.status = 0; 325 recv_buffers.push(buffer); 326 } 327 // Same as receive buffers 328 for ring in trans_desc_ring.iter_mut().take(recv_ring_length) { 329 let buffer = E1000EBuffer::new(PAGE_SIZE); 330 ring.addr = buffer.as_paddr() as u64; 331 ring.status = 1; 332 trans_buffers.push(buffer); 333 } 334 335 // Receive Initialization 14.6 336 // Initialzie mutlicast table array to 0b 337 // 初始化MTA，遍历0x05200-0x053FC中每个寄存器，写入0b，一共128个寄存器 338 let mut mta_adress = vaddress + E1000E_MTA_REGS_START_OFFSET; 339 while mta_adress != vaddress + E1000E_MTA_REGS_END_OFFSET { 340 let mta: NonNull<MTARegs> = get_register_ptr(mta_adress, 0); 341 unsafe { volwrite!(mta, mta, 0) }; 342 mta_adress += 4; 343 } 344 // 连续的寄存器读-写操作，放在同一个unsafe块中 345 unsafe { 346 // 设置descriptor环形队列的基地址 347 // Program the descriptor base address with the address of the region. 348 volwrite!(receive_regs, rdbal0, (recv_ring_pa) as u32); 349 volwrite!(receive_regs, rdbah0, (recv_ring_pa >> 32) as u32); 350 // 设置descriptor环形队列的长度 351 // Set the length register to the size of the descriptor ring. 352 volwrite!(receive_regs, rdlen0, PAGE_SIZE as u32); 353 // 设置队列的首尾指针 354 // Program the head and tail registers 355 volwrite!(receive_regs, rdh0, 0); 356 volwrite!(receive_regs, rdt0, (recv_ring_length - 1) as u32); 357 // 设置控制寄存器的相关功能 14.6.1 358 // Set the receive control register 359 volwrite!( 360 rctl_regs, 361 rctl, 362 E1000E_RCTL_EN 363 | E1000E_RCTL_BAM 364 | E1000E_RCTL_BSIZE_4K 365 | E1000E_RCTL_BSEX 366 | E1000E_RCTL_SECRC 367 ); 368 369 // Transmit Initialization 14.7 370 // 开启发包descriptor的回写功能 371 // Program the TXDCTL register with the desired TX descriptor write-back policy 372 volwrite!( 373 transimit_regs, 374 txdctl, 375 E1000E_TXDCTL_WTHRESH | E1000E_TXDCTL_GRAN 376 ); 377 // 设置descriptor环形队列的基地址，长度与首尾指针 378 // Program the descriptor base address with the address of the region 379 volwrite!(transimit_regs, tdbal0, trans_ring_pa as u32); 380 volwrite!(transimit_regs, tdbah0, (trans_ring_pa >> 32) as u32); 381 // Set the length register to the size of the descriptor ring. 382 volwrite!(transimit_regs, tdlen0, PAGE_SIZE as u32); 383 // Program the head and tail registerss 384 volwrite!(transimit_regs, tdh0, 0); 385 volwrite!(transimit_regs, tdt0, 0); 386 // Program the TIPG register 387 volwrite!( 388 tctl_regs, 389 tipg, 390 E1000E_TIPG_IPGT | E1000E_TIPG_IPGR1 | E1000E_TIPG_IPGR2 391 ); 392 // Program the TCTL register. 393 volwrite!( 394 tctl_regs, 395 tctl, 396 E1000E_TCTL_EN | E1000E_TCTL_PSP | E1000E_TCTL_CT_VAL | E1000E_TCTL_COLD_VAL 397 ); 398 399 let icr = volread!(interrupt_regs, icr); 400 volwrite!(interrupt_regs, icr, icr); 401 // 开启收包相关的中断 402 // Enable receive interrupts 403 let mut ims = volread!(interrupt_regs, ims); 404 ims = E1000E_IMS_LSC | E1000E_IMS_RXT0 | E1000E_IMS_RXDMT0 | E1000E_IMS_OTHER; 405 volwrite!(interrupt_regs, ims, ims); 406 } 407 return Ok(E1000EDevice { 408 general_regs, 409 interrupt_regs, 410 rctl_regs, 411 receive_regs, 412 tctl_regs, 413 transimit_regs, 414 pcie_regs, 415 recv_desc_ring, 416 trans_desc_ring, 417 recv_ring_pa, 418 trans_ring_pa, 419 recv_buffers, 420 trans_buffers, 421 mac, 422 first_trans: true, 423 napi_buffers: vec![E1000EBuffer::new(0); E1000E_RECV_NAPI], 424 napi_buffer_head: 0, 425 napi_buffer_tail: 0, 426 napi_buffer_empty: true, 427 }); 428 } 429 pub fn e1000e_receive(&mut self) -> Option<E1000EBuffer> { 430 self.e1000e_intr(); 431 let mut rdt = unsafe { volread!(self.receive_regs, rdt0) } as usize; 432 let index = (rdt + 1) % self.recv_desc_ring.len(); 433 let desc = &mut self.recv_desc_ring[index]; 434 if (desc.status & E1000E_RXD_STATUS_DD) == 0 { 435 return None; 436 } 437 let mut buffer = self.recv_buffers[index]; 438 let new_buffer = E1000EBuffer::new(PAGE_SIZE); 439 self.recv_buffers[index] = new_buffer; 440 desc.addr = new_buffer.as_paddr() as u64; 441 buffer.set_length(desc.len as usize); 442 rdt = index; 443 unsafe { volwrite!(self.receive_regs, rdt0, rdt as u32) }; 444 // debug!("e1000e: receive packet"); 445 return Some(buffer); 446 } 447 448 pub fn e1000e_can_transmit(&self) -> bool { 449 let tdt = unsafe { volread!(self.transimit_regs, tdt0) } as usize; 450 let index = tdt % self.trans_desc_ring.len(); 451 let desc = &self.trans_desc_ring[index]; 452 if (desc.status & E1000E_TXD_STATUS_DD) == 0 { 453 return false; 454 } 455 true 456 } 457 458 pub fn e1000e_transmit(&mut self, packet: E1000EBuffer) { 459 let mut tdt = unsafe { volread!(self.transimit_regs, tdt0) } as usize; 460 let index = tdt % self.trans_desc_ring.len(); 461 let desc = &mut self.trans_desc_ring[index]; 462 let buffer = self.trans_buffers[index]; 463 self.trans_buffers[index] = packet; 464 // recycle unused transmit buffer 465 buffer.free_buffer(); 466 // Set the transmit descriptor 467 desc.addr = packet.as_paddr() as u64; 468 desc.len = packet.len() as u16; 469 desc.status = 0; 470 desc.cmd = E1000E_TXD_CMD_EOP | E1000E_TXD_CMD_RS | E1000E_TXD_CMD_IFCS; 471 tdt = (tdt + 1) % self.trans_desc_ring.len(); 472 unsafe { volwrite!(self.transimit_regs, tdt0, tdt as u32) }; 473 self.first_trans = false; 474 } 475 pub fn mac_address(&self) -> [u8; 6] { 476 return self.mac; 477 } 478 // 向ICR寄存器中的某一bit写入1b表示该中断已经被接收，同时会清空该位 479 // we need to clear ICR to tell e1000e we have read the interrupt 480 pub fn e1000e_intr(&mut self) { 481 let icr = unsafe { volread!(self.interrupt_regs, icr) }; 482 // write 1b to any bit in ICR will clear the bit 483 unsafe { volwrite!(self.interrupt_regs, icr, icr) }; 484 } 485 486 // 切换是否接受分组到达的中断 487 // change whether the receive timer interrupt is enabled 488 // Note: this method is not completely implemented and not used in the current version 489 #[allow(dead_code)] 490 pub fn e1000e_intr_set(&mut self, state: bool) { 491 let mut ims = unsafe { volread!(self.interrupt_regs, ims) }; 492 match state { 493 true => ims |= E1000E_IMS_RXT0, 494 false => ims &= !E1000E_IMS_RXT0, 495 } 496 unsafe { volwrite!(self.interrupt_regs, ims, ims) }; 497 } 498 499 // 实现了一部分napi机制的收包函数, 现在还没有投入使用 500 // This method is a partial implementation of napi (New API) techniques 501 // Note: this method is not completely implemented and not used in the current version 502 #[allow(dead_code)] 503 pub fn e1000e_receive2(&mut self) -> Option<E1000EBuffer> { 504 // 向设备表明我们已经接受到了之前的中断 505 // Tell e1000e we have received the interrupt 506 self.e1000e_intr(); 507 // 如果napi队列不存在已经收到的分组... 508 // if napi queue is empty... 509 if self.napi_buffer_empty { 510 // 暂时关闭设备中断 511 // close interrupt 512 self.e1000e_intr_set(false); 513 loop { 514 if self.napi_buffer_tail == self.napi_buffer_head && !self.napi_buffer_empty { 515 // napi缓冲队列已满，停止收包 516 // napi queue is full, stop 517 break; 518 } 519 match self.e1000e_receive() { 520 Some(buffer) => { 521 self.napi_buffers[self.napi_buffer_tail] = buffer; 522 self.napi_buffer_tail = (self.napi_buffer_tail + 1) % E1000E_RECV_NAPI; 523 self.napi_buffer_empty = false; 524 } 525 None => { 526 // 设备队列中没有剩余的已到达的数据包 527 // no packet remains in the device buffer 528 break; 529 } 530 }; 531 } 532 // 重新打开设备中断 533 // open the interrupt 534 self.e1000e_intr_set(true); 535 } 536 537 let result = self.napi_buffers[self.napi_buffer_head]; 538 match result.len() { 539 0 => { 540 // napi队列和网卡队列中都不存在数据包 541 // both napi queue and device buffer is empty, no packet will receive 542 return None; 543 } 544 _ => { 545 // 有剩余的已到达的数据包 546 // there is packet in napi queue 547 self.napi_buffer_head = (self.napi_buffer_head + 1) % E1000E_RECV_NAPI; 548 if self.napi_buffer_head == self.napi_buffer_tail { 549 self.napi_buffer_empty = true; 550 } 551 return Some(result); 552 } 553 } 554 } 555 } 556 557 impl Drop for E1000EDevice { 558 fn drop(&mut self) { 559 // 释放已分配的所有dma页 560 // free all dma pages we have allocated 561 debug!("droping..."); 562 let recv_ring_length = PAGE_SIZE / size_of::<E1000ERecvDesc>(); 563 let trans_ring_length = PAGE_SIZE / size_of::<E1000ETransDesc>(); 564 unsafe { 565 // 释放所有buffer中的dma页 566 // free all dma pages in buffers 567 for i in 0..recv_ring_length { 568 self.recv_buffers[i].free_buffer(); 569 } 570 for i in 0..trans_ring_length { 571 self.trans_buffers[i].free_buffer(); 572 } 573 // 释放descriptor ring 574 // free descriptor ring 575 dma_dealloc( 576 self.recv_ring_pa, 577 NonNull::new(self.recv_desc_ring).unwrap().cast(), 578 E1000E_DMA_PAGES, 579 ); 580 dma_dealloc( 581 self.trans_ring_pa, 582 NonNull::new(self.trans_desc_ring).unwrap().cast(), 583 E1000E_DMA_PAGES, 584 ); 585 } 586 } 587 } 588 589 pub fn e1000e_init() { 590 match e1000e_probe() { 591 Ok(_code) => { 592 info!("Successfully init e1000e device!"); 593 } 594 Err(_error) => { 595 info!("Error occurred!"); 596 } 597 } 598 } 599 600 pub fn e1000e_probe() -> Result<u64, E1000EPciError> { 601 let mut list = PCI_DEVICE_LINKEDLIST.write(); 602 let result = get_pci_device_structure_mut(&mut list, NETWORK_CLASS, ETHERNET_SUBCLASS); 603 if result.is_empty() { 604 return Ok(0); 605 } 606 for device in result { 607 let standard_device = device.as_standard_device_mut().unwrap(); 608 let header = &standard_device.common_header; 609 if header.vendor_id == 0x8086 { 610 // intel 611 if E1000E_DEVICE_ID.contains(&header.device_id) { 612 debug!( 613 "Detected e1000e PCI device with device id {:#x}", 614 header.device_id 615 ); 616 617 // todo: 根据pci的path来生成device id 618 let e1000e = E1000EDevice::new( 619 standard_device, 620 DeviceId::new(None, Some(format!("e1000e_{}", header.device_id))).unwrap(), 621 )?; 622 e1000e_driver_init(e1000e); 623 } 624 } 625 } 626 627 return Ok(1); 628 } 629 630 // 用到的e1000e寄存器结构体 631 // pp.275, Table 13-3 632 // 设备通用寄存器 633 #[allow(dead_code)] 634 struct GeneralRegs { 635 ctrl: Volatile<u32>, //0x00000 636 ctrl_alias: Volatile<u32>, //0x00004 637 status: ReadOnly<u32>, //0x00008 638 status_align: ReadOnly<u32>, //0x0000c 639 eec: Volatile<u32>, //0x00010 640 eerd: Volatile<u32>, //0x00014 641 ctrl_ext: Volatile<u32>, //0x00018 642 fla: Volatile<u32>, //0x0001c 643 mdic: Volatile<u32>, //0x00020 644 } 645 // 中断控制 646 #[allow(dead_code)] 647 struct InterruptRegs { 648 icr: Volatile<u32>, //0x000c0 ICR寄存器应当为只读寄存器，但我们需要向其中写入来清除对应位 649 itr: Volatile<u32>, //0x000c4 650 ics: WriteOnly<u32>, //0x000c8 651 ics_align: ReadOnly<u32>, //0x000cc 652 ims: Volatile<u32>, //0x000d0 653 ims_align: ReadOnly<u32>, //0x000d4 654 imc: WriteOnly<u32>, //0x000d8 655 } 656 // 收包功能控制 657 struct ReceiveCtrlRegs { 658 rctl: Volatile<u32>, //0x00100 659 } 660 // 发包功能控制 661 #[allow(dead_code)] 662 struct TransmitCtrlRegs { 663 tctl: Volatile<u32>, //0x00400 664 tctl_ext: Volatile<u32>, //0x00404 665 unused_1: ReadOnly<u32>, //0x00408 666 unused_2: ReadOnly<u32>, //0x0040c 667 tipg: Volatile<u32>, //0x00410 668 } 669 // 收包功能相关 670 #[allow(dead_code)] 671 struct ReceiveRegs { 672 rdbal0: Volatile<u32>, //0x02800 673 rdbah0: Volatile<u32>, //0x02804 674 rdlen0: Volatile<u32>, //0x02808 675 rdl_align: ReadOnly<u32>, //0x0280c 676 rdh0: Volatile<u32>, //0x02810 677 rdh_align: ReadOnly<u32>, //0x02814 678 rdt0: Volatile<u32>, //0x02818 679 rdt_align: ReadOnly<u32>, //0x281c 680 rdtr: Volatile<u32>, //0x2820 681 rdtr_align: ReadOnly<u32>, //0x2824 682 rxdctl: Volatile<u32>, //0x2828 683 } 684 // 发包功能相关 685 #[allow(dead_code)] 686 struct TransimitRegs { 687 tdbal0: Volatile<u32>, //0x03800 688 tdbah0: Volatile<u32>, //0x03804 689 tdlen0: Volatile<u32>, //0x03808 690 tdlen_algin: ReadOnly<u32>, //0x0380c 691 tdh0: Volatile<u32>, //0x03810 692 tdh_align: ReadOnly<u32>, //0x03814 693 tdt0: Volatile<u32>, //0x03818 694 tdt_align: ReadOnly<u32>, //0x0381c 695 tidv: Volatile<u32>, //0x03820 696 tidv_align: ReadOnly<u32>, //0x03824 697 txdctl: Volatile<u32>, //0x03828 698 tadv: Volatile<u32>, //0x0382c 699 } 700 // mac地址 701 struct ReceiveAddressRegs { 702 ral0: Volatile<u32>, //0x05400 703 rah0: Volatile<u32>, //0x05404 704 } 705 // PCIe 通用控制 706 struct PCIeRegs { 707 gcr: Volatile<u32>, //0x05b00 708 } 709 #[allow(dead_code)] 710 struct StatisticsRegs {} 711 712 // 0x05200-0x053fc 713 // 在Receive Initialization 中按照每次一个32bit寄存器的方式来遍历 714 // Multicast Table Array Registers will be written per 32bit 715 struct MTARegs { 716 mta: Volatile<u32>, 717 } 718 719 const E1000E_GENERAL_REGS_OFFSET: u64 = 0x00000; 720 const E1000E_INTERRRUPT_REGS_OFFSET: u64 = 0x000c0; 721 const E1000E_RECEIVE_CTRL_REG_OFFSET: u64 = 0x00100; 722 const E1000E_RECEIVE_REGS_OFFSET: u64 = 0x02800; 723 const E1000E_TRANSMIT_CTRL_REG_OFFSET: u64 = 0x00400; 724 const E1000E_TRANSMIT_REGS_OFFSET: u64 = 0x03800; 725 const E1000E_RECEIVE_ADDRESS_REGS_OFFSET: u64 = 0x05400; 726 const E1000E_PCIE_REGS_OFFSET: u64 = 0x05b00; 727 const E1000E_MTA_REGS_START_OFFSET: u64 = 0x05200; 728 const E1000E_MTA_REGS_END_OFFSET: u64 = 0x053fc; 729 // 寄存器的特定位 730 //CTRL 731 const E1000E_CTRL_SLU: u32 = 1 << 6; 732 const E1000E_CTRL_FRCSPD: u32 = 1 << 11; 733 const E1000E_CTRL_FRCDPLX: u32 = 1 << 12; 734 const E1000E_CTRL_RST: u32 = 1 << 26; 735 #[allow(dead_code)] 736 const E1000E_CTRL_RFCE: u32 = 1 << 27; 737 #[allow(dead_code)] 738 const E1000E_CTRL_TFCE: u32 = 1 << 28; 739 const E1000E_CTRL_PHY_RST: u32 = 1 << 31; 740 741 // IMS 742 const E1000E_IMS_LSC: u32 = 1 << 2; 743 const E1000E_IMS_RXDMT0: u32 = 1 << 4; 744 #[allow(dead_code)] 745 const E1000E_IMS_RXO: u32 = 1 << 6; 746 const E1000E_IMS_RXT0: u32 = 1 << 7; 747 #[allow(dead_code)] 748 const E1000E_IMS_RXQ0: u32 = 1 << 20; 749 const E1000E_IMS_OTHER: u32 = 1 << 24; // qemu use this bit to set msi-x interrupt 750 751 // IMC 752 const E1000E_IMC_CLEAR: u32 = 0xffffffff; 753 754 // RCTL 755 const E1000E_RCTL_EN: u32 = 1 << 1; 756 const E1000E_RCTL_BAM: u32 = 1 << 15; 757 const E1000E_RCTL_BSIZE_4K: u32 = 3 << 16; 758 const E1000E_RCTL_BSEX: u32 = 1 << 25; 759 const E1000E_RCTL_SECRC: u32 = 1 << 26; 760 761 // TCTL 762 const E1000E_TCTL_EN: u32 = 1 << 1; 763 const E1000E_TCTL_PSP: u32 = 1 << 3; 764 const E1000E_TCTL_CT_VAL: u32 = 0x0f << 4; // suggested 16d collision, 手册建议值：16d 765 const E1000E_TCTL_COLD_VAL: u32 = 0x03f << 12; // suggested 64 byte time for Full-Duplex, 手册建议值：64 766 // TXDCTL 767 const E1000E_TXDCTL_WTHRESH: u32 = 1 << 16; 768 const E1000E_TXDCTL_GRAN: u32 = 1 << 24; 769 // TIPG 770 const E1000E_TIPG_IPGT: u32 = 8; 771 const E1000E_TIPG_IPGR1: u32 = 2 << 10; 772 const E1000E_TIPG_IPGR2: u32 = 10 << 20; 773 774 // RxDescriptorStatus 775 const E1000E_RXD_STATUS_DD: u16 = 1 << 0; 776 777 // TxDescriptorStatus 778 const E1000E_TXD_STATUS_DD: u8 = 1 << 0; 779 const E1000E_TXD_CMD_EOP: u8 = 1 << 0; 780 const E1000E_TXD_CMD_IFCS: u8 = 1 << 1; 781 const E1000E_TXD_CMD_RS: u8 = 1 << 3; 782 783 /// E1000E驱动初始化过程中可能的错误 784 #[allow(dead_code)] 785 pub enum E1000EPciError { 786 // 获取到错误类型的BAR（IO BAR） 787 // An IO BAR was provided rather than a memory BAR. 788 UnexpectedBarType, 789 // 获取的BAR没有被分配到某个地址(address == 0) 790 // A BAR which we need was not allocated an address(address == 0). 791 BarNotAllocated, 792 //获取虚拟地址失败 793 BarGetVaddrFailed, 794 // 没有对应的BAR或者获取BAR失败 795 BarGetFailed, 796 // BAR的大小与预期不符(128KB) 797 // Size of BAR is not 128KB 798 UnexpectedBarSize, 799 Pci(PciError), 800 } 801 802 /// PCI error到VirtioPciError的转换，层层上报 803 impl From<PciError> for E1000EPciError { 804 fn from(error: PciError) -> Self { 805 Self::Pci(error) 806 } 807 } 808 809 /** 810 * @brief 获取基地址的某个偏移量的指针，用于在mmio bar中构造寄存器结构体 811 * @brief used for build register struct in mmio bar 812 * @param vaddr: base address (in virtual memory) 813 * @param offset: offset 814 */ 815 fn get_register_ptr<T>(vaddr: u64, offset: u64) -> NonNull<T> { 816 NonNull::new((vaddr + offset) as *mut T).unwrap() 817 } 818