1 use core::{intrinsics::size_of, ptr}; 2 3 use core::sync::atomic::compiler_fence; 4 5 use crate::mm::phys_2_virt; 6 7 /// 文件说明: 实现了 AHCI 中的控制器 HBA 的相关行为 8 9 /// 根据 AHCI 写出 HBA 的 Command 10 pub const ATA_CMD_READ_DMA_EXT: u8 = 0x25; // 读操作，并且退出 11 pub const ATA_CMD_WRITE_DMA_EXT: u8 = 0x35; // 写操作，并且退出 12 #[allow(dead_code)] 13 pub const ATA_CMD_IDENTIFY: u8 = 0xEC; 14 #[allow(dead_code)] 15 pub const ATA_CMD_IDENTIFY_PACKET: u8 = 0xA1; 16 #[allow(dead_code)] 17 pub const ATA_CMD_PACKET: u8 = 0xA0; 18 pub const ATA_DEV_BUSY: u8 = 0x80; 19 pub const ATA_DEV_DRQ: u8 = 0x08; 20 21 pub const HBA_PORT_CMD_CR: u32 = 1 << 15; 22 pub const HBA_PORT_CMD_FR: u32 = 1 << 14; 23 pub const HBA_PORT_CMD_FRE: u32 = 1 << 4; 24 pub const HBA_PORT_CMD_ST: u32 = 1; 25 #[allow(dead_code)] 26 pub const HBA_PORT_IS_ERR: u32 = 1 << 30 | 1 << 29 | 1 << 28 | 1 << 27; 27 pub const HBA_SSTS_PRESENT: u32 = 0x3; 28 pub const HBA_SIG_ATA: u32 = 0x00000101; 29 pub const HBA_SIG_ATAPI: u32 = 0xEB140101; 30 pub const HBA_SIG_PM: u32 = 0x96690101; 31 pub const HBA_SIG_SEMB: u32 = 0xC33C0101; 32 33 /// 接入 Port 的 不同设备类型 34 #[derive(Debug)] 35 pub enum HbaPortType { 36 None, 37 Unknown(u32), 38 SATA, 39 SATAPI, 40 PM, 41 SEMB, 42 } 43 44 /// 声明了 HBA 的所有属性 45 #[repr(packed)] 46 pub struct HbaPort { 47 pub clb: u64, // 0x00, command list base address, 1K-byte aligned 48 pub fb: u64, // 0x08, FIS base address, 256-byte aligned 49 pub is: u32, // 0x10, interrupt status 50 pub ie: u32, // 0x14, interrupt enable 51 pub cmd: u32, // 0x18, command and status 52 pub _rsv0: u32, // 0x1C, Reserved 53 pub tfd: u32, // 0x20, task file data 54 pub sig: u32, // 0x24, signature 55 pub ssts: u32, // 0x28, SATA status (SCR0:SStatus) 56 pub sctl: u32, // 0x2C, SATA control (SCR2:SControl) 57 pub serr: u32, // 0x30, SATA error (SCR1:SError) 58 pub sact: u32, // 0x34, SATA active (SCR3:SActive) 59 pub ci: u32, // 0x38, command issue 60 pub sntf: u32, // 0x3C, SATA notification (SCR4:SNotification) 61 pub fbs: u32, // 0x40, FIS-based switch control 62 pub _rsv1: [u32; 11], // 0x44 ~ 0x6F, Reserved 63 pub vendor: [u32; 4], // 0x70 ~ 0x7F, vendor specific 64 } 65 66 /// 全称 HBA Memory Register，是HBA的寄存器在内存中的映射 67 #[repr(packed)] 68 pub struct HbaMem { 69 pub cap: u32, // 0x00, Host capability 70 pub ghc: u32, // 0x04, Global host control 71 pub is: u32, // 0x08, Interrupt status 72 pub pi: u32, // 0x0C, Port implemented 73 pub vs: u32, // 0x10, Version 74 pub ccc_ctl: u32, // 0x14, Command completion coalescing control 75 pub ccc_pts: u32, // 0x18, Command completion coalescing ports 76 pub em_loc: u32, // 0x1C, Enclosure management location 77 pub em_ctl: u32, // 0x20, Enclosure management control 78 pub cap2: u32, // 0x24, Host capabilities extended 79 pub bohc: u32, // 0x28, BIOS/OS handoff control and status 80 pub _rsv: [u8; 116], // 0x2C - 0x9F, Reserved 81 pub vendor: [u8; 96], // 0xA0 - 0xFF, Vendor specific registers 82 pub ports: [HbaPort; 32], // 0x100 - 0x10FF, Port control registers 83 } 84 85 /// HBA Command Table 里面的 PRDT 项 86 /// 作用: 记录了内存中读/写数据的位置，以及长度。你可以把他类比成一个指针？ 87 #[repr(packed)] 88 pub struct HbaPrdtEntry { 89 pub dba: u64, // Data base address 90 _rsv0: u32, // Reserved 91 pub dbc: u32, // Byte count, 4M max, interrupt = 1 92 } 93 94 /// HAB Command Table 95 /// 每个 Port 一个 Table，主机和设备的交互都靠这个数据结构 96 #[repr(packed)] 97 pub struct HbaCmdTable { 98 // 0x00 99 pub cfis: [u8; 64], // Command FIS 100 // 0x40 101 pub acmd: [u8; 16], // ATAPI command, 12 or 16 bytes 102 // 0x50 103 _rsv: [u8; 48], // Reserved 104 // 0x80 105 pub prdt_entry: [HbaPrdtEntry; 8], // Physical region descriptor table entries, 0 ~ 65535, 需要注意不要越界 这里设置8的原因是，目前CmdTable只预留了8个PRDT项的空间 106 } 107 108 /// HBA Command Header 109 /// 作用: 你可以把他类比成 Command Table 的指针。 110 /// 猜测: 这里多了一层 Header，而不是直接在 HbaMem 结构体指向 CmdTable，可能是为了兼容和可移植性？ 111 #[repr(packed)] 112 pub struct HbaCmdHeader { 113 // DW0 114 pub cfl: u8, 115 // Command FIS length in DWORDS: 5(len in [2, 16]), atapi: 1, write - host to device: 1, prefetchable: 1 116 pub _pm: u8, // Reset - 0x80, bist: 0x40, clear busy on ok: 0x20, port multiplier 117 pub prdtl: u16, // Physical region descriptor table length in entries 118 // DW1 119 pub _prdbc: u32, // Physical region descriptor byte count transferred 120 // DW2, 3 121 pub ctba: u64, // Command table descriptor base address 122 // DW4 - 7 123 pub _rsv1: [u32; 4], // Reserved 124 } 125 126 /// Port 的函数实现 127 impl HbaPort { 128 /// 获取设备类型 129 pub fn check_type(&mut self) -> HbaPortType { 130 if volatile_read!(self.ssts) & HBA_SSTS_PRESENT > 0 { 131 let sig = volatile_read!(self.sig); 132 match sig { 133 HBA_SIG_ATA => HbaPortType::SATA, 134 HBA_SIG_ATAPI => HbaPortType::SATAPI, 135 HBA_SIG_PM => HbaPortType::PM, 136 HBA_SIG_SEMB => HbaPortType::SEMB, 137 _ => HbaPortType::Unknown(sig), 138 } 139 } else { 140 HbaPortType::None 141 } 142 } 143 144 /// 启动该端口的命令引擎 145 pub fn start(&mut self) { 146 while volatile_read!(self.cmd) & HBA_PORT_CMD_CR > 0 { 147 core::hint::spin_loop(); 148 } 149 let val: u32 = volatile_read!(self.cmd) | HBA_PORT_CMD_FRE | HBA_PORT_CMD_ST; 150 volatile_write!(self.cmd, val); 151 } 152 153 /// 关闭该端口的命令引擎 154 pub fn stop(&mut self) { 155 #[allow(unused_unsafe)] 156 { 157 volatile_write!( 158 self.cmd, 159 (u32::MAX ^ HBA_PORT_CMD_ST) & volatile_read!(self.cmd) 160 ); 161 } 162 163 while volatile_read!(self.cmd) & (HBA_PORT_CMD_FR | HBA_PORT_CMD_CR) 164 == (HBA_PORT_CMD_FR | HBA_PORT_CMD_CR) 165 { 166 core::hint::spin_loop(); 167 } 168 169 #[allow(unused_unsafe)] 170 { 171 volatile_write!( 172 self.cmd, 173 (u32::MAX ^ HBA_PORT_CMD_FRE) & volatile_read!(self.cmd) 174 ); 175 } 176 } 177 178 /// @return: 返回一个空闲 cmd table 的 id; 如果没有，则返回 Option::None 179 pub fn find_cmdslot(&self) -> Option<u32> { 180 let slots = volatile_read!(self.sact) | volatile_read!(self.ci); 181 (0..32).find(|&i| slots & 1 << i == 0) 182 } 183 184 /// 初始化, 把 CmdList 等变量的地址赋值到 HbaPort 上 - 这些空间由操作系统分配且固定 185 /// 等价于原C版本的 port_rebase 函数 186 pub fn init(&mut self, clb: u64, fb: u64, ctbas: &[u64]) { 187 self.stop(); // 先暂停端口 188 189 // 赋值 command list base address 190 // Command list offset: 1K*portno 191 // Command list entry size = 32 192 // Command list entry maxim count = 32 193 // Command list maxim size = 32*32 = 1K per port 194 volatile_write!(self.clb, clb); 195 196 unsafe { 197 compiler_fence(core::sync::atomic::Ordering::SeqCst); 198 ptr::write_bytes(phys_2_virt(clb as usize) as *mut u64, 0, 1024); 199 } 200 201 // 赋值 fis base address 202 // FIS offset: 32K+256*portno 203 // FIS entry size = 256 bytes per port 204 volatile_write!(self.fb, fb); 205 unsafe { 206 compiler_fence(core::sync::atomic::Ordering::SeqCst); 207 ptr::write_bytes(phys_2_virt(fb as usize) as *mut u64, 0, 256); 208 } 209 210 // 赋值 command table base address 211 // Command table offset: 40K + 8K*portno 212 // Command table size = 256*32 = 8K per port 213 let mut cmdheaders = phys_2_virt(clb as usize) as *mut u64 as *mut HbaCmdHeader; 214 for ctbas_value in ctbas.iter().take(32) { 215 volatile_write!((*cmdheaders).prdtl, 0); // 一开始没有询问，prdtl = 0（预留了8个PRDT项的空间） 216 volatile_write!((*cmdheaders).ctba, *ctbas_value); 217 // 这里限制了 prdtl <= 8, 所以一共用了256bytes，如果需要修改，可以修改这里 218 compiler_fence(core::sync::atomic::Ordering::SeqCst); 219 unsafe { 220 ptr::write_bytes(phys_2_virt(*ctbas_value as usize) as *mut u64, 0, 256); 221 } 222 cmdheaders = (cmdheaders as usize + size_of::<HbaCmdHeader>()) as *mut HbaCmdHeader; 223 } 224 225 #[allow(unused_unsafe)] 226 { 227 // 启动中断 228 volatile_write!(self.ie, 0 /*TODO: Enable interrupts: 0b10111*/); 229 230 // 错误码 231 volatile_write!(self.serr, volatile_read!(self.serr)); 232 233 // Disable power management 234 volatile_write!(self.sctl, volatile_read!(self.sctl) | 7 << 8); 235 236 // Power on and spin up device 237 volatile_write!(self.cmd, volatile_read!(self.cmd) | 1 << 2 | 1 << 1); 238 } 239 self.start(); // 重新开启端口 240 } 241 } 242 243 #[repr(u8)] 244 #[allow(dead_code)] 245 pub enum FisType { 246 /// Register FIS - host to device 247 RegH2D = 0x27, 248 /// Register FIS - device to host 249 RegD2H = 0x34, 250 /// DMA activate FIS - device to host 251 DmaAct = 0x39, 252 /// DMA setup FIS - bidirectional 253 DmaSetup = 0x41, 254 /// Data FIS - bidirectional 255 Data = 0x46, 256 /// BIST activate FIS - bidirectional 257 Bist = 0x58, 258 /// PIO setup FIS - device to host 259 PioSetup = 0x5F, 260 /// Set device bits FIS - device to host 261 DevBits = 0xA1, 262 } 263 264 #[repr(packed)] 265 pub struct FisRegH2D { 266 // DWORD 0 267 pub fis_type: u8, // FIS_TYPE_REG_H2D 268 269 pub pm: u8, // Port multiplier, 1: Command, 0: Control 270 // uint8_t pmport : 4; // Port multiplier 低4位 271 // uint8_t rsv0 : 3; // Reserved 272 // uint8_t c : 1; // 1: Command, 0: Control 273 pub command: u8, // Command register 274 pub featurel: u8, // Feature register, 7:0 275 276 // DWORD 1 277 pub lba0: u8, // LBA low register, 7:0 278 pub lba1: u8, // LBA mid register, 15:8 279 pub lba2: u8, // LBA high register, 23:16 280 pub device: u8, // Device register 281 282 // DWORD 2 283 pub lba3: u8, // LBA register, 31:24 284 pub lba4: u8, // LBA register, 39:32 285 pub lba5: u8, // LBA register, 47:40 286 pub featureh: u8, // Feature register, 15:8 287 288 // DWORD 3 289 pub countl: u8, // Count register, 7:0 290 pub counth: u8, // Count register, 15:8 291 pub icc: u8, // Isochronous command completion 292 pub control: u8, // Control register 293 294 // DWORD 4 295 pub rsv1: [u8; 4], // Reserved 296 } 297 298 #[repr(packed)] 299 #[allow(dead_code)] 300 pub struct FisRegD2H { 301 // DWORD 0 302 pub fis_type: u8, // FIS_TYPE_REG_D2H 303 304 pub pm: u8, // Port multiplier, Interrupt bit: 2 305 306 pub status: u8, // Status register 307 pub error: u8, // Error register 308 309 // DWORD 1 310 pub lba0: u8, // LBA low register, 7:0 311 pub lba1: u8, // LBA mid register, 15:8 312 pub lba2: u8, // LBA high register, 23:16 313 pub device: u8, // Device register 314 315 // DWORD 2 316 pub lba3: u8, // LBA register, 31:24 317 pub lba4: u8, // LBA register, 39:32 318 pub lba5: u8, // LBA register, 47:40 319 pub rsv2: u8, // Reserved 320 321 // DWORD 3 322 pub countl: u8, // Count register, 7:0 323 pub counth: u8, // Count register, 15:8 324 pub rsv3: [u8; 2], // Reserved 325 326 // DWORD 4 327 pub rsv4: [u8; 4], // Reserved 328 } 329 330 #[repr(packed)] 331 #[allow(dead_code)] 332 pub struct FisData { 333 // DWORD 0 334 pub fis_type: u8, // FIS_TYPE_DATA 335 336 pub pm: u8, // Port multiplier 337 338 pub rsv1: [u8; 2], // Reserved 339 340 // DWORD 1 ~ N 341 pub data: [u8; 252], // Payload 342 } 343 344 #[repr(packed)] 345 #[allow(dead_code)] 346 pub struct FisPioSetup { 347 // DWORD 0 348 pub fis_type: u8, // FIS_TYPE_PIO_SETUP 349 350 pub pm: u8, // Port multiplier, direction: 4 - device to host, interrupt: 2 351 352 pub status: u8, // Status register 353 pub error: u8, // Error register 354 355 // DWORD 1 356 pub lba0: u8, // LBA low register, 7:0 357 pub lba1: u8, // LBA mid register, 15:8 358 pub lba2: u8, // LBA high register, 23:16 359 pub device: u8, // Device register 360 361 // DWORD 2 362 pub lba3: u8, // LBA register, 31:24 363 pub lba4: u8, // LBA register, 39:32 364 pub lba5: u8, // LBA register, 47:40 365 pub rsv2: u8, // Reserved 366 367 // DWORD 3 368 pub countl: u8, // Count register, 7:0 369 pub counth: u8, // Count register, 15:8 370 pub rsv3: u8, // Reserved 371 pub e_status: u8, // New value of status register 372 373 // DWORD 4 374 pub tc: u16, // Transfer count 375 pub rsv4: [u8; 2], // Reserved 376 } 377 378 #[repr(packed)] 379 #[allow(dead_code)] 380 pub struct FisDmaSetup { 381 // DWORD 0 382 pub fis_type: u8, // FIS_TYPE_DMA_SETUP 383 384 pub pm: u8, // Port multiplier, direction: 4 - device to host, interrupt: 2, auto-activate: 1 385 386 pub rsv1: [u8; 2], // Reserved 387 388 // DWORD 1&2 389 pub dma_buffer_id: u64, /* DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work. */ 390 391 // DWORD 3 392 pub rsv3: u32, // More reserved 393 394 // DWORD 4 395 pub dma_buffer_offset: u32, // Byte offset into buffer. First 2 bits must be 0 396 397 // DWORD 5 398 pub transfer_count: u32, // Number of bytes to transfer. Bit 0 must be 0 399 400 // DWORD 6 401 pub rsv6: u32, // Reserved 402 } 403