1e2841179SLoGin use bitfield_struct::bitfield; 2e2841179SLoGin 3e2841179SLoGin #[allow(dead_code)] 4e2841179SLoGin #[derive(Debug)] 5e2841179SLoGin pub enum X86MsiData { 6e2841179SLoGin Normal(X86MsiDataNormal), 7e2841179SLoGin Dmar(X86MsiDataDmar), 8e2841179SLoGin } 9e2841179SLoGin 10e2841179SLoGin #[bitfield(u32)] 11e2841179SLoGin pub struct X86MsiDataNormal { 12e2841179SLoGin #[bits(8)] 13e2841179SLoGin pub vector: u8, 14e2841179SLoGin #[bits(3)] 15e2841179SLoGin pub delivery_mode: u8, 16e2841179SLoGin #[bits(1)] 17e2841179SLoGin pub dest_mode_logical: bool, 18e2841179SLoGin #[bits(2)] 19e2841179SLoGin reserved: u8, 20e2841179SLoGin #[bits(1)] 21e2841179SLoGin pub active_low: bool, 22e2841179SLoGin #[bits(1)] 23e2841179SLoGin pub is_level_triggered: bool, 24e2841179SLoGin #[bits(16)] 25e2841179SLoGin reserved2: u16, 26e2841179SLoGin } 27e2841179SLoGin 28e2841179SLoGin #[derive(Debug)] 29*bd70d2d1SLoGin #[allow(dead_code)] 30e2841179SLoGin pub struct X86MsiDataDmar { 31e2841179SLoGin pub dmar_subhandle: u32, 32e2841179SLoGin } 33e2841179SLoGin 34e2841179SLoGin impl X86MsiDataDmar { 35e2841179SLoGin #[allow(dead_code)] new(dmar_subhandle: u32) -> Self36e2841179SLoGin pub const fn new(dmar_subhandle: u32) -> Self { 37e2841179SLoGin X86MsiDataDmar { dmar_subhandle } 38e2841179SLoGin } 39e2841179SLoGin } 40e2841179SLoGin 41e2841179SLoGin pub const X86_MSI_BASE_ADDRESS_LOW: u32 = 0xfee00000 >> 20; 42e2841179SLoGin 43e2841179SLoGin #[allow(dead_code)] 44e2841179SLoGin #[derive(Debug)] 45e2841179SLoGin pub enum X86MsiAddrLo { 46e2841179SLoGin Normal(X86MsiAddrLoNormal), 47e2841179SLoGin Dmar(X86MsiAddrLoDmar), 48e2841179SLoGin } 49e2841179SLoGin 50e2841179SLoGin #[bitfield(u32)] 51e2841179SLoGin pub struct X86MsiAddrLoNormal { 52e2841179SLoGin #[bits(2)] 53e2841179SLoGin reserved_0: u32, 54e2841179SLoGin #[bits(1)] 55e2841179SLoGin pub dest_mode_logical: bool, 56e2841179SLoGin #[bits(1)] 57e2841179SLoGin pub redirecti_hint: bool, 58e2841179SLoGin #[bits(1)] 59e2841179SLoGin reserved_1: bool, 60e2841179SLoGin #[bits(7)] 61e2841179SLoGin pub virt_destid_8_14: u32, 62e2841179SLoGin #[bits(8)] 63e2841179SLoGin pub destid_0_7: u32, 64e2841179SLoGin #[bits(12)] 65e2841179SLoGin pub base_address: u32, 66e2841179SLoGin } 67e2841179SLoGin 68e2841179SLoGin #[bitfield(u32)] 69e2841179SLoGin pub struct X86MsiAddrLoDmar { 70e2841179SLoGin #[bits(2)] 71e2841179SLoGin reserved_0: u32, 72e2841179SLoGin #[bits(1)] 73e2841179SLoGin pub index_15: bool, 74e2841179SLoGin #[bits(1)] 75e2841179SLoGin pub subhandle_valid: bool, 76e2841179SLoGin #[bits(1)] 77e2841179SLoGin pub format: bool, 78e2841179SLoGin #[bits(15)] 79e2841179SLoGin pub index_0_14: u32, 80e2841179SLoGin #[bits(12)] 81e2841179SLoGin pub base_address: u32, 82e2841179SLoGin } 83e2841179SLoGin 84e2841179SLoGin #[bitfield(u32)] 85e2841179SLoGin pub struct X86MsiAddrHi { 86e2841179SLoGin #[bits(8)] 87e2841179SLoGin reserved: u32, 88e2841179SLoGin #[bits(24)] 89e2841179SLoGin pub destid_8_31: u32, 90e2841179SLoGin } 91