1 use core::intrinsics::unlikely; 2 3 use alloc::{string::ToString, sync::Arc}; 4 use intertrait::CastFrom; 5 use system_error::SystemError; 6 7 use crate::{ 8 arch::{ 9 driver::apic::{ 10 apic_timer::{local_apic_timer_irq_desc_init, APIC_TIMER_IRQ_NUM}, 11 ioapic::ioapic_init, 12 }, 13 interrupt::{ 14 entry::arch_setup_interrupt_gate, 15 ipi::{arch_ipi_handler_init, send_ipi, IPI_NUM_FLUSH_TLB, IPI_NUM_KICK_CPU}, 16 msi::{X86MsiAddrHi, X86MsiAddrLoNormal, X86MsiDataNormal, X86_MSI_BASE_ADDRESS_LOW}, 17 }, 18 }, 19 driver::open_firmware::device_node::DeviceNode, 20 exception::{ 21 ipi::{IpiKind, IpiTarget}, 22 irqchip::{IrqChip, IrqChipData, IrqChipFlags}, 23 irqdata::IrqData, 24 irqdomain::{irq_domain_manager, IrqDomain, IrqDomainBusToken, IrqDomainOps}, 25 msi::MsiMsg, 26 HardwareIrqNumber, IrqNumber, 27 }, 28 kwarn, 29 libs::spinlock::{SpinLock, SpinLockGuard}, 30 smp::{core::smp_get_processor_id, cpu::ProcessorId}, 31 }; 32 33 use super::{hw_irq::HardwareIrqConfig, CurrentApic, LocalAPIC}; 34 35 static mut LOCAL_APIC_CHIP: Option<Arc<LocalApicChip>> = None; 36 37 pub fn local_apic_chip() -> &'static Arc<LocalApicChip> { 38 unsafe { LOCAL_APIC_CHIP.as_ref().unwrap() } 39 } 40 41 #[derive(Debug)] 42 pub struct LocalApicChip { 43 inner: SpinLock<InnerIrqChip>, 44 } 45 46 impl LocalApicChip { 47 pub fn new() -> Self { 48 Self { 49 inner: SpinLock::new(InnerIrqChip { 50 flags: IrqChipFlags::empty(), 51 }), 52 } 53 } 54 } 55 56 impl IrqChip for LocalApicChip { 57 fn name(&self) -> &'static str { 58 "APIC" 59 } 60 61 fn can_set_flow_type(&self) -> bool { 62 false 63 } 64 65 fn irq_disable(&self, _irq: &Arc<IrqData>) {} 66 67 fn irq_ack(&self, _irq: &Arc<IrqData>) { 68 CurrentApic.send_eoi(); 69 } 70 71 fn can_set_affinity(&self) -> bool { 72 false 73 } 74 75 fn can_mask_ack(&self) -> bool { 76 false 77 } 78 79 fn irq_enable(&self, _irq: &Arc<IrqData>) -> Result<(), SystemError> { 80 // 这里临时处理，后续需要修改 81 return Ok(()); 82 } 83 84 fn irq_unmask(&self, _irq: &Arc<IrqData>) -> Result<(), SystemError> { 85 Ok(()) 86 } 87 88 fn irq_compose_msi_msg(&self, irq: &Arc<IrqData>, msg: &mut MsiMsg) { 89 let chip_data = irq.chip_info_read_irqsave().chip_data().unwrap(); 90 let apicd = chip_data.ref_any().downcast_ref::<ApicChipData>().unwrap(); 91 let cfg = &apicd.inner().hw_irq_cfg; 92 irq_msi_compose_msg(cfg, msg, false); 93 } 94 95 fn retrigger(&self, irq: &Arc<IrqData>) -> Result<(), SystemError> { 96 let chip_data = irq 97 .chip_info_read_irqsave() 98 .chip_data() 99 .ok_or(SystemError::EINVAL)?; 100 let apicd = chip_data 101 .ref_any() 102 .downcast_ref::<ApicChipData>() 103 .ok_or(SystemError::EINVAL)?; 104 let inner = apicd.inner(); 105 106 send_ipi( 107 IpiKind::SpecVector(inner.vector), 108 IpiTarget::Specified(inner.cpu), 109 ); 110 111 Ok(()) 112 } 113 114 fn flags(&self) -> IrqChipFlags { 115 self.inner.lock_irqsave().flags 116 } 117 } 118 119 #[derive(Debug)] 120 struct InnerIrqChip { 121 flags: IrqChipFlags, 122 } 123 124 #[derive(Debug)] 125 struct ApicChipData { 126 inner: SpinLock<InnerApicChipData>, 127 } 128 129 impl ApicChipData { 130 #[allow(dead_code)] 131 pub fn new( 132 hw_irq_cfg: HardwareIrqConfig, 133 irq: IrqNumber, 134 vector: HardwareIrqNumber, 135 cpu: ProcessorId, 136 ) -> Self { 137 Self { 138 inner: SpinLock::new(InnerApicChipData { 139 hw_irq_cfg, 140 irq, 141 vector, 142 prev_vector: None, 143 cpu, 144 prev_cpu: None, 145 status: ApicChipStatus::empty(), 146 }), 147 } 148 } 149 150 pub fn inner(&self) -> SpinLockGuard<InnerApicChipData> { 151 self.inner.lock_irqsave() 152 } 153 } 154 155 #[allow(dead_code)] 156 #[derive(Debug)] 157 struct InnerApicChipData { 158 hw_irq_cfg: HardwareIrqConfig, 159 irq: IrqNumber, 160 vector: HardwareIrqNumber, 161 prev_vector: Option<HardwareIrqNumber>, 162 cpu: ProcessorId, 163 prev_cpu: Option<ProcessorId>, 164 status: ApicChipStatus, 165 } 166 167 impl IrqChipData for ApicChipData { 168 fn as_any_ref(&self) -> &dyn core::any::Any { 169 self 170 } 171 } 172 173 bitflags! { 174 pub struct ApicChipStatus: u32 { 175 const MOVE_IN_PROGRESS = 1 << 0; 176 const IS_MANAGED = 1 << 1; 177 const CAN_RESERVE = 1 << 2; 178 const HAS_RESERVED = 1 << 3; 179 } 180 } 181 182 pub(super) fn irq_msi_compose_msg(cfg: &HardwareIrqConfig, msg: &mut MsiMsg, dmar: bool) { 183 *msg = MsiMsg::new_zeroed(); 184 185 let arch_data = X86MsiDataNormal::new() 186 .with_delivery_mode(x86::apic::DeliveryMode::Fixed as u8) 187 .with_vector((cfg.vector.data() & 0xff) as u8); 188 let mut address_lo = X86MsiAddrLoNormal::new() 189 .with_base_address(X86_MSI_BASE_ADDRESS_LOW) 190 .with_dest_mode_logical(false) 191 .with_destid_0_7(cfg.apic_id.data() & 0xff); 192 193 let mut address_hi = X86MsiAddrHi::new(); 194 195 /* 196 * 只有IOMMU本身可以使用将目标APIC ID放入地址的高位的技术。 197 * 任何其他尝试这样做的东西都只是在写内存，并且需要IR来 198 * 寻址不能在正常的32位地址范围内0xFFExxxxx寻址的APIC。 199 * 这通常是8位，但一些虚拟化程序允许在位5-11使用扩展的目的地ID字段， 200 * 总共支持15位的APIC ID。 201 */ 202 if dmar { 203 address_hi.set_destid_8_31(cfg.apic_id.data() >> 8); 204 } else if cfg.apic_id.data() < 0x8000 { 205 // todo: 判断vmx是否支持 extended destination mode 206 // 参考 https://code.dragonos.org.cn/xref/linux-6.1.9/arch/x86/kernel/apic/apic.c?fi=__irq_msi_compose_msg#2580 207 address_lo.set_virt_destid_8_14(cfg.apic_id.data() >> 8); 208 } else { 209 if unlikely(cfg.apic_id.data() > 0xff) { 210 kwarn!( 211 "irq_msi_compose_msg: Invalid APIC ID: {}", 212 cfg.apic_id.data() 213 ); 214 } 215 } 216 msg.address_hi = address_hi.into(); 217 msg.address_lo = address_lo.into(); 218 msg.data = arch_data.into(); 219 } 220 221 static mut X86_VECTOR_DOMAIN: Option<Arc<IrqDomain>> = None; 222 223 #[inline(always)] 224 #[allow(dead_code)] 225 pub fn x86_vector_domain() -> &'static Arc<IrqDomain> { 226 unsafe { X86_VECTOR_DOMAIN.as_ref().unwrap() } 227 } 228 229 #[inline(never)] 230 pub fn arch_early_irq_init() -> Result<(), SystemError> { 231 let vec_domain = irq_domain_manager() 232 .create_and_add( 233 "VECTOR".to_string(), 234 &X86VectorDomainOps, 235 IrqNumber::new(32), 236 HardwareIrqNumber::new(32), 237 223, 238 ) 239 .ok_or(SystemError::ENOMEM)?; 240 irq_domain_manager().set_default_domain(vec_domain.clone()); 241 unsafe { X86_VECTOR_DOMAIN = Some(vec_domain) }; 242 243 let apic_chip = Arc::new(LocalApicChip::new()); 244 245 unsafe { LOCAL_APIC_CHIP = Some(apic_chip) }; 246 247 // todo: add vector matrix 248 // 参考 https://code.dragonos.org.cn/xref/linux-6.1.9/arch/x86/kernel/apic/vector.c#803 249 kwarn!("arch_early_irq_init: todo: add vector matrix"); 250 251 local_apic_timer_irq_desc_init(); 252 arch_ipi_handler_init(); 253 CurrentApic.init_current_cpu(); 254 if smp_get_processor_id().data() == 0 { 255 unsafe { arch_setup_interrupt_gate() }; 256 ioapic_init(&[APIC_TIMER_IRQ_NUM, IPI_NUM_KICK_CPU, IPI_NUM_FLUSH_TLB]); 257 } 258 return Ok(()); 259 } 260 261 /// x86的中断域操作 262 /// 263 /// 参考 https://code.dragonos.org.cn/xref/linux-6.1.9/arch/x86/kernel/apic/vector.c#693 264 #[derive(Debug)] 265 struct X86VectorDomainOps; 266 267 impl IrqDomainOps for X86VectorDomainOps { 268 fn match_node( 269 &self, 270 _irq_domain: &Arc<IrqDomain>, 271 _device_node: &Arc<DeviceNode>, 272 _bus_token: IrqDomainBusToken, 273 ) -> bool { 274 todo!() 275 } 276 277 fn map( 278 &self, 279 _irq_domain: &Arc<IrqDomain>, 280 _hwirq: HardwareIrqNumber, 281 _virq: IrqNumber, 282 ) -> Result<(), SystemError> { 283 Err(SystemError::ENOSYS) 284 } 285 286 fn unmap(&self, _irq_domain: &Arc<IrqDomain>, _virq: IrqNumber) { 287 todo!() 288 } 289 } 290