12dd9f0c7SLoGin use crate::{ 2*370472f7SLoGin driver::pci::pci::{BusDeviceFunction, PciAddr}, 32dd9f0c7SLoGin mm::PhysAddr, 42dd9f0c7SLoGin }; 540fe15e0SLoGin 64fda81ceSLoGin #[cfg(target_arch = "x86_64")] 74fda81ceSLoGin pub mod x86_64; 84fda81ceSLoGin #[cfg(target_arch = "x86_64")] 94fda81ceSLoGin pub use self::x86_64::*; // 公开x86_64架构下的函数，使外界接口统一 104fda81ceSLoGin 114fda81ceSLoGin #[cfg(target_arch = "riscv64")] 124fda81ceSLoGin pub mod riscv64; 134fda81ceSLoGin #[cfg(target_arch = "riscv64")] 144fda81ceSLoGin pub use self::riscv64::*; // 公开riscv64架构下的函数，使外界接口统一 154fda81ceSLoGin 16a03c4f9dSLoGin pub mod io; 17a03c4f9dSLoGin 1878bf93f0SYJwu2023 /// TraitPciArch Pci架构相关函数，任何架构都应独立实现trait里的函数 1978bf93f0SYJwu2023 pub trait TraitPciArch { 2078bf93f0SYJwu2023 /// @brief 读取寄存器值，x86_64架构通过读取两个特定io端口实现 2178bf93f0SYJwu2023 /// @param bus_device_function 设备的唯一标识符 2278bf93f0SYJwu2023 /// @param offset 寄存器偏移值 2378bf93f0SYJwu2023 /// @return 读取到的值 read_config(bus_device_function: &BusDeviceFunction, offset: u8) -> u322478bf93f0SYJwu2023 fn read_config(bus_device_function: &BusDeviceFunction, offset: u8) -> u32; 2578bf93f0SYJwu2023 /// @brief 写入寄存器值，x86_64架构通过读取两个特定io端口实现 2678bf93f0SYJwu2023 /// @param bus_device_function 设备的唯一标识符 2778bf93f0SYJwu2023 /// @param offset 寄存器偏移值 2878bf93f0SYJwu2023 /// @param data 要写入的值 write_config(bus_device_function: &BusDeviceFunction, offset: u8, data: u32)2978bf93f0SYJwu2023 fn write_config(bus_device_function: &BusDeviceFunction, offset: u8, data: u32); 3078bf93f0SYJwu2023 /// @brief PCI域地址到存储器域地址的转换,x86_64架构为一一对应 3178bf93f0SYJwu2023 /// @param address PCI域地址 325c1e552cSYJwu2023 /// @return usize 转换结果 address_pci_to_physical(pci_address: PciAddr) -> PhysAddr332dd9f0c7SLoGin fn address_pci_to_physical(pci_address: PciAddr) -> PhysAddr; 3478bf93f0SYJwu2023 } 35