Home
last modified time | relevance | path

Searched refs:mmVGA_SEQUENCER_RESET_CONTROL (Results 1 – 13 of 13) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h4394 #define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1 macro
Ddce_8_0_d.h5135 #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 macro
Ddce_10_0_d.h6018 #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 macro
Ddce_11_0_d.h6095 #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 macro
Ddce_11_2_d.h7769 #define mmVGA_SEQUENCER_RESET_CONTROL 0xc1 macro
Ddce_12_0_offset.h556 #define mmVGA_SEQUENCER_RESET_CONTROL … macro
/linux-6.6.21/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h19 #define mmVGA_SEQUENCER_RESET_CONTROL … macro
Ddcn_3_0_1_offset.h150 #define mmVGA_SEQUENCER_RESET_CONTROL … macro
Ddcn_2_1_0_offset.h90 #define mmVGA_SEQUENCER_RESET_CONTROL … macro
Ddcn_1_0_offset.h390 #define mmVGA_SEQUENCER_RESET_CONTROL … macro
Ddcn_3_0_2_offset.h34 #define mmVGA_SEQUENCER_RESET_CONTROL … macro
Ddcn_2_0_0_offset.h34 #define mmVGA_SEQUENCER_RESET_CONTROL … macro
Ddcn_3_0_0_offset.h16 #define mmVGA_SEQUENCER_RESET_CONTROL … macro