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Searched refs:dsc_dpcd (Results 1 – 6 of 6) sorted by relevance

/linux-6.6.21/include/drm/display/
Ddrm_dp_helper.h167 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
169 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
174 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_sink_supports_dsc()
176 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & in drm_dp_sink_supports_dsc()
181 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_edp_dsc_sink_output_bpp()
183 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | in drm_edp_dsc_sink_output_bpp()
184 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & in drm_edp_dsc_sink_output_bpp()
189 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_max_slice_width()
192 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * in drm_dp_dsc_sink_max_slice_width()
204 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) in drm_dp_dsc_sink_supports_format()
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/linux-6.6.21/drivers/gpu/drm/i915/display/
Dintel_dp.c829 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); in intel_dp_dsc_get_slice_count()
846 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false)) in intel_dp_dsc_get_slice_count()
1167 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { in intel_dp_mode_valid()
1180 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; in intel_dp_mode_valid()
1182 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, in intel_dp_mode_valid()
1339 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); in intel_dp_supports_dsc()
1532 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, in intel_dp_dsc_compute_bpp()
1551 return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> in intel_dp_sink_dsc_version_minor()
1602 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
1609 intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & in intel_dp_dsc_compute_params()
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Dintel_display_debugfs.c1235 str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); in i915_dsc_fec_support_show()
1237 str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, in i915_dsc_fec_support_show()
1239 str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, in i915_dsc_fec_support_show()
1241 str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, in i915_dsc_fec_support_show()
Dintel_dp_mst.c205 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, in intel_dp_dsc_mst_compute_link_config()
968 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { in intel_dp_mst_mode_valid_ctx()
Dintel_display_types.h1716 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; member
/linux-6.6.21/drivers/gpu/drm/display/
Ddrm_dp_helper.c2342 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_max_slice_count()
2345 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2357 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_max_slice_count()
2400 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) in drm_dp_dsc_sink_line_buf_depth()
2402 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_line_buf_depth()
2446 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], in drm_dp_dsc_sink_supported_input_bpcs()
2450 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; in drm_dp_dsc_sink_supported_input_bpcs()