| /linux-6.6.21/sound/soc/intel/skylake/ |
| D | skl-sst-dsp.c | 39 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; in skl_dsp_init_core_state()
40 skl->cores.usage_count[SKL_DSP_CORE0_ID] = 1; in skl_dsp_init_core_state()
42 for (i = SKL_DSP_CORE0_ID + 1; i < skl->cores.count; i++) { in skl_dsp_init_core_state()
43 skl->cores.state[i] = SKL_DSP_RESET; in skl_dsp_init_core_state()
44 skl->cores.usage_count[i] = 0; in skl_dsp_init_core_state()
55 core_mask = SKL_DSP_CORES_MASK(skl->cores.count); in skl_dsp_get_enabled_cores()
341 if (core_id >= skl->cores.count) { in skl_dsp_get_core()
346 skl->cores.usage_count[core_id]++; in skl_dsp_get_core()
348 if (skl->cores.state[core_id] == SKL_DSP_RESET) { in skl_dsp_get_core()
358 core_id, skl->cores.state[core_id], in skl_dsp_get_core()
[all …]
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| D | skl-messages.c | 256 struct skl_dsp_cores *cores; in skl_init_dsp() local
285 cores = &skl->cores; in skl_init_dsp()
286 cores->count = ops->num_cores; in skl_init_dsp()
288 cores->state = kcalloc(cores->count, sizeof(*cores->state), GFP_KERNEL); in skl_init_dsp()
289 if (!cores->state) { in skl_init_dsp()
294 cores->usage_count = kcalloc(cores->count, sizeof(*cores->usage_count), in skl_init_dsp()
296 if (!cores->usage_count) { in skl_init_dsp()
306 kfree(cores->state); in skl_init_dsp()
323 kfree(skl->cores.state); in skl_free_dsp()
324 kfree(skl->cores.usage_count); in skl_free_dsp()
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| D | bxt-sst.c | 271 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING) in bxt_d0i3_target_state()
326 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING_D0I3; in bxt_set_dsp_D0i3()
358 if (skl->cores.state[SKL_DSP_CORE0_ID] != SKL_DSP_RUNNING_D0I3) in bxt_set_dsp_D0i0()
381 skl->cores.state[SKL_DSP_CORE0_ID] = SKL_DSP_RUNNING; in bxt_set_dsp_D0i0()
410 skl->cores.state[core_id] = SKL_DSP_RUNNING; in bxt_set_dsp_D0()
472 skl->cores.state[core_id] = SKL_DSP_RUNNING; in bxt_set_dsp_D0()
518 skl->cores.state[core_id] = SKL_DSP_RESET; in bxt_set_dsp_D3()
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| /linux-6.6.21/Documentation/admin-guide/ |
| D | lockup-watchdogs.rst | 67 By default, the watchdog runs on all online cores. However, on a
69 on the housekeeping cores, not the cores specified in the "nohz_full"
71 the "nohz_full" cores, we would have to run timer ticks to activate
73 from protecting the user code on those cores from the kernel.
74 Of course, disabling it by default on the nohz_full cores means that
75 when those cores do enter the kernel, by default we will not be
77 to continue to run on the housekeeping (non-tickless) cores means
78 that we will continue to detect lockups properly on those cores.
80 In either case, the set of cores excluded from running the watchdog
82 nohz_full cores, this may be useful for debugging a case where the
[all …]
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| /linux-6.6.21/drivers/gpu/drm/nouveau/dispnv50/ |
| D | core.c | 44 } cores[] = { in nv50_core_new() local
65 cid = nvif_mclass(&disp->disp->object, cores); in nv50_core_new()
71 return cores[cid].new(drm, cores[cid].oclass, pcore); in nv50_core_new()
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| /linux-6.6.21/Documentation/devicetree/bindings/timer/ |
| D | snps,arc-timer.txt | 4 - Two identical copies TIMER0 and TIMER1 exist in ARC cores and historically
5 TIMER0 used as clockevent provider (true for all ARC cores)
12 (16 for ARCHS cores, 3 for ARC700 cores)
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| /linux-6.6.21/Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 13 For most flexcan IP cores the driver supports 2 RX modes:
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
28 cores come up in a mode where RTR reception is possible.
39 On some IP cores the controller cannot receive RTR frames in the
45 Waive ability to receive RTR frames. (not supported on all IP cores)
48 some IP cores RTR frames cannot be received anymore.
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| /linux-6.6.21/Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
10 cores are represented as defined in ../video-interfaces.txt.
18 The following properties are common to all Xilinx video IP cores.
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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| D | xlnx,video.txt | 8 video IP cores. Each video IP core is represented as documented in video.txt
11 mappings between DMAs and the video IP cores.
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| /linux-6.6.21/drivers/remoteproc/ |
| D | ti_k3_r5_remoteproc.c | 111 struct list_head cores; member
288 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
299 list_for_each_entry(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
312 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
317 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem); in k3_r5_lockstep_reset()
319 list_for_each_entry_from_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_reset()
333 list_for_each_entry_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_release()
345 list_for_each_entry_reverse(core, &cluster->cores, elem) { in k3_r5_lockstep_release()
357 list_for_each_entry_continue(core, &cluster->cores, elem) { in k3_r5_lockstep_release()
361 core = list_first_entry(&cluster->cores, struct k3_r5_core, elem); in k3_r5_lockstep_release()
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| /linux-6.6.21/Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 9 The cores on the AXI bus are automatically detected by bcma with the
12 BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide
17 The top-level axi bus may contain children representing attached cores
19 detected (e.g. IRQ numbers). Also some of the cores may be responsible
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| /linux-6.6.21/Documentation/devicetree/bindings/remoteproc/ |
| D | ti,pru-consumer.yaml | 37 firmwares for the PRU cores, the default firmware for the core from
39 correspond to the PRU cores listed in the 'ti,prus' property
50 should correspond to the PRU cores listed in the 'ti,prus' property. The
52 and Tx_PRU0 on K3 SoCs). Use the same value for all cores within the
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| /linux-6.6.21/Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
58 cores in a MPCore configuration in a test chip on the core tile. See
64 A15 CPU cores in a test chip on the core tile. This is the first test
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
77 cores in a test chip on the core tile. See ARM DDI 0498D.
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
85 cores in a big.LITTLE configuration. It also features the MALI T624
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| /linux-6.6.21/arch/riscv/ |
| D | Kconfig.errata | 9 here if your platform uses Andes CPU cores.
20 non-standard handling on non-coherent operations on Andes cores.
30 here if your platform uses SiFive CPU cores.
62 here if your platform uses T-HEAD CPU cores.
94 The T-Head C9xx cores implement a PMU overflow extension very
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| /linux-6.6.21/arch/x86/mm/ |
| D | amdtopology.c | 63 unsigned int bits, cores, apicid_base; in amd_numa_init() local
165 cores = 1 << bits; in amd_numa_init()
179 for (j = apicid_base; j < cores + apicid_base; j++) in amd_numa_init()
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| /linux-6.6.21/drivers/gpu/drm/v3d/ |
| D | v3d_irq.c | 213 for (core = 0; core < v3d->cores; core++) in v3d_irq_init()
258 for (core = 0; core < v3d->cores; core++) { in v3d_irq_enable()
273 for (core = 0; core < v3d->cores; core++) in v3d_irq_disable()
278 for (core = 0; core < v3d->cores; core++) in v3d_irq_disable()
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| D | v3d_debugfs.c | 102 for (core = 0; core < v3d->cores; core++) { in v3d_v3d_debugfs_regs()
132 u32 ident0, ident1, ident2, ident3, cores; in v3d_v3d_debugfs_ident() local
139 cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); in v3d_v3d_debugfs_ident()
158 for (core = 0; core < cores; core++) { in v3d_v3d_debugfs_ident()
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| /linux-6.6.21/drivers/bcma/ |
| D | main.c | 92 list_for_each_entry(core, &bus->cores, list) { in bcma_find_core_unit()
272 INIT_LIST_HEAD(&bus->cores); in bcma_init_bus()
296 list_for_each_entry(core, &bus->cores, list) { in bcma_register_devices()
366 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
376 list_for_each_entry_safe(core, tmp, &bus->cores, list) { in bcma_unregister_cores()
412 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_register()
537 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_suspend()
558 list_for_each_entry(core, &bus->cores, list) { in bcma_bus_resume()
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| /linux-6.6.21/sound/soc/sof/ |
| D | ipc4-mtrace.c | 124 struct sof_mtrace_core_data cores[]; member
414 debugfs_create_file(dfs_name, 0444, dfs_root, &priv->cores[i], in mtrace_debugfs_create()
492 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_disable()
528 core_data = &priv->cores[core]; in sof_mtrace_find_core_slots()
565 priv = devm_kzalloc(sdev->dev, struct_size(priv, cores, sdev->num_cores), in ipc4_mtrace_init()
579 struct sof_mtrace_core_data *core_data = &priv->cores[i]; in ipc4_mtrace_init()
634 core_data = &priv->cores[core]; in sof_ipc4_mtrace_update_pos()
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| /linux-6.6.21/arch/arm64/boot/dts/qcom/ |
| D | sdm632.dtsi | 45 * CPU0-3 are efficiency cores, CPU4-7 are performance cores
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| /linux-6.6.21/Documentation/ABI/testing/ |
| D | sysfs-bus-bcma | 14 There are a few types of BCMA cores, they can be identified by
22 BCMA cores of the same type can still slightly differ depending
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| /linux-6.6.21/arch/arm/boot/dts/arm/ |
| D | vexpress-v2p-ca15-tc1.dts | 199 volt-cores {
210 amp-cores {
211 /* Total current for the two cores */
224 power-cores {
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| /linux-6.6.21/Documentation/admin-guide/device-mapper/ |
| D | unstriped.rst | 85 Intel NVMe drives contain two cores on the physical device.
88 in a 256k stripe across the two cores::
100 are striped across the two cores. When we unstripe this hardware RAID 0
113 unstriped on top of Intel NVMe device that has 2 cores
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| /linux-6.6.21/Documentation/locking/ |
| D | percpu-rw-semaphore.rst | 9 cores take the lock for reading, the cache line containing the semaphore
10 is bouncing between L1 caches of the cores, causing performance
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| /linux-6.6.21/Documentation/devicetree/bindings/power/ |
| D | renesas,apmu.yaml | 40 Array of phandles pointing to CPU cores, which should match the order of
41 CPU cores used by the WUPCR and PSTR registers in the Advanced Power
|