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Searched refs:GRBM_GFX_INDEX (Results 1 – 25 of 31) sorted by relevance

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/linux-6.6.21/drivers/gpu/drm/amd/amdkfd/
Dcik_regs.h69 #define GRBM_GFX_INDEX 0x30800 macro
/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4.c99 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_select_se_sh()
102 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_select_se_sh()
106 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
109 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_select_se_sh()
112 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
Damdgpu_amdkfd_gfx_v8.c553 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
555 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
557 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
Damdgpu_amdkfd_gfx_v10_3.c600 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
602 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
604 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v10_3()
Dvce_v4_0.c748 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
753 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0x10);
758 WREG32_FIELD(GRBM_GFX_INDEX, INSTANCE_INDEX, 0);
940 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, i);
959 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0);
Damdgpu_amdkfd_gfx_v11.c585 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11()
587 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11()
589 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in wave_control_execute_v11()
Damdgpu_amdkfd_gfx_v10.c688 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
690 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
692 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_wave_control_execute()
Dgfx_v9_4_2.c855 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_2_select_se_sh()
858 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v9_4_2_select_se_sh()
862 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh()
865 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_2_select_se_sh()
868 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, in gfx_v9_4_2_select_se_sh()
871 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
Damdgpu_amdkfd_gfx_v9.c640 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
642 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
644 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in kgd_gfx_v9_wave_control_execute()
Dsoc15_common.h158 …dx = adev->reg_offset[GC_HWIP][inst][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \
Dgfx_v9_4_3.c529 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
532 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
536 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_4_3_xcc_select_se_sh()
542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, in gfx_v9_4_3_xcc_select_se_sh()
545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_3_xcc_select_se_sh()
Dvce_v3_0.c851 WREG32_FIELD(GRBM_GFX_INDEX, VCE_INSTANCE, 0); in vce_v3_0_get_clockgating_state()
Dgfx_v11_0.c1537 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v11_0_select_se_sh()
1540 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v11_0_select_se_sh()
1544 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v11_0_select_se_sh()
1547 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v11_0_select_se_sh()
1550 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, in gfx_v11_0_select_se_sh()
1553 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v11_0_select_se_sh()
Dgfx_v8_0.c3404 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3406 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v8_0_select_se_sh()
3409 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3411 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v8_0_select_se_sh()
3414 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v8_0_select_se_sh()
3416 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
Dgfx_v9_0.c2225 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2227 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); in gfx_v9_0_select_se_sh()
2230 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2232 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v9_0_select_se_sh()
2235 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); in gfx_v9_0_select_se_sh()
2237 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
Dsid.h996 #define GRBM_GFX_INDEX 0x200B macro
Dgfx_v10_0.c4697 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, in gfx_v10_0_select_se_sh()
4700 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, in gfx_v10_0_select_se_sh()
4704 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, in gfx_v10_0_select_se_sh()
4707 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); in gfx_v10_0_select_se_sh()
4710 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, in gfx_v10_0_select_se_sh()
4713 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
/linux-6.6.21/drivers/gpu/drm/radeon/
Dcypress_dpm.c125 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
152 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_gfx_clock_gating_enable()
186 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
207 WREG32(GRBM_GFX_INDEX, 0xC0000000); in cypress_mg_clock_gating_enable()
Dni.c1082 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1102 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in cayman_gpu_init()
1111 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in cayman_gpu_init()
Dnid.h295 #define GRBM_GFX_INDEX 0x802C macro
Dsid.h998 #define GRBM_GFX_INDEX 0x802C macro
Dcikd.h1627 #define GRBM_GFX_INDEX 0x30800 macro
Devergreen.c3467 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3488 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i)); in evergreen_gpu_init()
3497 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES); in evergreen_gpu_init()
/linux-6.6.21/drivers/gpu/drm/radeon/reg_srcs/
Dcayman2 0x0000802C GRBM_GFX_INDEX
Devergreen2 0x0000802C GRBM_GFX_INDEX

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