Searched refs:DBC (Results 1 – 5 of 5) sorted by relevance
237 (DBC for short) is solely for the use of that workload and is not shared with240 Each DBC is a pair of FIFOs that manage data in and out of the workload. One243 Each DBC contains 4 registers in hardware:258 DBC registers are exposed to the host via the second BAR. Each DBC consumes264 memory must be provided per DBC, which hosts both FIFOs. The request FIFO will404 response FIFO of a DBC. The DMA Bridge hardware has an IRQ storm mitigation445 used by the DBC.483 channel. This notification identifies the workload by it's assigned DBC. A485 DBC/NSPs into a working state.
94 DMA Bridge, and as such, locks the BO to a specific DBC.132 workload should be allowed to interface with the DBC.
200 if (!PSP_FEATURE(psp, DBC)) in dbc_dev_init()
420 DBC = 0x38, enumerator
918 AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - DBC SUPPORT