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Searched refs:CTX (Results 1 – 25 of 185) sorted by relevance

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/linux-6.6.21/arch/x86/crypto/
Dcamellia-x86_64-asm_64.S38 #define CTX %rdi macro
92 movq (key_table + ((subkey) * 2) * 4)(CTX), RT2; \
102 movl (key_table + ((kl) * 2) * 4)(CTX), RT0d; \
107 movq (key_table + ((kr) * 2) * 4)(CTX), RT1; \
112 movq (key_table + ((kl) * 2) * 4)(CTX), RT2; \
116 movl (key_table + ((kr) * 2) * 4)(CTX), RT0d; \
140 xorq key_table(CTX), RAB0;
143 xorq key_table(CTX, max, 8), RCD0; \
169 xorq key_table(CTX, max, 8), RAB0;
172 xorq key_table(CTX), RCD0; \
[all …]
Dblowfish-x86_64-asm_64.S21 #define CTX %r12 macro
64 movl s0(CTX,RT0,4), RT0d; \
65 addl s1(CTX,RT1,4), RT0d; \
69 xorl s2(CTX,RT1,4), RT0d; \
70 addl s3(CTX,RT2,4), RT0d; \
74 xorq p+4*(n)(CTX), RX0;
83 movq p+4*(n-1)(CTX), RT0; \
110 movq %rdi, CTX;
141 movq %rdi, CTX;
179 movl s0(CTX,RT0,4), RT0d; \
[all …]
Dtwofish-x86_64-asm_64-3way.S24 #define CTX %rdi macro
81 op1##l T0(CTX, tmp2, 4), dst ## d; \
82 op2##l T1(CTX, tmp1, 4), dst ## d;
120 addl k+4*(2*(n))(CTX), x ## d; \
122 addl k+4*(2*(n)+1)(CTX), y ## d; \
133 addl k+4*(2*(n))(CTX), x ## d; \
134 addl k+4*(2*(n)+1)(CTX), y ## d; \
177 xorq w+4*m(CTX), xy ## 0; \
180 xorq w+4*m(CTX), xy ## 1; \
183 xorq w+4*m(CTX), xy ## 2;
[all …]
Dcamellia-aesni-avx-asm_64.S28 #define CTX %rdi macro
214 leaq (key_table + (i) * 8)(CTX), %r9; \
226 leaq (key_table + ((i) + (dir)) * 8)(CTX), %r9; \
739 ((key_table + (8) * 8) + 0)(CTX),
740 ((key_table + (8) * 8) + 4)(CTX),
741 ((key_table + (8) * 8) + 8)(CTX),
742 ((key_table + (8) * 8) + 12)(CTX));
751 ((key_table + (16) * 8) + 0)(CTX),
752 ((key_table + (16) * 8) + 4)(CTX),
753 ((key_table + (16) * 8) + 8)(CTX),
[all …]
Dsha256-avx2-asm.S95 CTX = %rdi # 1st arg define
101 SRND = CTX # SRND is same register as CTX
549 mov (CTX), a
550 mov 4*1(CTX), b
551 mov 4*2(CTX), c
552 mov 4*3(CTX), d
553 mov 4*4(CTX), e
554 mov 4*5(CTX), f
555 mov 4*6(CTX), g
556 mov 4*7(CTX), h
[all …]
Dcamellia-aesni-avx2-asm_64.S18 #define CTX %rdi macro
246 leaq (key_table + (i) * 8)(CTX), %r9; \
258 leaq (key_table + ((i) + (dir)) * 8)(CTX), %r9; \
773 ((key_table + (8) * 8) + 0)(CTX),
774 ((key_table + (8) * 8) + 4)(CTX),
775 ((key_table + (8) * 8) + 8)(CTX),
776 ((key_table + (8) * 8) + 12)(CTX));
785 ((key_table + (16) * 8) + 0)(CTX),
786 ((key_table + (16) * 8) + 4)(CTX),
787 ((key_table + (16) * 8) + 8)(CTX),
[all …]
Dtwofish-avx-x86_64-asm_64.S35 #define CTX %rdi macro
90 movl t0(CTX, RID1, 4), dst ## d; \
91 movl t1(CTX, RID2, 4), RID2d; \
96 xorl t2(CTX, RID1, 4), dst ## d; \
97 xorl t3(CTX, RID2, 4), dst ## d;
173 vbroadcastss (k+4*(2*(n)))(CTX), RK1; \
174 vbroadcastss (k+4*(2*(n)+1))(CTX), RK2; \
181 vbroadcastss (k+4*(2*(n)))(CTX), RK1; \
182 vbroadcastss (k+4*(2*(n)+1))(CTX), RK2; \
239 vmovdqu w(CTX), RK1;
[all …]
Dcast5-avx-x86_64-asm_64.S35 #define CTX %r15 macro
150 vbroadcastss (km+(4*n))(CTX), RKM; \
160 vpxor kr(CTX), RKR, RKR;
165 vpxor kr(CTX), RKR, RKR; \
240 movq %rdi, CTX;
265 movzbl rr(CTX), %eax;
313 movq %rdi, CTX;
325 movzbl rr(CTX), %eax;
373 movq %rdi, CTX;
411 movq %rdi, CTX;
[all …]
Dsha256-avx-asm.S100 CTX = %rdi # 1st arg define
368 mov 4*0(CTX), a
369 mov 4*1(CTX), b
370 mov 4*2(CTX), c
371 mov 4*3(CTX), d
372 mov 4*4(CTX), e
373 mov 4*5(CTX), f
374 mov 4*6(CTX), g
375 mov 4*7(CTX), h
438 addm (4*0)(CTX),a
[all …]
Dsha256-ssse3-asm.S93 CTX = %rdi # 1st arg define
377 mov 4*0(CTX), a
378 mov 4*1(CTX), b
379 mov 4*2(CTX), c
380 mov 4*3(CTX), d
381 mov 4*4(CTX), e
382 mov 4*5(CTX), f
383 mov 4*6(CTX), g
384 mov 4*7(CTX), h
451 addm (4*0)(CTX),a
[all …]
Dcast6-avx-x86_64-asm_64.S35 #define CTX %r15 macro
150 vbroadcastss (km+(4*(nn)))(CTX), RKM; \
187 vpxor (kr+n*16)(CTX), RKR, RKR; \
263 movq %rdi, CTX;
311 movq %rdi, CTX;
355 movq %rdi, CTX;
378 movq %rdi, CTX;
402 movq %rdi, CTX;
/linux-6.6.21/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.h51 #define REG_READ(reg) ((CTX)->funcs.reg_read((CTX)->user_ctx, REG(reg)))
54 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
59 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
86 dmub_reg_update(CTX, REG(reg_name), n, __VA_ARGS__)
113 dmub_reg_get(CTX, REG(reg_name), FN(reg_name, field), val)
Ddmub_dcn21.c35 #define CTX dmub macro
Ddmub_dcn301.c35 #define CTX dmub macro
Ddmub_dcn302.c35 #define CTX dmub macro
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h40 dm_read_reg(CTX, REG(reg_name))
43 dm_write_reg(CTX, REG(reg_name), value)
55 generic_reg_set_ex(CTX, \
157 generic_reg_get(CTX, REG(reg_name), \
161 generic_reg_get2(CTX, REG(reg_name), \
166 generic_reg_get3(CTX, REG(reg_name), \
172 generic_reg_get4(CTX, REG(reg_name), \
179 generic_reg_get5(CTX, REG(reg_name), \
187 generic_reg_get6(CTX, REG(reg_name), \
196 generic_reg_get7(CTX, REG(reg_name), \
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_smu.c75 CTX->logger
156 generic_write_indirect_reg(CTX, in dcn315_smu_send_msg_with_param()
159 read_back_data = generic_read_indirect_reg(CTX, in dcn315_smu_send_msg_with_param()
172 dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000); in dcn315_smu_send_msg_with_param()
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_hubbub.c33 #define CTX \ macro
43 #define CTX \ macro
Ddcn301_hwseq.c33 #define CTX \ macro
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn321/
Ddcn321_dio_link_encoder.c42 #define CTX \ macro
58 dm_read_reg(CTX, AUX_REG(reg_name))
61 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_hubbub.c36 #define CTX \ macro
46 #define CTX \ macro
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dio_link_encoder.c37 #define CTX \ macro
214 dm_read_reg(CTX, AUX_REG(reg_name))
217 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux-6.6.21/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_dio_link_encoder.c43 #define CTX \ macro
59 dm_read_reg(CTX, AUX_REG(reg_name))
62 dm_write_reg(CTX, AUX_REG(reg_name), val)
/linux-6.6.21/arch/sparc/kernel/
Dsun4v_tlb_miss.S11 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \ argument
13 ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
16 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \ argument
18 ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
24 #define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \ argument
26 brz,pn CTX, ZERO_CTX_LABEL; \
Diommu.c28 #define STC_CTXMATCH_ADDR(STC, CTX) \ argument
29 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
70 #define IOPTE_CONSISTENT(CTX) \ argument
72 (((CTX) << 47) & IOPTE_CONTEXT))
74 #define IOPTE_STREAMING(CTX) \ argument
75 (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)

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