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Searched refs:ARRAY_MODE (Results 1 – 16 of 16) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/ !
Dgfx_v6_0.c79 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) macro
406 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
414 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
422 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
430 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
438 ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
457 ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
464 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED); in gfx_v6_0_tiling_mode_table_init()
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Dgfx_v8_0.c68 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) macro
2092 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2096 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2100 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2104 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2108 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2112 modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2116 modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2120 modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v8_0_tiling_mode_table_init()
2122 modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
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Dgfx_v7_0.c1019 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1023 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1027 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1031 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1035 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1039 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1042 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1047 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in gfx_v7_0_tiling_mode_table_init()
1049 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1052 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
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Dcikd.h189 # define ARRAY_MODE(x) ((x) << 2) macro
Dsid.h1177 # define ARRAY_MODE(x) ((x) << 2) macro
Ddce_v6_0.c1938 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
1953 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v6_0_crtc_do_set_base()
Ddce_v8_0.c1907 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
1923 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v8_0_crtc_do_set_base()
Ddce_v10_0.c1982 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
2002 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v10_0_crtc_do_set_base()
Ddce_v11_0.c2032 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
2052 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { in dce_v11_0_crtc_do_set_base()
/linux-6.6.21/drivers/gpu/drm/radeon/ !
Dcik.c2357 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2361 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2365 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2369 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2373 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2377 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2380 tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2384 tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2388 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2390 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
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Dsi.c2515 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2524 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2533 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2542 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2551 tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
2560 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2569 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2578 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2587 tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in si_tiling_mode_table_init()
2596 tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in si_tiling_mode_table_init()
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Dsid.h1180 # define ARRAY_MODE(x) ((x) << 2) macro
Dcikd.h1218 # define ARRAY_MODE(x) ((x) << 2) macro
/linux-6.6.21/drivers/gpu/drm/amd/display/amdgpu_dm/ !
Damdgpu_dm_plane.c184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { in fill_gfx8_tiling_info_from_flags()
203 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) in fill_gfx8_tiling_info_from_flags()
Damdgpu_dm.c9679 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && in dm_check_cursor_fb()
9680 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && in dm_check_cursor_fb()
/linux-6.6.21/drivers/gpu/drm/amd/include/ !
Dnavi10_enum.h1673 typedef enum ARRAY_MODE { enum
1690 } ARRAY_MODE; typedef