| /linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | ctxgv100.c | 70 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gv100_grctx_generate_attrib()
120 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
131 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
134 u8 v19 = (1 << (j + 0)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
135 u8 v20 = (1 << (j + 1)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
136 u8 v21 = (1 << (j + 2)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
137 u8 v22 = (1 << (j + 3)) % gr->tpc_total; in gv100_grctx_generate_rop_mapping()
145 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gv100_grctx_generate_rop_mapping()
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| D | ctxgf117.c | 211 ntpcv = gr->tpc_total; in gf117_grctx_generate_rop_mapping()
224 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
230 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
237 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gf117_grctx_generate_rop_mapping()
252 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gf117_grctx_generate_attrib()
256 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gf117_grctx_generate_attrib()
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| D | gm200.c | 167 if (gr->gpc_nr == 2 && gr->tpc_total == 8) { in gm200_gr_oneinit_tiles()
168 memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total); in gm200_gr_oneinit_tiles()
171 if (gr->gpc_nr == 4 && gr->tpc_total == 16) { in gm200_gr_oneinit_tiles()
172 memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total); in gm200_gr_oneinit_tiles()
175 if (gr->gpc_nr == 6 && gr->tpc_total == 24) { in gm200_gr_oneinit_tiles()
176 memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total); in gm200_gr_oneinit_tiles()
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| D | gf117.c | 127 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf117_gr_init_zcull()
128 const u8 tile_nr = ALIGN(gr->tpc_total, 32); in gf117_gr_init_zcull()
133 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf117_gr_init_zcull()
144 gr->tpc_total); in gf117_gr_init_zcull()
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| D | tu102.c | 55 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in tu102_gr_init_zcull()
56 const u8 tile_nr = ALIGN(gr->tpc_total, 64); in tu102_gr_init_zcull()
61 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in tu102_gr_init_zcull()
72 gr->tpc_total); in tu102_gr_init_zcull()
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| D | ctxgf100.c | 1071 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gf100_grctx_generate_attrib()
1128 ntpcv = gr->tpc_total; in gf100_grctx_generate_rop_mapping()
1141 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1147 nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1154 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gf100_grctx_generate_rop_mapping()
1278 u32 atarget = gf100_grctx_alpha_beta_map[gr->tpc_total][i]; in gf100_grctx_generate_alpha_beta_tables()
1283 atarget = max_t(u32, gr->tpc_total * i / 32, 1); in gf100_grctx_generate_alpha_beta_tables()
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| D | ctxgk104.c | 926 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk104_grctx_generate_gpc_tpc_nr()
936 u32 atarget = max_t(u32, gr->tpc_total * i / 32, 1); in gk104_grctx_generate_alpha_beta_tables()
937 u32 btarget = gr->tpc_total - atarget; in gk104_grctx_generate_alpha_beta_tables()
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| D | ctxgf108.c | 744 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gf108_grctx_generate_attrib()
748 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gf108_grctx_generate_attrib()
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| D | ctxgp100.c | 53 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp100_grctx_generate_attrib()
99 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gp100_grctx_generate_smid_config()
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| D | ctxgm107.c | 917 const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), false); in gm107_grctx_generate_attrib()
920 u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; in gm107_grctx_generate_attrib()
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| D | ctxgk20a.c | 50 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk20a_grctx_generate_main()
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| D | ctxgm20b.c | 47 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm20b_grctx_generate_main()
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| D | ctxgm200.c | 49 const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); in gm200_grctx_generate_smid_config()
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| D | ctxgp102.c | 49 u32 size = grctx->alpha_nr_max * gr->tpc_total; in gp102_grctx_generate_attrib()
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| D | gf100.c | 1106 cfg |= (u32)gr->tpc_total << 8; in gf100_gr_units()
1876 switch (gr->tpc_total) { in gf100_gr_oneinit_tiles()
1889 if (gr->tpc_total % primes[i]) { in gf100_gr_oneinit_tiles()
1929 for (i = 0; i < gr->tpc_total;) { in gf100_gr_oneinit_tiles()
1956 gr->tpc_total += gr->tpc_nr[i]; in gf100_gr_oneinit()
2224 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); in gf100_gr_init_zcull()
2225 const u8 tile_nr = ALIGN(gr->tpc_total, 32); in gf100_gr_init_zcull()
2230 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { in gf100_gr_init_zcull()
2241 gr->tpc_total); in gf100_gr_init_zcull()
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| D | gk20a.c | 273 nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16); in gk20a_gr_init()
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| D | gf100.h | 116 u8 tpc_total; member
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