/linux-6.1.9/drivers/net/ethernet/intel/ixgbevf/ |
D | ipsec.c | 23 struct sa_mbx_msg *sam; in ixgbevf_ipsec_set_pf_sa() local 27 sam = (struct sa_mbx_msg *)(&msgbuf[1]); in ixgbevf_ipsec_set_pf_sa() 28 sam->dir = xs->xso.dir; in ixgbevf_ipsec_set_pf_sa() 29 sam->spi = xs->id.spi; in ixgbevf_ipsec_set_pf_sa() 30 sam->proto = xs->id.proto; in ixgbevf_ipsec_set_pf_sa() 31 sam->family = xs->props.family; in ixgbevf_ipsec_set_pf_sa() 34 memcpy(sam->addr, &xs->id.daddr.a6, sizeof(xs->id.daddr.a6)); in ixgbevf_ipsec_set_pf_sa() 36 memcpy(sam->addr, &xs->id.daddr.a4, sizeof(xs->id.daddr.a4)); in ixgbevf_ipsec_set_pf_sa() 37 memcpy(sam->key, xs->aead->alg_key, sizeof(sam->key)); in ixgbevf_ipsec_set_pf_sa()
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/linux-6.1.9/drivers/clk/hisilicon/ |
D | clk-hi3620.c | 325 u32 sam, drv, div, val; in mmc_clk_set_timing() local 330 sam = 3; in mmc_clk_set_timing() 335 sam = 13; in mmc_clk_set_timing() 340 sam = 3; in mmc_clk_set_timing() 345 sam = 6; in mmc_clk_set_timing() 350 sam = 6; in mmc_clk_set_timing() 365 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits); in mmc_clk_set_timing()
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/linux-6.1.9/drivers/net/ethernet/intel/ixgbe/ |
D | ixgbe_ipsec.c | 888 struct sa_mbx_msg *sam; in ixgbe_ipsec_vf_add_sa() local 895 sam = (struct sa_mbx_msg *)(&msgbuf[1]); in ixgbe_ipsec_vf_add_sa() 906 if (sam->dir != XFRM_DEV_OFFLOAD_IN) { in ixgbe_ipsec_vf_add_sa() 917 xs->xso.dir = sam->dir; in ixgbe_ipsec_vf_add_sa() 918 xs->id.spi = sam->spi; in ixgbe_ipsec_vf_add_sa() 919 xs->id.proto = sam->proto; in ixgbe_ipsec_vf_add_sa() 920 xs->props.family = sam->family; in ixgbe_ipsec_vf_add_sa() 922 memcpy(&xs->id.daddr.a6, sam->addr, sizeof(xs->id.daddr.a6)); in ixgbe_ipsec_vf_add_sa() 924 memcpy(&xs->id.daddr.a4, sam->addr, sizeof(xs->id.daddr.a4)); in ixgbe_ipsec_vf_add_sa() 944 memcpy(xs->aead->alg_key, sam->key, sizeof(sam->key)); in ixgbe_ipsec_vf_add_sa()
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/linux-6.1.9/arch/arm64/boot/dts/mediatek/ |
D | mt7986b.dtsi | 4 * Author: Sam.Shih <sam.shih@mediatek.com>
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D | mt7986b-rfb.dts | 4 * Author: Sam.Shih <sam.shih@mediatek.com>
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D | mt7986a-rfb.dts | 4 * Author: Sam.Shih <sam.shih@mediatek.com>
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D | mt7986a.dtsi | 4 * Author: Sam.Shih <sam.shih@mediatek.com>
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/linux-6.1.9/drivers/net/can/mscan/ |
D | mscan.h | 256 #define BTR1_SET_SAM(sam) ((sam) ? 1 << BTR1_SAM_SHIFT : 0) argument
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/linux-6.1.9/Documentation/devicetree/bindings/display/panel/ |
D | panel-dpi.yaml | 10 - Sam Ravnborg <sam@ravnborg.org>
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D | display-timings.yaml | 12 - Sam Ravnborg <sam@ravnborg.org>
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D | boe,tv101wum-nl6.yaml | 11 - Sam Ravnborg <sam@ravnborg.org>
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D | panel-simple-dsi.yaml | 11 - Sam Ravnborg <sam@ravnborg.org>
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D | panel-timing.yaml | 11 - Sam Ravnborg <sam@ravnborg.org>
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D | panel-simple.yaml | 11 - Sam Ravnborg <sam@ravnborg.org>
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/linux-6.1.9/net/6lowpan/ |
D | iphc.c | 849 const unsigned char *lladdr, bool sam) in lowpan_compress_ctx_addr() argument 898 if (sam) in lowpan_compress_ctx_addr() 946 const unsigned char *lladdr, bool sam) in lowpan_compress_addr_64() argument 984 if (sam) in lowpan_compress_addr_64()
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/linux-6.1.9/Documentation/hwmon/ |
D | ir35221.rst | 13 Author: Samuel Mendoza-Jonas <sam@mendozajonas.com>
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/linux-6.1.9/Documentation/devicetree/bindings/mips/cavium/ |
D | bootbus.txt | 64 - cavium,sam-mode: Optional. If present, SAM mode is selected.
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/linux-6.1.9/tools/build/ |
D | Build.include | 7 # Copyright (C) Sam Ravnborg <sam@mars.ravnborg.org>, 2015
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/linux-6.1.9/arch/mips/include/asm/octeon/ |
D | cvmx-mio-defs.h | 596 uint64_t sam:1; member 614 uint64_t sam:1; 624 uint64_t sam:1; member 642 uint64_t sam:1; 668 uint64_t sam:1; member 686 uint64_t sam:1;
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/linux-6.1.9/drivers/ata/ |
D | pata_octeon_cf.c | 108 reg_cfg.s.sam = 0; /* Don't combine write and output enable */ in octeon_cf_set_boot_reg_cfg()
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/linux-6.1.9/ |
D | .mailmap | 383 Sam Ravnborg <sam@mars.ravnborg.org>
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D | CREDITS | 2742 E: sam.mosel@computer.org
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D | MAINTAINERS | 6848 M: Sam Ravnborg <sam@ravnborg.org> 7087 R: Sam Ravnborg <sam@ravnborg.org> 14190 M: Samuel Mendoza-Jonas <sam@mendozajonas.com>
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/linux-6.1.9/Documentation/kbuild/ |
D | makefiles.rst | 1685 - Updates by Sam Ravnborg <sam@ravnborg.org>
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