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Searched refs:reg_tbl (Results 1 – 14 of 14) sorted by relevance

/linux-6.1.9/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.h39 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
43 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
Dqlcnic.h530 u32 *reg_tbl; member
Dqlcnic_83xx_hw.c264 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_83xx_register_map()
3615 sizeof(*adapter->ahw->reg_tbl)); in qlcnic_83xx_get_regs_len()
Dqlcnic_sriov_common.c664 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_sriov_vf_register_map()
Dqlcnic_main.c2459 ahw->reg_tbl = (u32 *) qlcnic_reg_tbl; in qlcnic_probe()
/linux-6.1.9/drivers/media/platform/qcom/venus/
Dcore.c543 .reg_tbl = msm8916_reg_preset,
573 .reg_tbl = msm8996_reg_preset,
627 .reg_tbl = sdm660_reg_preset,
796 .reg_tbl = sm8250_reg_preset,
855 .reg_tbl = sm7280_reg_preset,
Dcore.h59 const struct reg_val *reg_tbl; member
Dhfi_venus.c351 const struct reg_val *tbl = res->reg_tbl; in venus_set_registers()
/linux-6.1.9/drivers/scsi/qla4xxx/
Dql4_def.h818 uint32_t *reg_tbl; member
1058 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); in qla4_8xxx_rd_direct()
1065 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); in qla4_8xxx_wr_direct()
Dql4_83xx.c453 ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]); in qla4_83xx_can_perform_reset()
455 drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]); in qla4_83xx_can_perform_reset()
Dql4_os.c8647 ha->reg_tbl = (uint32_t *) qla4_82xx_reg_tbl; in qla4xxx_probe_adapter()
8659 ha->reg_tbl = (uint32_t *)qla4_83xx_reg_tbl; in qla4xxx_probe_adapter()
/linux-6.1.9/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_ethtool.c2242 } reg_tbl[] = { in bnx2x_test_registers() local
2354 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { in bnx2x_test_registers()
2356 if (!(hw & reg_tbl[i].hw)) in bnx2x_test_registers()
2359 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; in bnx2x_test_registers()
2360 mask = reg_tbl[i].mask; in bnx2x_test_registers()
/linux-6.1.9/drivers/net/ethernet/broadcom/
Dbnx2.c5573 } reg_tbl[] = { in bnx2_test_registers() local
5687 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in bnx2_test_registers()
5689 u16 flags = reg_tbl[i].flags; in bnx2_test_registers()
5694 offset = (u32) reg_tbl[i].offset; in bnx2_test_registers()
5695 rw_mask = reg_tbl[i].rw_mask; in bnx2_test_registers()
5696 ro_mask = reg_tbl[i].ro_mask; in bnx2_test_registers()
Dtg3.c13059 } reg_tbl[] = { in tg3_test_registers() local
13202 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in tg3_test_registers()
13203 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) in tg3_test_registers()
13206 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) in tg3_test_registers()
13210 (reg_tbl[i].flags & TG3_FL_NOT_5788)) in tg3_test_registers()
13213 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) in tg3_test_registers()
13216 offset = (u32) reg_tbl[i].offset; in tg3_test_registers()
13217 read_mask = reg_tbl[i].read_mask; in tg3_test_registers()
13218 write_mask = reg_tbl[i].write_mask; in tg3_test_registers()