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Searched refs:plane_res (Results 1 – 25 of 31) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_hw_sequencer.c151 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in dce60_set_default_colors()
158 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in dce60_set_default_colors()
160 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( in dce60_set_default_colors()
161 pipe_ctx->plane_res.xfm, &default_adjust); in dce60_set_default_colors()
202 switch (pipe_ctx->plane_res.scl_data.format) { in dce60_get_surface_visual_confirm_color()
246 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in dce60_program_scaler()
247 pipe_ctx->plane_res.xfm, in dce60_program_scaler()
248 pipe_ctx->plane_res.scl_data.lb_params.depth, in dce60_program_scaler()
265 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in dce60_program_scaler()
266 &pipe_ctx->plane_res.scl_data); in dce60_program_scaler()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c789 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport_size()
806 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_recout()
895 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
898 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
903 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
905 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
907 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
908 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
909 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( in calculate_scaling_ratios()
910 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); in calculate_scaling_ratios()
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Ddc_stream.c375 (!pipe_ctx->plane_res.mi && !pipe_ctx->plane_res.hubp) || in program_cursor_position()
377 (!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) || in program_cursor_position()
378 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp)) in program_cursor_position()
690 hubp = pipe_ctx->plane_res.hubp; in dc_stream_set_dynamic_metadata()
Ddc_hw_sequencer.c320 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
376 switch (top_pipe_ctx->plane_res.scl_data.format) { in get_hdr_visual_confirm_color()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_hw_sequencer.c286 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; in dce110_set_input_transfer_func()
614 struct transform *xfm = pipe_ctx->plane_res.xfm; in dce110_set_output_transfer_func()
1382 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) in program_scaler()
1392 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( in program_scaler()
1393 pipe_ctx->plane_res.xfm, in program_scaler()
1394 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1411 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, in program_scaler()
1412 &pipe_ctx->plane_res.scl_data); in program_scaler()
1606 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; in apply_single_controller_ctx_to_hw()
1857 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( in dce110_set_displaymarks()
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Ddce110_resource.c1135 pipe_ctx->plane_res.mi = pool->mis[underlay_idx]; in dce110_acquire_underlay()
1137 pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx]; in dce110_acquire_underlay()
1171 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi, in dce110_acquire_underlay()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c183 if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl) in dcn20_set_flip_control_gsl()
184 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl( in dcn20_set_flip_control_gsl()
185 pipe_ctx->plane_res.hubp, flip_immediate); in dcn20_set_flip_control_gsl()
270 if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) { in dcn20_program_triple_buffer()
271 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer( in dcn20_program_triple_buffer()
272 pipe_ctx->plane_res.hubp, in dcn20_program_triple_buffer()
574 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn20_plane_atomic_disable()
575 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn20_plane_atomic_disable()
594 pipe_ctx->plane_res.dpp, in dcn20_plane_atomic_disable()
595 pipe_ctx->plane_res.hubp); in dcn20_plane_atomic_disable()
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Ddcn20_resource.c1469 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1470 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1471 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1472 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1473 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1474 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1492 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1509 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1554 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
1555 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; in dcn20_split_stream_for_mpc()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calcs.c318 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
333 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
341 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
342 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
343 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
344 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
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Ddce_calcs.c2827 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2829 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2830 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2831 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2832 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2833 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
2882 …data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.v… in populate_initial_data()
2883 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2886 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2887 …data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c537 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_did_underflow_occur()
1082 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1107 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1120 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1130 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1142 hubp = pipe_ctx->plane_res.hubp; in dcn10_hw_wa_force_recovery()
1180 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disconnect()
1181 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn10_plane_atomic_disconnect()
1198 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1253 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn10_plane_atomic_disable()
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Ddcn10_resource.c1116 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1117 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1118 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_idle_pipe_for_layer()
1119 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_resource_helpers.c87 full_vp_height = main_pipe->plane_res.scl_data.viewport.height; in dcn32_helper_calculate_num_ways_for_subvp()
99 full_vp_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + in dcn32_helper_calculate_num_ways_for_subvp()
100 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) + in dcn32_helper_calculate_num_ways_for_subvp()
101 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); in dcn32_helper_calculate_num_ways_for_subvp()
106 full_vp_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + in dcn32_helper_calculate_num_ways_for_subvp()
108 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); in dcn32_helper_calculate_num_ways_for_subvp()
114 … mall_alloc_height_blk_aligned = (pipe->plane_res.scl_data.viewport.height - 1 + mblk_height - 1) / in dcn32_helper_calculate_num_ways_for_subvp()
174 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
188 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_merge_pipes_for_subvp()
Ddcn32_hwseq.c244 mall_alloc_width_blk_aligned = ((pipe->plane_res.scl_data.viewport.x + in dcn32_calculate_cab_allocation()
245 pipe->plane_res.scl_data.viewport.width + mblk_width - 1) / mblk_width * mblk_width) - in dcn32_calculate_cab_allocation()
246 (pipe->plane_res.scl_data.viewport.x / mblk_width * mblk_width); in dcn32_calculate_cab_allocation()
253 mall_alloc_height_blk_aligned = ((pipe->plane_res.scl_data.viewport.y + in dcn32_calculate_cab_allocation()
254 pipe->plane_res.scl_data.viewport.height + mblk_height - 1) / mblk_height * mblk_height) - in dcn32_calculate_cab_allocation()
255 (pipe->plane_res.scl_data.viewport.y / mblk_height * mblk_height); in dcn32_calculate_cab_allocation()
279 struct hubp *hubp = pipe->plane_res.hubp; in dcn32_calculate_cab_allocation()
519 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
520 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn32_set_mpc_shaper_3dlut()
555 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts()
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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_hwseq.c146 pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr( in dcn201_update_plane_addr()
147 pipe_ctx->plane_res.hubp, in dcn201_update_plane_addr()
323 pipe_ctx->plane_res.hubp = hubp; in dcn201_init_hw()
324 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
325 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
333 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
356 pipe_ctx->plane_res.hubp = NULL; in dcn201_init_hw()
392 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn201_plane_atomic_disconnect()
393 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
424 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect()
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Ddcn201_resource.c1022 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; in dcn201_acquire_idle_pipe_for_layer()
1023 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; in dcn201_acquire_idle_pipe_for_layer()
1024 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_idle_pipe_for_layer()
1025 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_idle_pipe_for_layer()
/linux-6.1.9/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_trace.h385 const struct plane_resource *plane_res,
387 TP_ARGS(pipe_idx, plane_state, stream, plane_res, update_flags),
438 __entry->recout_x = plane_res->scl_data.recout.x;
439 __entry->recout_y = plane_res->scl_data.recout.y;
440 __entry->recout_w = plane_res->scl_data.recout.width;
441 __entry->recout_h = plane_res->scl_data.recout.height;
442 __entry->viewport_x = plane_res->scl_data.viewport.x;
443 __entry->viewport_y = plane_res->scl_data.viewport.y;
444 __entry->viewport_w = plane_res->scl_data.viewport.width;
445 __entry->viewport_h = plane_res->scl_data.viewport.height;
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/
Ddc_trace.h31 pipe_ctx->stream, &pipe_ctx->plane_res, \
Ddc_dmub_srv.c904 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dc_build_cursor_update_payload0()
1009 pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
1022 pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp); in dc_send_update_cursor_info_to_dmu()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_hwseq.c76 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_blend_lut()
97 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_mpc_shaper_3dlut()
98 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_mpc_shaper_3dlut()
151 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn30_set_input_transfer_func()
193 int mpcc_id = pipe_ctx->plane_res.hubp->inst; in dcn30_set_output_transfer_func()
407 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
687 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn30_program_dmdata_engine()
Ddcn30_resource.c1547 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1548 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1549 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1550 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1551 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1552 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1720 && memcmp(&mpo_pipe->plane_res.scl_data.recout, in dcn30_internal_validate_bw()
1721 &pipe->plane_res.scl_data.recout, in dcn30_internal_validate_bw()
1753 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
1768 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn30_internal_validate_bw()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c172 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
173 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/
Ddmub_psr.c347 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
349 if (pipe_ctx->plane_res.dpp) in dmub_psr_copy_settings()
350 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_psr_copy_settings()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/
Ddcn32_fpu.c1306 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn32_calculate_dlg_params()
1418 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1419 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1420 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1421 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1422 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn32_split_stream_for_mpc_or_odm()
1423 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn32_split_stream_for_mpc_or_odm()
1560 && memcmp(&mpo_pipe->plane_res.scl_data.recout, in dcn32_internal_validate_bw()
1561 &pipe->plane_res.scl_data.recout, in dcn32_internal_validate_bw()
1619 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); in dcn32_internal_validate_bw()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h404 struct plane_resource plane_res; member

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