Searched refs:num_vcn_inst (Results 1 – 10 of 10) sorted by relevance
85 adev->vcn.num_vcn_inst = 2; in vcn_v2_5_early_init()92 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_early_init()126 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()160 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { in vcn_v2_5_sw_init()244 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v2_5_sw_fini()282 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in vcn_v2_5_hw_init()333 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_hw_fini()401 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_mc_resume()558 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_disable_clock_gating()723 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v2_5_enable_clock_gating()[all …]
114 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_init()182 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_sw_fini()226 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()243 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_init()281 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_hw_fini()1001 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_start()1208 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v4_0_start_sriov()1412 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_stop()1763 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_set_unified_ring_funcs()1786 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v4_0_is_idle()[all …]
92 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; in vcn_v3_0_early_init()152 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_init()260 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_sw_fini()304 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()335 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_init()379 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_hw_fini()1103 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_start()1321 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in vcn_v3_0_start_sriov()1526 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_stop()2028 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in vcn_v3_0_set_dec_ring_funcs()[all …]
96 for (i = 0; i < adev->vcn.num_vcn_inst; i++) in amdgpu_vcn_sw_init()272 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_sw_init()315 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_sw_fini()379 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_suspend()406 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { in amdgpu_vcn_resume()451 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { in amdgpu_vcn_idle_work_handler()1110 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_vcn_setup_ucode()
1131 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = in amdgpu_discovery_reg_base_init()1134 if (adev->vcn.num_vcn_inst < AMDGPU_MAX_VCN_INSTANCES) in amdgpu_discovery_reg_base_init()1135 adev->vcn.num_vcn_inst++; in amdgpu_discovery_reg_base_init()1138 adev->vcn.num_vcn_inst + 1, in amdgpu_discovery_reg_base_init()1271 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { in amdgpu_discovery_harvest_ip()1444 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { in amdgpu_discovery_get_vcn_info()1462 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { in amdgpu_discovery_get_vcn_info()2019 adev->vcn.num_vcn_inst = 1; in amdgpu_discovery_set_ip_blocks()2081 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()2109 adev->vcn.num_vcn_inst = 2; in amdgpu_discovery_set_ip_blocks()
259 uint8_t num_vcn_inst; member
432 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()444 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_hw_ip_info()
1985 for ( i = 0; i < adev->vcn.num_vcn_inst; i++) { in amdgpu_debugfs_init()
1841 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_performance_level()1856 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_performance_level()2121 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in smu_v13_0_set_vcn_enable()
1006 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()1029 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_set_default_dpm_table()1130 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { in sienna_cichlid_dpm_set_vcn_enable()