Home
last modified time | relevance | path

Searched refs:mmVCE_VCPU_CACHE_SIZE0 (Results 1 – 7 of 7) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vce/
Dvce_1_0_d.h59 #define mmVCE_VCPU_CACHE_SIZE0 0x800A macro
Dvce_2_0_d.h30 #define mmVCE_VCPU_CACHE_SIZE0 0x800a macro
Dvce_3_0_d.h30 #define mmVCE_VCPU_CACHE_SIZE0 0x800a macro
Dvce_4_0_offset.h34 #define mmVCE_VCPU_CACHE_SIZE0 macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dvce_v2_0.c188 WREG32(mmVCE_VCPU_CACHE_SIZE0, size); in vce_v2_0_mc_resume()
Dvce_v4_0.c285 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); in vce_v4_0_sriov_start()
669 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); in vce_v4_0_mc_resume()
Dvce_v3_0.c577 WREG32(mmVCE_VCPU_CACHE_SIZE0, size); in vce_v3_0_mc_resume()