Searched refs:mmUVD_SUVD_CGC_GATE (Results 1 – 14 of 14) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_5_0_d.h | 89 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
|
| D | uvd_6_0_d.h | 105 #define mmUVD_SUVD_CGC_GATE 0x3be4 macro
|
| D | uvd_7_0_offset.h | 66 #define mmUVD_SUVD_CGC_GATE … macro
|
| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | uvd_v5_0.c | 633 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v5_0_enable_clock_gating()
671 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v5_0_enable_clock_gating()
728 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
759 WREG32(mmUVD_SUVD_CGC_GATE, data1);
|
| D | uvd_v6_0.c | 641 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
709 WREG32(mmUVD_SUVD_CGC_GATE, data1);
1281 data1 = RREG32(mmUVD_SUVD_CGC_GATE); in uvd_v6_0_enable_clock_gating()
1328 WREG32(mmUVD_SUVD_CGC_GATE, data1); in uvd_v6_0_enable_clock_gating()
1386 data1 = RREG32(mmUVD_SUVD_CGC_GATE);
1419 WREG32(mmUVD_SUVD_CGC_GATE, data1);
|
| D | uvd_v7_0.c | 1614 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1661 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1670 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1703 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
|
| D | vcn_v1_0.c | 526 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
551 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
687 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
|
| D | vcn_v2_0.c | 551 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
576 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
633 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
|
| D | vcn_v2_5.c | 621 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
646 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
704 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
|
| D | vcn_v3_0.c | 758 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
790 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
864 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
|
| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 154 #define mmUVD_SUVD_CGC_GATE … macro
|
| D | vcn_2_5_offset.h | 505 #define mmUVD_SUVD_CGC_GATE … macro
|
| D | vcn_2_0_0_offset.h | 818 #define mmUVD_SUVD_CGC_GATE … macro
|
| D | vcn_3_0_0_offset.h | 821 #define mmUVD_SUVD_CGC_GATE … macro
|