Searched refs:mmUVD_RB_BASE_LO (Results 1 – 12 of 12) sorted by relevance
| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_d.h | 44 #define mmUVD_RB_BASE_LO 0x3c26 macro
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| D | uvd_7_0_offset.h | 94 #define mmUVD_RB_BASE_LO … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| D | vcn_1_0_offset.h | 216 #define mmUVD_RB_BASE_LO … macro
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| D | vcn_2_5_offset.h | 551 #define mmUVD_RB_BASE_LO … macro
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| D | vcn_2_0_0_offset.h | 928 #define mmUVD_RB_BASE_LO … macro
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| D | vcn_3_0_0_offset.h | 881 #define mmUVD_RB_BASE_LO … macro
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| /linux-6.1.9/drivers/gpu/drm/amd/amdgpu/ |
| D | vcn_v2_0.c | 1085 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1952 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), in vcn_v2_0_start_sriov()
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| D | vcn_v2_5.c | 1092 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1263 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), in vcn_v2_5_sriov_start()
1441 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
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| D | vcn_v3_0.c | 1262 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_start()
1395 mmUVD_RB_BASE_LO), in vcn_v3_0_start_sriov()
1636 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
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| D | uvd_v7_0.c | 919 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); in uvd_v7_0_sriov_start()
1114 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v7_0_start()
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| D | vcn_v1_0.c | 944 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
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| D | uvd_v6_0.c | 865 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v6_0_start()
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