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Searched refs:mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH (Results 1 – 10 of 10) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_offset.h76 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h166 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH macro
Dvcn_2_5_offset.h879 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH macro
Dvcn_2_0_0_offset.h834 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH macro
Dvcn_3_0_0_offset.h1365 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c367 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
455 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_0_mc_resume_dpg_mode()
1938 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_0_start_sriov()
Dvcn_v2_5.c434 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
521 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
1249 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_5_sriov_start()
Dvcn_v3_0.c480 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
566 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()
1381 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v3_0_start_sriov()
Duvd_v7_0.c709 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
852 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in uvd_v7_0_sriov_start()
Dvcn_v1_0.c338 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
411 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_dpg_mode()