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Searched refs:mmCP_ME_RAM_WADDR (Results 1 – 13 of 13) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h462 #define mmCP_ME_RAM_WADDR 0x3057 macro
Dgfx_7_0_d.h243 #define mmCP_ME_RAM_WADDR 0x3057 macro
Dgfx_7_2_d.h245 #define mmCP_ME_RAM_WADDR 0x3057 macro
Dgfx_8_0_d.h274 #define mmCP_ME_RAM_WADDR 0xf816 macro
Dgfx_8_1_d.h275 #define mmCP_ME_RAM_WADDR 0xf816 macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c1985 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1988 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
1992 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v6_0_cp_gfx_load_microcode()
Dgfx_v7_0.c2469 WREG32(mmCP_ME_RAM_WADDR, 0); in gfx_v7_0_cp_gfx_load_microcode()
2472 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v7_0_cp_gfx_load_microcode()
Dgfx_v9_0.c3046 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); in gfx_v9_0_cp_gfx_load_microcode()
3049 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); in gfx_v9_0_cp_gfx_load_microcode()
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6727 #define mmCP_ME_RAM_WADDR macro
Dgc_9_1_offset.h6951 #define mmCP_ME_RAM_WADDR macro
Dgc_9_2_1_offset.h6979 #define mmCP_ME_RAM_WADDR macro
Dgc_10_1_0_offset.h10219 #define mmCP_ME_RAM_WADDR macro
Dgc_10_3_0_offset.h9931 #define mmCP_ME_RAM_WADDR macro