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Searched refs:mmCPC_INT_STATUS (Results 1 – 12 of 12) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h273 #define mmCPC_INT_STATUS 0x30b5 macro
Dgfx_7_2_d.h275 #define mmCPC_INT_STATUS 0x30b5 macro
Dgfx_8_0_d.h306 #define mmCPC_INT_STATUS 0x30b5 macro
Dgfx_8_1_d.h306 #define mmCPC_INT_STATUS 0x30b5 macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2595 #define mmCPC_INT_STATUS … macro
Dgc_9_1_offset.h2865 #define mmCPC_INT_STATUS … macro
Dgc_9_2_1_offset.h2799 #define mmCPC_INT_STATUS … macro
Dgc_10_1_0_offset.h4931 #define mmCPC_INT_STATUS … macro
Dgc_10_3_0_offset.h4590 #define mmCPC_INT_STATUS … macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c5320 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); in gfx_v9_0_ring_emit_fence_kiq()
Dgfx_v8_0.c6310 amdgpu_ring_write(ring, mmCPC_INT_STATUS); in gfx_v8_0_ring_emit_fence_kiq()
Dgfx_v10_0.c8650 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); in gfx_v10_0_ring_emit_fence_kiq()