| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| D | dcn321_fpu.c | 278 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) in build_synthetic_soc_states()
279 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in build_synthetic_soc_states()
289 if (bw_params->clk_table.entries[i].memclk_mhz > 0) in build_synthetic_soc_states()
338 entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16; in build_synthetic_soc_states()
382 if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) { in build_synthetic_soc_states()
383 table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16; in build_synthetic_soc_states()
554 …if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz… in dcn321_update_bw_bounding_box_fpu()
606 dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn321_update_bw_bounding_box_fpu()
618 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
634 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 272 …base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn3_update_clocks()
370 …base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn3_set_hard_min_memclk()
373 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
386 …base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn3_set_hard_max_memclk()
389 static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) in dcn3_set_max_memclk() argument
396 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn3_set_max_memclk()
398 static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz) in dcn3_set_min_memclk() argument
404 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn3_set_min_memclk()
418 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, in dcn3_get_memclk_states_from_smu()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| D | dcn302_fpu.c | 220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
262 dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn302_fpu_update_bw_bounding_box()
273 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
304 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| D | dcn303_fpu.c | 216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
256 dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn303_fpu_update_bw_bounding_box()
267 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
284 bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
299 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn303_fpu_update_bw_bounding_box()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 88 unsigned int memclk_mhz; member
288 void (*set_max_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);
289 void (*set_min_memclk)(struct clk_mgr *clk_mgr, unsigned int memclk_mhz);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 171 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
184 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
185 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
223 …mmy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
225 …mmy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
227 …mmy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
229 …mmy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16; in dcn32_build_wm_range_table_fpu()
1923 dc->clk_mgr->bw_params->clk_table.entries[min_dram_speed_mts_offset].memclk_mhz * 16; in dcn32_calculate_wm_and_dlg_fpu()
2072 if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz) in dcn32_patch_dpm_table()
2073 max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in dcn32_patch_dpm_table()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 501 .memclk_mhz = 800,
508 .memclk_mhz = 1600,
515 .memclk_mhz = 1067,
522 .memclk_mhz = 1600,
577 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 582 .memclk_mhz = 800,
589 .memclk_mhz = 1600,
596 .memclk_mhz = 1067,
603 .memclk_mhz = 1600,
666 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 387 ….entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); in dcn32_update_clocks()
638 ….entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); in dcn32_set_hard_min_memclk()
641 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn32_set_hard_min_memclk()
654 ….entries[clk_mgr_base->bw_params->clk_table.num_entries_per_clk.num_memclk_levels - 1].memclk_mhz); in dcn32_set_hard_max_memclk()
669 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz, in dcn32_get_memclk_states_from_smu()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | dcn314_fpu.c | 239 if (clk_table->entries[i].memclk_mhz && clk_table->entries[i].wck_ratio) in dcn314_update_bw_bounding_box_fpu()
240 …clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_… in dcn314_update_bw_bounding_box_fpu()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 515 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
527 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn315_clk_mgr_helper_populate_bw_params()
550 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 625 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[min_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
641 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[max_pstate].MemClk; in dcn314_clk_mgr_helper_populate_bw_params()
669 bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 599 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn31_update_bw_bounding_box()
671 …dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->ent… in dcn315_update_bw_bounding_box()
760 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn316_update_bw_bounding_box()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 2123 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn30_update_bw_bounding_box()
2161 dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, in dcn30_update_bw_bounding_box()
2174 bw_params->clk_table.entries[j].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2190 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2205 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
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| D | dcn30_hwseq.c | 992 …k_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); in dcn30_prepare_bandwidth()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 355 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_update_bw_bounding_box()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 453 …r->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16; in dcn30_fpu_calculate_wm_and_dlg()
668 uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz; in dcn3_fpu_build_wm_range_table()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 532 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn316_clk_mgr_helper_populate_bw_params()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 593 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn31_clk_mgr_helper_populate_bw_params()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 4294 static void blank_and_force_memclk(struct dc *dc, bool apply, unsigned int memclk_mhz) in blank_and_force_memclk() argument
4317 dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, memclk_mhz); in blank_and_force_memclk()
4318 dc->clk_mgr->funcs->set_min_memclk(dc->clk_mgr, memclk_mhz); in blank_and_force_memclk()
4359 …lk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz; in dc_enable_dcmode_clk_limit()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 2218 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2; in construct_low_pstate_lvl()
2271 s[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn21_update_bw_bounding_box()
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