| /linux-6.1.9/drivers/media/platform/ti/davinci/ |
| D | vpbe_display.c | 41 struct vpbe_layer *layer);
62 struct vpbe_layer *layer) in vpbe_isr_even_field() argument
64 if (layer->cur_frm == layer->next_frm) in vpbe_isr_even_field()
67 layer->cur_frm->vb.vb2_buf.timestamp = ktime_get_ns(); in vpbe_isr_even_field()
68 vb2_buffer_done(&layer->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE); in vpbe_isr_even_field()
70 layer->cur_frm = layer->next_frm; in vpbe_isr_even_field()
74 struct vpbe_layer *layer) in vpbe_isr_odd_field() argument
80 if (list_empty(&layer->dma_queue) || in vpbe_isr_odd_field()
81 (layer->cur_frm != layer->next_frm)) { in vpbe_isr_odd_field()
91 layer->next_frm = list_entry(layer->dma_queue.next, in vpbe_isr_odd_field()
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| D | vpbe_osd.c | 102 #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1)) argument
103 #define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1)) argument
409 static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer, in _osd_set_zoom() argument
415 switch (layer) { in _osd_set_zoom()
443 static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer) in _osd_disable_layer() argument
445 switch (layer) { in _osd_disable_layer()
463 static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer) in osd_disable_layer() argument
466 struct osd_window_state *win = &osd->win[layer]; in osd_disable_layer()
477 _osd_disable_layer(sd, layer); in osd_disable_layer()
488 static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer) in _osd_enable_layer() argument
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| /linux-6.1.9/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_qos.c | 22 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_leak_time() argument
26 value = spx5_rd(sparx5, HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_get_leak_time()
30 static void sparx5_lg_set_leak_time(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_set_leak_time() argument
34 HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_set_leak_time()
37 static u32 sparx5_lg_get_first(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_first() argument
41 value = spx5_rd(sparx5, HSCH_HSCH_LEAK_CFG(layer, group)); in sparx5_lg_get_first()
45 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_get_next() argument
55 static u32 sparx5_lg_get_last(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_last() argument
59 itr = sparx5_lg_get_first(sparx5, layer, group); in sparx5_lg_get_last()
62 next = sparx5_lg_get_next(sparx5, layer, group, itr); in sparx5_lg_get_last()
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| /linux-6.1.9/drivers/media/dvb-frontends/ |
| D | mb86a20s.c | 377 unsigned layer) in mb86a20s_get_modulation() argument
386 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_modulation()
388 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_modulation()
409 unsigned layer) in mb86a20s_get_fec() argument
419 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_fec()
421 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_fec()
444 unsigned layer) in mb86a20s_get_interleaving() argument
457 if (layer >= ARRAY_SIZE(reg)) in mb86a20s_get_interleaving()
459 rc = mb86a20s_writereg(state, 0x6d, reg[layer]); in mb86a20s_get_interleaving()
470 unsigned layer) in mb86a20s_get_segment_count() argument
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| /linux-6.1.9/Documentation/devicetree/bindings/display/ |
| D | xylon,logicvc-display.yaml | 25 In version 3 of the controller, each layer has fixed memory offset and address
103 xylon,background-layer:
106 The last layer is used to display a black background (C_USE_BACKGROUND).
107 The layer must still be registered.
126 "^layer@[0-9]+$":
133 xylon,layer-depth:
137 xylon,layer-colorspace:
145 xylon,layer-alpha-mode:
147 # Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0)
148 - layer
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| /linux-6.1.9/drivers/gpu/drm/logicvc/ |
| D | logicvc_layer.c | 87 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_check() local
111 ret = logicvc_layer_buffer_find_setup(logicvc, layer, new_state, in logicvc_plane_atomic_check()
123 layer->index != (logicvc->config.layers_count - 1) && in logicvc_plane_atomic_check()
140 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_update() local
149 u32 index = layer->index; in logicvc_plane_atomic_update()
167 logicvc_layer_buffer_find_setup(logicvc, layer, new_state, in logicvc_plane_atomic_update()
191 if (layer->config.alpha_mode == LOGICVC_LAYER_ALPHA_LAYER) { in logicvc_plane_atomic_update()
196 switch (layer->config.depth) { in logicvc_plane_atomic_update()
201 if (layer->config.colorspace == in logicvc_plane_atomic_update()
237 struct logicvc_layer *layer = logicvc_layer(drm_plane); in logicvc_plane_atomic_disable() local
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| /linux-6.1.9/drivers/gpu/drm/sun4i/ |
| D | sun4i_layer.c | 69 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_disable() local
70 struct sun4i_backend *backend = layer->backend; in sun4i_backend_layer_atomic_disable()
72 sun4i_backend_layer_enable(backend, layer->id, false); in sun4i_backend_layer_atomic_disable()
89 struct sun4i_layer *layer = plane_to_sun4i_layer(plane); in sun4i_backend_layer_atomic_update() local
90 struct sun4i_backend *backend = layer->backend; in sun4i_backend_layer_atomic_update()
93 sun4i_backend_cleanup_layer(backend, layer->id); in sun4i_backend_layer_atomic_update()
101 sun4i_backend_update_layer_frontend(backend, layer->id, in sun4i_backend_layer_atomic_update()
105 sun4i_backend_update_layer_formats(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
106 sun4i_backend_update_layer_buffer(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
109 sun4i_backend_update_layer_coord(backend, layer->id, plane); in sun4i_backend_layer_atomic_update()
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| D | sun8i_ui_layer.h | 17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
18 ((base) + 0x20 * (layer) + 0x0)
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
20 ((base) + 0x20 * (layer) + 0x4)
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
22 ((base) + 0x20 * (layer) + 0x8)
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
24 ((base) + 0x20 * (layer) + 0xc)
25 #define SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(base, layer) \ argument
26 ((base) + 0x20 * (layer) + 0x10)
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| D | sun8i_ui_layer.c | 235 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); in sun8i_ui_layer_atomic_check() local
251 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { in sun8i_ui_layer_atomic_check()
267 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); in sun8i_ui_layer_atomic_disable() local
269 struct sun8i_mixer *mixer = layer->mixer; in sun8i_ui_layer_atomic_disable()
271 sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0, in sun8i_ui_layer_atomic_disable()
282 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); in sun8i_ui_layer_atomic_update() local
285 struct sun8i_mixer *mixer = layer->mixer; in sun8i_ui_layer_atomic_update()
288 sun8i_ui_layer_enable(mixer, layer->channel, in sun8i_ui_layer_atomic_update()
289 layer->overlay, false, 0, old_zpos); in sun8i_ui_layer_atomic_update()
293 sun8i_ui_layer_update_coord(mixer, layer->channel, in sun8i_ui_layer_atomic_update()
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| D | sun8i_vi_layer.h | 11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
12 ((base) + 0x30 * (layer) + 0x0)
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
14 ((base) + 0x30 * (layer) + 0x4)
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
16 ((base) + 0x30 * (layer) + 0x8)
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
18 ((base) + 0x30 * (layer) + 0xc + 4 * (plane))
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
20 ((base) + 0x30 * (layer) + 0x18 + 4 * (plane))
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| D | sun8i_csc.c | 143 static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, in sun8i_de3_ccsc_set_coefficients() argument
156 addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); in sun8i_de3_ccsc_set_coefficients()
163 layer, in sun8i_de3_ccsc_set_coefficients()
167 layer, in sun8i_de3_ccsc_set_coefficients()
171 layer, i); in sun8i_de3_ccsc_set_coefficients()
193 static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) in sun8i_de3_ccsc_enable() argument
197 mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); in sun8i_de3_ccsc_enable()
208 void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, in sun8i_csc_set_ccsc_coefficients() argument
216 sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, in sun8i_csc_set_ccsc_coefficients()
221 base = ccsc_base[mixer->cfg->ccsc][layer]; in sun8i_csc_set_ccsc_coefficients()
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| D | sun8i_vi_layer.c | 369 struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); in sun8i_vi_layer_atomic_check() local
385 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { in sun8i_vi_layer_atomic_check()
401 struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); in sun8i_vi_layer_atomic_disable() local
403 struct sun8i_mixer *mixer = layer->mixer; in sun8i_vi_layer_atomic_disable()
405 sun8i_vi_layer_enable(mixer, layer->channel, layer->overlay, false, 0, in sun8i_vi_layer_atomic_disable()
416 struct sun8i_vi_layer *layer = plane_to_sun8i_vi_layer(plane); in sun8i_vi_layer_atomic_update() local
419 struct sun8i_mixer *mixer = layer->mixer; in sun8i_vi_layer_atomic_update()
422 sun8i_vi_layer_enable(mixer, layer->channel, in sun8i_vi_layer_atomic_update()
423 layer->overlay, false, 0, old_zpos); in sun8i_vi_layer_atomic_update()
427 sun8i_vi_layer_update_coord(mixer, layer->channel, in sun8i_vi_layer_atomic_update()
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| D | sun4i_backend.c | 82 int layer, bool enable) in sun4i_backend_layer_enable() argument
87 layer); in sun4i_backend_layer_enable()
90 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); in sun4i_backend_layer_enable()
95 SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); in sun4i_backend_layer_enable()
170 int layer, struct drm_plane *plane) in sun4i_backend_update_layer_coord() argument
174 DRM_DEBUG_DRIVER("Updating layer %d\n", layer); in sun4i_backend_update_layer_coord()
179 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer), in sun4i_backend_update_layer_coord()
186 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer), in sun4i_backend_update_layer_coord()
194 int layer, struct drm_plane *plane) in sun4i_backend_update_yuv_format() argument
212 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), in sun4i_backend_update_yuv_format()
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| /linux-6.1.9/drivers/gpu/drm/xlnx/ |
| D | zynqmp_disp.c | 419 static bool zynqmp_disp_layer_is_gfx(const struct zynqmp_disp_layer *layer) in zynqmp_disp_layer_is_gfx() argument
421 return layer->id == ZYNQMP_DISP_LAYER_GFX; in zynqmp_disp_layer_is_gfx()
424 static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer) in zynqmp_disp_layer_is_video() argument
426 return layer->id == ZYNQMP_DISP_LAYER_VID; in zynqmp_disp_layer_is_video()
438 struct zynqmp_disp_layer *layer, in zynqmp_disp_avbuf_set_format() argument
445 val &= zynqmp_disp_layer_is_video(layer) in zynqmp_disp_avbuf_set_format()
452 unsigned int reg = zynqmp_disp_layer_is_video(layer) in zynqmp_disp_avbuf_set_format()
574 struct zynqmp_disp_layer *layer, in zynqmp_disp_avbuf_enable_video() argument
580 if (zynqmp_disp_layer_is_video(layer)) { in zynqmp_disp_avbuf_enable_video()
605 struct zynqmp_disp_layer *layer) in zynqmp_disp_avbuf_disable_video() argument
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| /linux-6.1.9/net/caif/ |
| D | caif_dev.c | 34 struct cflayer layer; member
160 caifd->layer.up-> in caif_flow_cb()
161 ctrlcmd(caifd->layer.up, in caif_flow_cb()
163 caifd->layer.id); in caif_flow_cb()
167 static int transmit(struct cflayer *layer, struct cfpkt *pkt) in transmit() argument
171 container_of(layer, struct caif_device_entry, layer); in transmit()
229 caifd->layer.up->ctrlcmd(caifd->layer.up, in transmit()
231 caifd->layer.id); in transmit()
258 if (!caifd || !caifd->layer.up || !caifd->layer.up->receive || in receive()
269 err = caifd->layer.up->receive(caifd->layer.up, pkt); in receive()
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| D | cfserl.c | 22 struct cflayer layer; member
34 void cfserl_release(struct cflayer *layer) in cfserl_release() argument
36 kfree(layer); in cfserl_release()
44 caif_assert(offsetof(struct cfserl, layer) == 0); in cfserl_create()
45 this->layer.receive = cfserl_receive; in cfserl_create()
46 this->layer.transmit = cfserl_transmit; in cfserl_create()
47 this->layer.ctrlcmd = cfserl_ctrlcmd; in cfserl_create()
50 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "ser1"); in cfserl_create()
51 return &this->layer; in cfserl_create()
157 ret = layr->layer.up->receive(layr->layer.up, pkt); in cfserl_receive()
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| D | caif_usb.c | 32 struct cflayer layer; member
54 struct cfusbl *usbl = container_of(layr, struct cfusbl, layer); in cfusbl_transmit()
92 caif_assert(offsetof(struct cfusbl, layer) == 0); in cfusbl_create()
94 memset(&this->layer, 0, sizeof(this->layer)); in cfusbl_create()
95 this->layer.receive = cfusbl_receive; in cfusbl_create()
96 this->layer.transmit = cfusbl_transmit; in cfusbl_create()
97 this->layer.ctrlcmd = cfusbl_ctrlcmd; in cfusbl_create()
98 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "usb%d", phyid); in cfusbl_create()
99 this->layer.id = phyid; in cfusbl_create()
118 static void cfusbl_release(struct cflayer *layer) in cfusbl_release() argument
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| D | cfsrvl.c | 25 #define container_obj(layr) container_of(layr, struct cfsrvl, layer)
121 info->channel_id = service->layer.id; in cfservl_modemcmd()
142 info->channel_id = service->layer.id; in cfservl_modemcmd()
154 static void cfsrvl_release(struct cflayer *layer) in cfsrvl_release() argument
156 struct cfsrvl *service = container_of(layer, struct cfsrvl, layer); in cfsrvl_release()
165 caif_assert(offsetof(struct cfsrvl, layer) == 0); in cfsrvl_init()
169 service->layer.id = channel_id; in cfsrvl_init()
170 service->layer.ctrlcmd = cfservl_ctrlcmd; in cfsrvl_init()
171 service->layer.modemcmd = cfservl_modemcmd; in cfsrvl_init()
186 u8 cfsrvl_getphyid(struct cflayer *layer) in cfsrvl_getphyid() argument
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| D | cfctrl.c | 17 #define container_obj(layr) container_of(layr, struct cfctrl, serv.layer)
42 caif_assert(offsetof(struct cfctrl, serv.layer) == 0); in cfctrl_create()
48 this->serv.layer.receive = cfctrl_recv; in cfctrl_create()
49 sprintf(this->serv.layer.name, "ctrl"); in cfctrl_create()
50 this->serv.layer.ctrlcmd = cfctrl_ctrlcmd; in cfctrl_create()
57 return &this->serv.layer; in cfctrl_create()
60 void cfctrl_remove(struct cflayer *layer) in cfctrl_remove() argument
63 struct cfctrl *ctrl = container_obj(layer); in cfctrl_remove()
71 kfree(layer); in cfctrl_remove()
163 struct cfctrl_rsp *cfctrl_get_respfuncs(struct cflayer *layer) in cfctrl_get_respfuncs() argument
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| D | cfmuxl.c | 18 #define container_obj(layr) container_of(layr, struct cfmuxl, layer)
25 struct cflayer layer; member
54 this->layer.receive = cfmuxl_receive; in cfmuxl_create()
55 this->layer.transmit = cfmuxl_transmit; in cfmuxl_create()
56 this->layer.ctrlcmd = cfmuxl_ctrlcmd; in cfmuxl_create()
61 snprintf(this->layer.name, CAIF_LAYER_NAME_SZ, "mux"); in cfmuxl_create()
62 return &this->layer; in cfmuxl_create()
250 struct cflayer *layer; in cfmuxl_ctrlcmd() local
253 list_for_each_entry_rcu(layer, &muxl->srvl_list, node) { in cfmuxl_ctrlcmd()
255 if (cfsrvl_phyid_match(layer, phyid) && layer->ctrlcmd) { in cfmuxl_ctrlcmd()
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| /linux-6.1.9/drivers/gpu/drm/atmel-hlcdc/ |
| D | atmel_hlcdc_dc.h | 276 struct atmel_hlcdc_layer layer; member
286 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) in atmel_hlcdc_layer_to_plane() argument
288 return container_of(layer, struct atmel_hlcdc_plane, layer); in atmel_hlcdc_layer_to_plane()
351 static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_write_reg() argument
354 regmap_write(layer->regmap, layer->desc->regs_offset + reg, val); in atmel_hlcdc_layer_write_reg()
357 static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_read_reg() argument
362 regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val); in atmel_hlcdc_layer_read_reg()
367 static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer, in atmel_hlcdc_layer_write_cfg() argument
370 atmel_hlcdc_layer_write_reg(layer, in atmel_hlcdc_layer_write_cfg()
371 layer->desc->cfgs_offset + in atmel_hlcdc_layer_write_cfg()
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| D | atmel_hlcdc_plane.c | 281 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i, in atmel_hlcdc_plane_scaler_set_phicoeff()
288 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_hlcdc_plane_setup_scaler()
295 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_hlcdc_plane_setup_scaler()
327 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, in atmel_hlcdc_plane_setup_scaler()
337 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_hlcdc_plane_update_pos_and_size()
340 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size, in atmel_hlcdc_plane_update_pos_and_size()
345 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_hlcdc_plane_update_pos_and_size()
351 atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.pos, in atmel_hlcdc_plane_update_pos_and_size()
363 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_hlcdc_plane_update_general_settings()
373 atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_HLCDC_LAYER_DMA_CFG, in atmel_hlcdc_plane_update_general_settings()
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| /linux-6.1.9/Documentation/networking/caif/ |
| D | linux_caif.rst | 66 CAIF Core layer implements the CAIF protocol as defined by ST-Ericsson.
68 each layer described in the specification is implemented as a separate layer.
78 - Layered architecture (a la Streams), each layer in the CAIF
80 - Clients must call configuration function to add PHY layer.
81 - Clients must implement CAIF layer to consume/produce
84 Client layer.
100 - CFCNFG CAIF Configuration layer. Configures the CAIF Protocol
104 - CFCTRL CAIF Control layer. Encodes and Decodes control messages
111 - CFVEI CAIF VEI layer. Handles CAIF AT Channels on VEI (Virtual
112 External Interface). This layer encodes/decodes VEI frames.
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| /linux-6.1.9/Documentation/hid/ |
| D | amd-sfh-hid.rst | 49 sensor data. The layer, which binds each device (AMD SFH HID driver) identifies the device type and
50 registers with the HID core. Transport layer attaches a constant "struct hid_ll_driver" object with
52 used by HID core to communicate with the device. AMD HID Transport layer implements the synchronous…
56 This layer is responsible to implement HID requests and descriptors. As firmware is OS agnostic, HID
57 client layer fills the HID request structure and descriptors. HID client layer is complex as it is
58 interface between MP2 PCIe layer and HID. HID client layer initializes the MP2 PCIe layer and holds
59 the instance of MP2 layer. It identifies the number of sensors connected using MP2-PCIe layer. Based
61 enumeration of each sensor, client layer fills the HID Descriptor structure and HID input report
65 AMD MP2 PCIe layer
76 interrupt to MP2. The client layer allocates the physical memory and the same is sent to MP2 via
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| /linux-6.1.9/fs/overlayfs/ |
| D | export.c | 94 return oe->lowerstack[0].layer->idx; in ovl_connectable_layer()
115 origin_layer = OVL_E(dentry)->lowerstack[0].layer->idx; in ovl_connect_layer()
323 oe->lowerstack->layer = lowerpath->layer; in ovl_obtain_alias()
352 if (oe->lowerstack[i].layer->idx == idx) in ovl_dentry_real_at()
367 const struct ovl_layer *layer) in ovl_lookup_real_one() argument
384 if (ovl_dentry_real_at(connected, layer->idx) != parent) in ovl_lookup_real_one()
408 } else if (ovl_dentry_real_at(this, layer->idx) != real) { in ovl_lookup_real_one()
421 real, layer->idx, connected, err); in ovl_lookup_real_one()
428 const struct ovl_layer *layer);
435 const struct ovl_layer *layer) in ovl_lookup_real_inode() argument
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