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Searched refs:dpcd (Results 1 – 25 of 40) sorted by relevance

12

/linux-6.1.9/include/drm/display/
Ddrm_dp_helper.h47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
107 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
109 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
113 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
115 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
119 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap()
121 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
[all …]
/linux-6.1.9/drivers/gpu/drm/display/
Ddrm_dp_helper.c284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in __read_delay()
300 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in __read_delay()
326 rd_interval = dpcd[offset]; in __read_delay()
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_clock_recovery_delay()
342 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_read_channel_eq_delay()
349 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
374 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
376 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
380 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
[all …]
/linux-6.1.9/drivers/gpu/drm/nouveau/
Dnouveau_dp.c43 return drm_dp_read_sink_count_cap(connector, outp->dp.dpcd, &outp->dp.desc); in nouveau_dp_has_sink_count()
55 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd() local
57 ret = drm_dp_read_dpcd_caps(aux, dpcd); in nouveau_dp_probe_dpcd()
61 ret = drm_dp_read_desc(aux, &outp->dp.desc, drm_dp_is_branch(dpcd)); in nouveau_dp_probe_dpcd()
68 mstm->can_mst = drm_dp_read_mst_cap(aux, dpcd); in nouveau_dp_probe_dpcd()
86 ret = drm_dp_read_downstream_info(aux, dpcd, in nouveau_dp_probe_dpcd()
109 u8 *dpcd = nv_encoder->dp.dpcd; in nouveau_dp_detect() local
116 dpcd[DP_DPCD_REV] != 0) in nouveau_dp_detect()
156 nv_encoder->dp.link_bw = 27000 * dpcd[DP_MAX_LINK_RATE]; in nouveau_dp_detect()
158 dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_detect()
[all …]
Dnouveau_encoder.h83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Datombios_dp.c253 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
260 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
261 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in amdgpu_atombios_dp_probe_oui()
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in amdgpu_atombios_dp_get_dpcd()
362 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
369 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_set_link_config()
[all …]
/linux-6.1.9/drivers/gpu/drm/bridge/analogix/
Danalogix-anx6345.c64 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
100 u8 dp_bw, dpcd[2]; in anx6345_dp_link_training() local
135 &anx6345->dpcd, DP_RECEIVER_CAP_SIZE); in anx6345_dp_link_training()
151 if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) { in anx6345_dp_link_training()
152 err = drm_dp_dpcd_readb(&anx6345->aux, DP_SET_POWER, &dpcd[0]); in anx6345_dp_link_training()
159 dpcd[0] &= ~DP_SET_POWER_MASK; in anx6345_dp_link_training()
160 dpcd[0] |= DP_SET_POWER_D0; in anx6345_dp_link_training()
162 err = drm_dp_dpcd_writeb(&anx6345->aux, DP_SET_POWER, dpcd[0]); in anx6345_dp_link_training()
183 if (anx6345->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { in anx6345_dp_link_training()
202 if (drm_dp_enhanced_frame_cap(anx6345->dpcd)) in anx6345_dp_link_training()
[all …]
Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 u8 dp_bw, dpcd[2]; in anx78xx_dp_link_training() local
647 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE); in anx78xx_dp_link_training()
663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { in anx78xx_dp_link_training()
664 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SET_POWER, &dpcd[0]); in anx78xx_dp_link_training()
671 dpcd[0] &= ~DP_SET_POWER_MASK; in anx78xx_dp_link_training()
672 dpcd[0] |= DP_SET_POWER_D0; in anx78xx_dp_link_training()
674 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_SET_POWER, dpcd[0]); in anx78xx_dp_link_training()
695 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) { in anx78xx_dp_link_training()
714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
[all …]
/linux-6.1.9/drivers/gpu/drm/radeon/
Datombios_dp.c307 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
313 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
314 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
375 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
396 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
398 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
399 dig_connector->dpcd); in radeon_dp_getdpcd()
406 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
463 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
490 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
[all …]
/linux-6.1.9/drivers/gpu/drm/msm/dp/
Ddp_panel.c30 u8 *dpcd, major = 0, minor = 0, temp; in dp_panel_read_dpcd() local
33 dpcd = dp_panel->dpcd; in dp_panel_read_dpcd()
39 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
50 temp = dpcd[DP_TRAINING_AUX_RD_INTERVAL]; in dp_panel_read_dpcd()
60 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
71 link_info->revision = dpcd[DP_DPCD_REV]; in dp_panel_read_dpcd()
75 link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in dp_panel_read_dpcd()
76 link_info->num_lanes = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in dp_panel_read_dpcd()
89 if (drm_dp_enhanced_frame_cap(dpcd)) in dp_panel_read_dpcd()
92 dp_panel->dfp_present = dpcd[DP_DOWNSTREAMPORT_PRESENT]; in dp_panel_read_dpcd()
[all …]
Ddp_ctrl.c124 const u8 *dpcd = ctrl->panel->dpcd; in dp_ctrl_config_ctrl() local
130 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) in dp_ctrl_config_ctrl()
147 if (drm_dp_enhanced_frame_cap(dpcd)) in dp_ctrl_config_ctrl()
1108 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); in dp_ctrl_link_train_1()
1186 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in dp_ctrl_clear_training_pattern()
1202 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in dp_ctrl_link_train_2()
1205 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in dp_ctrl_link_train_2()
1220 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in dp_ctrl_link_train_2()
1245 const u8 *dpcd = ctrl->panel->dpcd; in dp_ctrl_link_train() local
1258 if (drm_dp_max_downspread(dpcd)) in dp_ctrl_link_train()
[all …]
Ddp_panel.h39 u8 dpcd[DP_RECEIVER_CAP_SIZE + 1]; member
/linux-6.1.9/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddp.c206 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x14 && in nvkm_dp_train_eq()
207 lt->outp->dp.dpcd[DPCD_RC03] & DPCD_RC03_TPS4_SUPPORTED) in nvkm_dp_train_eq()
210 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] >= 0x12 && in nvkm_dp_train_eq()
211 lt->outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
216 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_eq()
248 if (lt->outp->dp.dpcd[DPCD_RC00_DPCD_REV] < 0x14 && !lt->repeater) in nvkm_dp_train_cr()
249 usec = (lt->outp->dp.dpcd[DPCD_RC0E] & DPCD_RC0E_AUX_RD_INTERVAL) * 4000; in nvkm_dp_train_cr()
294 outp->dp.dpcd[DPCD_RC03] &= ~DPCD_RC03_TPS4_SUPPORTED; in nvkm_dp_train_links()
296 outp->dp.dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
297 lt.pc2 = outp->dp.dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
[all …]
Doutp.h40 u8 dpcd[16]; member
43 int dpcd; /* -1, or index into SUPPORTED_LINK_RATES table */ member
/linux-6.1.9/drivers/gpu/drm/tegra/
Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe() local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in drm_dp_link_probe()
182 link->revision = dpcd[DP_DPCD_REV]; in drm_dp_link_probe()
183 link->max_rate = drm_dp_max_link_rate(dpcd); in drm_dp_link_probe()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); in drm_dp_link_probe()
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); in drm_dp_link_probe()
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd); in drm_dp_link_probe()
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); in drm_dp_link_probe()
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in drm_dp_link_probe()
[all …]
/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c47 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in intel_dp_read_lttpr_phy_caps()
53 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
70 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_read_lttpr_common_caps()
75 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, in intel_dp_read_lttpr_common_caps()
106 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in intel_dp_init_lttpr()
113 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) in intel_dp_init_lttpr()
152 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); in intel_dp_init_lttpr()
186 u8 dpcd[DP_RECEIVER_CAP_SIZE]; in intel_dp_init_lttpr_and_dprx_caps() local
191 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) in intel_dp_init_lttpr_and_dprx_caps()
194 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); in intel_dp_init_lttpr_and_dprx_caps()
[all …]
Dintel_dp.c155 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in intel_dp_set_dpcd_sink_rates()
170 if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { in intel_dp_set_dpcd_sink_rates()
234 intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_set_max_sink_lane_count()
2173 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
2174 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
2237 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_set_power()
2298 if (intel_dp->dpcd[DP_DPCD_REV] == 0) in intel_dp_sync_state()
2496 if (drm_dp_is_branch(intel_dp->dpcd) && in intel_dp_is_hdmi_2_1_sink()
2657 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) in intel_dp_configure_protocol_converter()
2660 if (!drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_configure_protocol_converter()
[all …]
/linux-6.1.9/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c262 uint8_t dpcd[4]; member
325 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
326 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; in cdv_intel_dp_max_lane_count()
341 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; in cdv_intel_dp_max_link_bw()
1075 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && in cdv_intel_dp_mode_set()
1076 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { in cdv_intel_dp_mode_set()
1111 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1670 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd, in cdv_dp_detect()
1671 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1673 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
[all …]
/linux-6.1.9/drivers/gpu/drm/i915/gvt/
Ddisplay.c516 kfree(port->dpcd); in clean_virtual_dp_monitor()
517 port->dpcd = NULL; in clean_virtual_dp_monitor()
549 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); in setup_virtual_dp_monitor()
550 if (!port->dpcd) { in setup_virtual_dp_monitor()
559 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); in setup_virtual_dp_monitor()
560 port->dpcd->data_valid = true; in setup_virtual_dp_monitor()
561 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
Dhandlers.c1116 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, in dp_aux_ch_ctl_link_training() argument
1122 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; in dp_aux_ch_ctl_link_training()
1124 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; in dp_aux_ch_ctl_link_training()
1129 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; in dp_aux_ch_ctl_link_training()
1130 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; in dp_aux_ch_ctl_link_training()
1132 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; in dp_aux_ch_ctl_link_training()
1133 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; in dp_aux_ch_ctl_link_training()
1135 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= in dp_aux_ch_ctl_link_training()
1141 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; in dp_aux_ch_ctl_link_training()
1161 struct intel_vgpu_dpcd_data *dpcd = NULL; in dp_aux_ch_ctl_mmio_write() local
[all …]
/linux-6.1.9/drivers/gpu/drm/bridge/
Dite-it6505.c427 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num) in it6505_get_dpcd() argument
611 ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num); in it6505_get_dpcd()
617 num, dpcd); in it6505_get_dpcd()
1446 return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01; in it6505_use_step_train_check()
1457 if (it6505->dpcd[0] == 0) { in it6505_parse_link_capabilities()
1459 it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd, in it6505_parse_link_capabilities()
1460 ARRAY_SIZE(it6505->dpcd)); in it6505_parse_link_capabilities()
1480 it6505->branch_device = drm_dp_is_branch(it6505->dpcd); in it6505_parse_link_capabilities()
1488 it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] & in it6505_parse_link_capabilities()
[all …]
Dtc358767.c274 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
735 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
740 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
741 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
742 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
778 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
1083 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1130 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1400 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_edp_stream_enable()
/linux-6.1.9/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c318 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
711 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_cr()
759 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
760 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
776 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_ce()
810 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd); in zynqmp_dp_train()
816 if (dp->dpcd[3] & 0x1) { in zynqmp_dp_train()
1307 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in zynqmp_dp_connector_detect()
1308 sizeof(dp->dpcd)); in zynqmp_dp_connector_detect()
1315 drm_dp_max_link_rate(dp->dpcd), in zynqmp_dp_connector_detect()
[all …]
/linux-6.1.9/Documentation/devicetree/bindings/display/exynos/
Dexynos_dp.txt67 -samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
68 -samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
/linux-6.1.9/drivers/gpu/drm/bridge/cadence/
Dcdns-mhdp8546-core.c1385 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps()
1393 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1398 if (drm_dp_tps3_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1400 if (drm_dp_tps4_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1404 mhdp->sink.fast_link = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1410 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up() local
1426 err = drm_dp_dpcd_read(&mhdp->aux, addr, dpcd, DP_RECEIVER_CAP_SIZE); in cdns_mhdp_link_up()
1432 mhdp->link.revision = dpcd[0]; in cdns_mhdp_link_up()
1433 mhdp->link.rate = drm_dp_bw_code_to_link_rate(dpcd[1]); in cdns_mhdp_link_up()
1434 mhdp->link.num_lanes = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in cdns_mhdp_link_up()
[all …]
/linux-6.1.9/drivers/gpu/drm/rockchip/
Dcdn-dp-core.h103 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member

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