| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-cpu.c | 68 struct rockchip_cpuclk *cpuclk, unsigned long rate) in rockchip_get_cpuclk_settings() argument
71 cpuclk->rate_table; in rockchip_get_cpuclk_settings()
74 for (i = 0; i < cpuclk->rate_count; i++) { in rockchip_get_cpuclk_settings()
85 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); in rockchip_cpuclk_recalc_rate() local
86 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_recalc_rate()
87 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]); in rockchip_cpuclk_recalc_rate()
98 static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, in rockchip_cpuclk_set_dividers() argument
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
116 static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, in rockchip_cpuclk_pre_rate_change() argument
119 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_pre_rate_change()
[all …]
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| /linux-6.1.9/drivers/clk/mvebu/ |
| D | clk-cpu.c | 51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_recalc_rate() local
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate()
78 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_off_set_rate() local
83 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate()
84 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8)))) in clk_cpu_off_set_rate()
85 | (div << (cpuclk->cpu * 8)); in clk_cpu_off_set_rate()
86 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_off_set_rate()
88 reload_mask = 1 << (20 + cpuclk->cpu); in clk_cpu_off_set_rate()
90 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
[all …]
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| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-cpu.c | 150 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_pre_rate_change() argument
152 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_pre_rate_change()
153 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change()
165 spin_lock_irqsave(cpuclk->lock, flags); in exynos_cpuclk_pre_rate_change()
173 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()
194 if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { in exynos_cpuclk_pre_rate_change()
215 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()
221 spin_unlock_irqrestore(cpuclk->lock, flags); in exynos_cpuclk_pre_rate_change()
227 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_post_rate_change() argument
229 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_post_rate_change()
[all …]
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| /linux-6.1.9/drivers/cpufreq/ |
| D | sh-cpufreq.c | 47 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in __sh_cpufreq_target() local
58 freq = clk_round_rate(cpuclk, target->freq * 1000); in __sh_cpufreq_target()
70 clk_set_rate(cpuclk, freq); in __sh_cpufreq_target()
91 struct clk *cpuclk = &per_cpu(sh_cpuclk, policy->cpu); in sh_cpufreq_verify() local
94 freq_table = cpuclk->nr_freqs ? cpuclk->freq_table : NULL; in sh_cpufreq_verify()
100 policy->min = (clk_round_rate(cpuclk, 1) + 500) / 1000; in sh_cpufreq_verify()
101 policy->max = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000; in sh_cpufreq_verify()
110 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in sh_cpufreq_cpu_init() local
116 cpuclk = clk_get(dev, "cpu_clk"); in sh_cpufreq_cpu_init()
117 if (IS_ERR(cpuclk)) { in sh_cpufreq_cpu_init()
[all …]
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| /linux-6.1.9/arch/mips/txx9/generic/ |
| D | setup_tx4927.c | 92 unsigned int cpuclk = 0; in tx4927_setup() local
126 cpuclk = txx9_gbus_clock * 2; break; in tx4927_setup()
129 cpuclk = txx9_gbus_clock * 5 / 2; break; in tx4927_setup()
132 cpuclk = txx9_gbus_clock * 3; break; in tx4927_setup()
135 cpuclk = txx9_gbus_clock * 4; break; in tx4927_setup()
137 txx9_cpu_clock = cpuclk; in tx4927_setup()
142 cpuclk = txx9_cpu_clock; in tx4927_setup()
147 txx9_gbus_clock = cpuclk / 2; break; in tx4927_setup()
150 txx9_gbus_clock = cpuclk * 2 / 5; break; in tx4927_setup()
153 txx9_gbus_clock = cpuclk / 3; break; in tx4927_setup()
[all …]
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| D | setup_tx4938.c | 97 unsigned int cpuclk = 0; in tx4938_setup() local
132 cpuclk = txx9_gbus_clock * 2; break; in tx4938_setup()
135 cpuclk = txx9_gbus_clock * 5 / 2; break; in tx4938_setup()
138 cpuclk = txx9_gbus_clock * 3; break; in tx4938_setup()
141 cpuclk = txx9_gbus_clock * 4; break; in tx4938_setup()
144 cpuclk = txx9_gbus_clock * 9 / 2; break; in tx4938_setup()
146 txx9_cpu_clock = cpuclk; in tx4938_setup()
151 cpuclk = txx9_cpu_clock; in tx4938_setup()
156 txx9_gbus_clock = cpuclk / 2; break; in tx4938_setup()
159 txx9_gbus_clock = cpuclk * 2 / 5; break; in tx4938_setup()
[all …]
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| /linux-6.1.9/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 9 1 = cpuclk (CPU clock)
16 1 = cpuclk (CPU clock)
22 1 = cpuclk (CPU clock)
28 1 = cpuclk (CPU clock)
36 1 = cpuclk (CPU clock)
42 1 = cpuclk (CPU0 clock)
48 1 = cpuclk (CPU0 clock)
72 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
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| D | mvebu-cpu-clock.txt | 12 cpuclk: clock-complex@d0018700 {
22 clocks = <&cpuclk 0>;
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| /linux-6.1.9/arch/mips/cavium-octeon/ |
| D | oct_ilm.c | 33 u64 cpuclk, avg, max, min; in oct_ilm_show() local
36 cpuclk = octeon_get_clock_rate(); in oct_ilm_show()
38 max = (curr_li.max_latency * 1000000000) / cpuclk; in oct_ilm_show()
39 min = (curr_li.min_latency * 1000000000) / cpuclk; in oct_ilm_show()
40 avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt); in oct_ilm_show()
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| /linux-6.1.9/drivers/clk/qcom/ |
| D | clk-cpu-8996.c | 268 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); in clk_cpu_8996_pmux_get_parent() local
271 regmap_read(clkr->regmap, cpuclk->reg, &val); in clk_cpu_8996_pmux_get_parent()
279 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); in clk_cpu_8996_pmux_set_parent() local
284 return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val); in clk_cpu_8996_pmux_set_parent()
490 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb); in cpu_clk_notifier_cb() local
496 ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); in cpu_clk_notifier_cb()
501 ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, in cpu_clk_notifier_cb()
504 ret = clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, in cpu_clk_notifier_cb()
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | mstar-infinity2m.dtsi | 30 clock-names = "cpuclk";
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| D | armada-xp-98dx3336.dtsi | 22 clocks = <&cpuclk 1>;
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| D | armada-xp-mv78460.dtsi | 35 clocks = <&cpuclk 0>;
43 clocks = <&cpuclk 1>;
51 clocks = <&cpuclk 2>;
59 clocks = <&cpuclk 3>;
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| D | armada-xp-98dx4251.dtsi | 22 clocks = <&cpuclk 1>;
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| D | armada-xp-mv78230.dtsi | 33 clocks = <&cpuclk 0>;
41 clocks = <&cpuclk 1>;
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| D | armada-xp-98dx3236.dtsi | 35 clocks = <&cpuclk 0>;
158 cpuclk: clock-complex@18700 { label
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| D | mstar-v7.dtsi | 25 clock-names = "cpuclk";
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| D | armada-xp-mv78260.dtsi | 34 clocks = <&cpuclk 0>;
42 clocks = <&cpuclk 1>;
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| D | armada-xp.dtsi | 102 cpuclk: clock-complex@18700 { label
|