Searched refs:cntr_val (Results 1 – 9 of 9) sorted by relevance
125 CHECKREGIDX(TRCCNTVRn(0), cntr_val, idx, off_mask); in etm4_cfg_map_reg_offset()
193 u32 cntr_val[ETM_MAX_CNTR]; member
226 config->cntr_val[i] = 0x0; in etm_set_default()402 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i)); in etm_enable_hw()583 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i)); in etm_disable_hw()
433 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); in etm4_enable_hw()548 if (config->cntr_val[ctridx] == 0) in etm4_config_timestamp_event()582 config->cntr_val[ctridx] = 1; in etm4_config_timestamp_event()858 config->cntr_val[i] = in etm4_disable_hw()
728 i, config->cntr_val[i]); in cntr_val_show()755 config->cntr_val[config->cntr_idx] = val; in cntr_val_store()760 static DEVICE_ATTR_RW(cntr_val);
871 u32 cntr_val[ETMv4_MAX_CNTR]; member945 u32 cntr_val[ETMv4_MAX_CNTR]; member
236 config->cntr_val[i] = 0x0; in reset_store()1593 val = config->cntr_val[idx]; in cntr_val_show()1614 config->cntr_val[idx] = val; in cntr_val_store()1618 static DEVICE_ATTR_RW(cntr_val);
74 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val
221 What: /sys/bus/coresight/devices/etm<N>/cntr_val