| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| D | clk_mgr.c | 99 void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_exit_optimized_pwr_state() argument
117 clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active; in clk_mgr_exit_optimized_pwr_state()
124 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_optimize_pwr_state() argument
138 &clk_mgr->psr_allow_active_cache, false, false, NULL); in clk_mgr_optimize_pwr_state()
147 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create()
154 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local
156 if (clk_mgr == NULL) { in dc_clk_mgr_create()
160 dce60_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
161 dce_clk_mgr_construct(ctx, clk_mgr); in dc_clk_mgr_create()
162 return &clk_mgr->base; in dc_clk_mgr_create()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 49 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
52 (clk_mgr->regs->reg)
80 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *en… in dcn3_init_single_clock() argument
84 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); in dcn3_init_single_clock()
96 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); in dcn3_init_single_clock()
97 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
101 static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr) in dcn3_build_wm_range_table() argument
104 dcn3_fpu_build_wm_range_table(&clk_mgr->base); in dcn3_build_wm_range_table()
108 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) in dcn3_init_clocks()
110 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_init_clocks() local
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| D | dcn30_clk_mgr_smu_msg.c | 55 static uint32_t dcn30_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn30_smu_wait_for_response() argument
77 static bool dcn30_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32… in dcn30_smu_send_msg_with_param() argument
81 dcn30_smu_wait_for_response(clk_mgr, 10, 200000); in dcn30_smu_send_msg_with_param()
92 result = dcn30_smu_wait_for_response(clk_mgr, 10, 200000); in dcn30_smu_send_msg_with_param()
110 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input) in dcn30_smu_test_message() argument
116 if (dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_test_message()
124 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version) in dcn30_smu_get_smu_version() argument
128 if (dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_get_smu_version()
140 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr) in dcn30_smu_check_driver_if_version() argument
146 if (dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_check_driver_if_version()
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| D | dcn30_clk_mgr_smu_msg.h | 33 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input);
34 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version);
35 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr);
36 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr);
37 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
38 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
39 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
40 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
41 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_…
42 unsigned int dcn30_smu_set_hard_max_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_…
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 79 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
82 (clk_mgr->regs->reg)
125 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *en… in dcn32_init_single_clock() argument
131 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF); in dcn32_init_single_clock()
143 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF); in dcn32_init_single_clock()
144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn32_init_single_clock()
148 static void dcn32_build_wm_range_table(struct clk_mgr_internal *clk_mgr) in dcn32_build_wm_range_table() argument
151 dcn32_build_wm_range_table_fpu(clk_mgr); in dcn32_build_wm_range_table()
155 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) in dcn32_init_clocks()
157 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn32_init_clocks() local
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_smu.c | 102 static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn316_smu_wait_for_response() argument
121 struct clk_mgr_internal *clk_mgr, in dcn316_smu_send_msg_with_param() argument
126 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); in dcn316_smu_send_msg_with_param()
144 result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000); in dcn316_smu_send_msg_with_param()
154 int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn316_smu_get_smu_version() argument
157 clk_mgr, in dcn316_smu_get_smu_version()
163 int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn316_smu_set_dispclk() argument
167 if (!clk_mgr->smu_present) in dcn316_smu_set_dispclk()
172 clk_mgr, in dcn316_smu_set_dispclk()
179 int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn316_smu_set_hard_min_dcfclk() argument
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| D | dcn316_clk_mgr.c | 79 #define TO_CLK_MGR_DCN316(clk_mgr)\ argument
80 container_of(clk_mgr, struct clk_mgr_dcn316, base)
115 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disa… in dcn316_disable_otg_wa()
136 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) in dcn316_enable_pme_wa()
138 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn316_enable_pme_wa() local
140 dcn316_smu_enable_pme_wa(clk_mgr); in dcn316_enable_pme_wa()
143 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, in dcn316_update_clocks()
148 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn316_update_clocks() local
166 dcn316_smu_set_dtbclk(clk_mgr, false); in dcn316_update_clocks()
178 dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn316_update_clocks()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_smu.c | 86 static uint32_t dcn31_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us… in dcn31_smu_wait_for_response() argument
104 static int dcn31_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn31_smu_send_msg_with_param() argument
110 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); in dcn31_smu_send_msg_with_param()
128 result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000); in dcn31_smu_send_msg_with_param()
148 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn31_smu_get_smu_version() argument
151 clk_mgr, in dcn31_smu_get_smu_version()
157 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn31_smu_set_dispclk() argument
161 if (!clk_mgr->smu_present) in dcn31_smu_set_dispclk()
166 clk_mgr, in dcn31_smu_set_dispclk()
173 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn31_smu_set_dprefclk() argument
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| D | dcn31_clk_mgr.c | 54 clk_mgr->base.base.ctx->logger
71 #define TO_CLK_MGR_DCN31(clk_mgr)\ argument
72 container_of(clk_mgr, struct clk_mgr_dcn31, base)
107 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disab… in dcn31_disable_otg_wa()
127 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base, in dcn31_update_clocks()
132 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn31_update_clocks() local
150 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); in dcn31_update_clocks()
156 dcn31_smu_set_dtbclk(clk_mgr, false); in dcn31_update_clocks()
168 dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn31_update_clocks()
176 dcn31_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); in dcn31_update_clocks()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_smu.c | 101 static uint32_t dcn314_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn314_smu_wait_for_response() argument
119 static int dcn314_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn314_smu_send_msg_with_param() argument
125 result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000); in dcn314_smu_send_msg_with_param()
143 result = dcn314_smu_wait_for_response(clk_mgr, 10, 200000); in dcn314_smu_send_msg_with_param()
163 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn314_smu_get_smu_version() argument
166 clk_mgr, in dcn314_smu_get_smu_version()
172 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn314_smu_set_dispclk() argument
176 if (!clk_mgr->smu_present) in dcn314_smu_set_dispclk()
181 clk_mgr, in dcn314_smu_set_dispclk()
188 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn314_smu_set_dprefclk() argument
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| D | dcn314_clk_mgr.c | 58 clk_mgr->base.base.ctx->logger
93 #define TO_CLK_MGR_DCN314(clk_mgr)\ argument
94 container_of(clk_mgr, struct clk_mgr_dcn314, base)
129 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disa… in dcn314_disable_otg_wa()
158 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, in dcn314_update_clocks()
163 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_update_clocks() local
181 dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); in dcn314_update_clocks()
187 dcn314_smu_set_dtbclk(clk_mgr, false); in dcn314_update_clocks()
199 dcn314_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn314_update_clocks()
207 dcn314_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW); in dcn314_update_clocks()
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| D | dcn314_smu.h | 93 int dcn314_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
94 int dcn314_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
95 int dcn314_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
96 int dcn314_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
97 int dcn314_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
98 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
99 void dcn314_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
100 void dcn314_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
101 void dcn314_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
102 void dcn314_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_smu.c | 114 static uint32_t dcn315_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn315_smu_wait_for_response() argument
133 struct clk_mgr_internal *clk_mgr, in dcn315_smu_send_msg_with_param() argument
138 result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000); in dcn315_smu_send_msg_with_param()
158 result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000); in dcn315_smu_send_msg_with_param()
168 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn315_smu_get_smu_version() argument
171 clk_mgr, in dcn315_smu_get_smu_version()
177 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn315_smu_set_dispclk() argument
181 if (!clk_mgr->smu_present) in dcn315_smu_set_dispclk()
186 clk_mgr, in dcn315_smu_set_dispclk()
193 int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz) in dcn315_smu_set_hard_min_dcfclk() argument
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| D | dcn315_clk_mgr.c | 47 clk_mgr->base.base.ctx->logger
51 #define TO_CLK_MGR_DCN315(clk_mgr)\ argument
52 container_of(clk_mgr, struct clk_mgr_dcn315, base)
90 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disa… in dcn315_disable_otg_wa()
111 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, in dcn315_update_clocks()
116 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn315_update_clocks() local
143 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
152 dcn315_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in dcn315_update_clocks()
163 dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); in dcn315_update_clocks()
169 dcn315_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in dcn315_update_clocks()
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| D | dcn315_smu.h | 114 int dcn315_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
115 int dcn315_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
116 int dcn315_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
117 int dcn315_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcf…
118 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
119 void dcn315_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
120 void dcn315_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
121 void dcn315_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
122 void dcn315_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
123 void dcn315_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 44 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
47 (clk_mgr->regs->reg)
104 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, in dcn20_update_clocks_update_dpp_dto() argument
109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
127 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct dc_state *context) in dcn20_update_clocks_update_dentist() argument
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) in dcn20_update_clocks_update_dentist()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| D | dcn201_clk_mgr.c | 43 (clk_mgr->regs->reg)
58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
61 clk_mgr->base.ctx
63 clk_mgr->base.ctx->logger
77 static void dcn201_init_clocks(struct clk_mgr *clk_mgr) in dcn201_init_clocks() argument
79 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in dcn201_init_clocks()
80 clk_mgr->clks.p_state_change_support = true; in dcn201_init_clocks()
81 clk_mgr->clks.prev_p_state_change_support = true; in dcn201_init_clocks()
82 clk_mgr->clks.max_supported_dppclk_khz = 1200000; in dcn201_init_clocks()
83 clk_mgr->clks.max_supported_dispclk_khz = 1200000; in dcn201_init_clocks()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 251 void (*update_clocks)(struct clk_mgr *clk_mgr,
255 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr);
256 int (*get_dtb_ref_clk_frequency)(struct clk_mgr *clk_mgr);
258 void (*set_low_power_state)(struct clk_mgr *clk_mgr);
260 void (*init_clocks)(struct clk_mgr *clk_mgr);
263 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);
265 void (*enable_pme_wa) (struct clk_mgr *clk_mgr);
266 void (*get_clock)(struct clk_mgr *clk_mgr,
273 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr);
276 void (*notify_link_rate_change)(struct clk_mgr *clk_mgr, struct dc_link *link);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 37 static void rv1_init_clocks(struct clk_mgr *clk_mgr) in rv1_init_clocks() argument
39 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks)); in rv1_init_clocks()
42 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_c… in rv1_determine_dppclk_threshold() argument
45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold()
77 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
89 struct clk_mgr_internal *clk_mgr, in ramp_up_dispclk_with_dpp() argument
95 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks); in ramp_up_dispclk_with_dpp()
161 clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold); in ramp_up_dispclk_with_dpp()
162 clk_mgr->funcs->set_dprefclk(clk_mgr); in ramp_up_dispclk_with_dpp()
[all …]
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | dcn301_smu.c | 79 static uint32_t dcn301_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_u… in dcn301_smu_wait_for_response() argument
97 static int dcn301_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in dcn301_smu_send_msg_with_param() argument
103 result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); in dcn301_smu_send_msg_with_param()
121 result = dcn301_smu_wait_for_response(clk_mgr, 10, 200000); in dcn301_smu_send_msg_with_param()
129 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in dcn301_smu_get_smu_version() argument
131 int smu_version = dcn301_smu_send_msg_with_param(clk_mgr, in dcn301_smu_get_smu_version()
141 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in dcn301_smu_set_dispclk() argument
149 clk_mgr, in dcn301_smu_set_dispclk()
156 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in dcn301_smu_set_dprefclk() argument
160 DC_LOG_DEBUG("%s %d\n", __func__, clk_mgr->base.dprefclk_khz / 1000); in dcn301_smu_set_dprefclk()
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| D | vg_clk_mgr.c | 55 #define TO_CLK_MGR_VGH(clk_mgr)\ argument
56 container_of(clk_mgr, struct clk_mgr_vgh, base)
95 static void vg_update_clocks(struct clk_mgr *clk_mgr_base, in vg_update_clocks()
99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in vg_update_clocks() local
126 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
136 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data); in vg_update_clocks()
144 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz); in vg_update_clocks()
150 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz); in vg_update_clocks()
159 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()
160 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in vg_update_clocks()
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr_vbios_smu.c | 78 static uint32_t rn_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, u… in rn_smu_wait_for_response() argument
97 static int rn_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, in rn_vbios_smu_send_msg_with_param() argument
103 result = rn_smu_wait_for_response(clk_mgr, 10, 200000); in rn_vbios_smu_send_msg_with_param()
121 result = rn_smu_wait_for_response(clk_mgr, 10, 200000); in rn_vbios_smu_send_msg_with_param()
129 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr) in rn_vbios_smu_get_smu_version() argument
132 clk_mgr, in rn_vbios_smu_get_smu_version()
138 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rn_vbios_smu_set_dispclk() argument
141 struct dc *dc = clk_mgr->base.ctx->dc; in rn_vbios_smu_set_dispclk()
146 clk_mgr, in rn_vbios_smu_set_dispclk()
152 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) in rn_vbios_smu_set_dispclk()
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| D | rn_clk_mgr.c | 86 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) in rn_set_low_power_state()
89 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_set_low_power_state() local
99 rn_vbios_smu_set_dcn_low_power_state(clk_mgr, DCN_PWR_STATE_LOW_POWER); in rn_set_low_power_state()
106 static void rn_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, in rn_update_clocks_update_dpp_dto() argument
111 clk_mgr->dccg->ref_dppclk = ref_dpp_clk; in rn_update_clocks_update_dpp_dto()
113 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in rn_update_clocks_update_dpp_dto()
119 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst; in rn_update_clocks_update_dpp_dto()
122 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst]; in rn_update_clocks_update_dpp_dto()
125 clk_mgr->dccg->funcs->update_dpp_dto( in rn_update_clocks_update_dpp_dto()
126 clk_mgr->dccg, dpp_inst, dppclk_khz); in rn_update_clocks_update_dpp_dto()
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| D | rn_clk_mgr_vbios_smu.h | 29 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
30 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
31 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
32 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
33 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_d…
34 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
35 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
36 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
37 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
38 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
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| /linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 48 clk_mgr->ctx->logger
148 static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce_get_dp_ref_freq_khz() argument
150 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_get_dp_ref_freq_khz()
174 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce12_get_dp_ref_freq_khz() argument
176 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce12_get_dp_ref_freq_khz()
214 struct clk_mgr *clk_mgr, in dce_get_required_clocks_state() argument
217 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_get_required_clocks_state()
247 struct clk_mgr *clk_mgr, in dce_set_clock() argument
250 struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr); in dce_set_clock()
252 struct dc_bios *bp = clk_mgr->ctx->dc_bios; in dce_set_clock()
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