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Searched refs:_MMIO (Results 1 – 25 of 35) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/i915/gt/
Dintel_gt_regs.h12 #define RPM_CONFIG0 _MMIO(0xd00)
26 #define RPM_CONFIG1 _MMIO(0xd04)
30 #define RCP_CONFIG _MMIO(0xd08)
32 #define RC6_LOCATION _MMIO(0xd40)
34 #define RC6_CTX_BASE _MMIO(0xd48)
37 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4)
38 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4)
39 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84)
40 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88)
42 #define MCFG_MCR_SELECTOR _MMIO(0xfd0)
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Dintel_engine_regs.h11 #define RING_EXCC(base) _MMIO((base) + 0x28)
12 #define RING_TAIL(base) _MMIO((base) + 0x30)
14 #define RING_HEAD(base) _MMIO((base) + 0x34)
18 #define RING_START(base) _MMIO((base) + 0x38)
19 #define RING_CTL(base) _MMIO((base) + 0x3c)
32 #define RING_SYNC_0(base) _MMIO((base) + 0x40)
33 #define RING_SYNC_1(base) _MMIO((base) + 0x44)
34 #define RING_SYNC_2(base) _MMIO((base) + 0x48)
47 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50)
55 #define RING_MAX_IDLE(base) _MMIO((base) + 0x54)
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/linux-6.1.9/drivers/gpu/drm/i915/
Dintel_gvt_mmio_table.c54 #define RING_REG(base) _MMIO((base) + 0x28) in iterate_generic_mmio()
58 #define RING_REG(base) _MMIO((base) + 0x134) in iterate_generic_mmio()
62 #define RING_REG(base) _MMIO((base) + 0x6c) in iterate_generic_mmio()
65 MMIO_D(_MMIO(0x2148)); in iterate_generic_mmio()
67 MMIO_D(_MMIO(0x12198)); in iterate_generic_mmio()
76 #define RING_REG(base) _MMIO((base) + 0x29c) in iterate_generic_mmio()
88 MMIO_D(_MMIO(0x2124)); in iterate_generic_mmio()
89 MMIO_D(_MMIO(0x20dc)); in iterate_generic_mmio()
91 MMIO_D(_MMIO(0x2088)); in iterate_generic_mmio()
93 MMIO_D(_MMIO(0x2470)); in iterate_generic_mmio()
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Dintel_mchbar_regs.h25 #define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)
26 #define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)
32 #define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
36 #define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)
43 #define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)
47 #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)
48 #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
51 #define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
68 #define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
69 #define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)
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Di915_perf_oa_regs.h11 #define GEN7_OACONTROL _MMIO(0x2360)
28 #define GEN8_OACTXID _MMIO(0x2364)
30 #define GEN8_OA_DEBUG _MMIO(0x2B04)
36 #define GEN8_OACONTROL _MMIO(0x2B00)
45 #define GEN8_OACTXCONTROL _MMIO(0x2360)
51 #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */
57 #define GEN8_OABUFFER_UDW _MMIO(0x23b4)
58 #define GEN8_OABUFFER _MMIO(0x2b14)
61 #define GEN7_OASTATUS1 _MMIO(0x2364)
67 #define GEN7_OASTATUS2 _MMIO(0x2368)
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Di915_reg.h145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b))
146 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b))
147 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b))
148 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b))
149 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))
150 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b))
154 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
155 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
156 #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
157 #define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
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Di915_reg_defs.h105 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) macro
107 #define INVALID_MMIO_REG _MMIO(0)
Di915_pvinfo.h117 #define vgtif_reg(x) _MMIO(VGT_PVINFO_PAGE + vgtif_offset(x))
/linux-6.1.9/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_reg.h16 #define GUC_STATUS _MMIO(0xc000)
35 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
38 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
41 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
44 #define DMA_ADDR_0_LOW _MMIO(0xc300)
45 #define DMA_ADDR_0_HIGH _MMIO(0xc304)
46 #define DMA_ADDR_1_LOW _MMIO(0xc308)
47 #define DMA_ADDR_1_HIGH _MMIO(0xc30c)
50 #define DMA_COPY_SIZE _MMIO(0xc310)
51 #define DMA_CTRL _MMIO(0xc314)
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/linux-6.1.9/drivers/gpu/drm/i915/gvt/
Dreg.h71 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
72 (_MMIO(0x50090))) : \
73 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
74 (_MMIO(0x50098))) : \
75 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
76 (_MMIO(0x5009C))) : \
77 (_MMIO(0x50080))))); })
117 #define PCH_GPIO_BASE _MMIO(0xc5010)
119 #define PCH_GMBUS0 _MMIO(0xc5100)
120 #define PCH_GMBUS1 _MMIO(0xc5104)
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Dhandlers.c51 #define PCH_PP_STATUS _MMIO(0xc7200)
52 #define PCH_PP_CONTROL _MMIO(0xc7204)
53 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
54 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
55 #define PCH_PP_DIVISOR _MMIO(0xc7210)
712 _MMIO(0xd80),
719 _MMIO(0x2690),
720 _MMIO(0x2694),
721 _MMIO(0x2698),
722 _MMIO(0x2754),
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Dmmio_context.c124 {RCS0, _MMIO(0x4dfc), 0, true},
143 {RCS0, _MMIO(0x20D8), 0xffff, true}, /* 0x20d8 */
371 reg = _MMIO(regs[engine->id]); in handle_tlb_pending_event()
Ddebugfs.c65 preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset)); in mmio_diff_handler()
/linux-6.1.9/drivers/gpu/drm/i915/display/
Dintel_combo_phy_regs.h27 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy))
31 #define ICL_PORT_CL_DW10(phy) _MMIO(_ICL_PORT_CL_DW(10, phy))
48 #define ICL_PORT_CL_DW12(phy) _MMIO(_ICL_PORT_CL_DW(12, phy))
56 #define ICL_PORT_COMP_DW0(phy) _MMIO(_ICL_PORT_COMP_DW(0, phy))
59 #define ICL_PORT_COMP_DW1(phy) _MMIO(_ICL_PORT_COMP_DW(1, phy))
61 #define ICL_PORT_COMP_DW3(phy) _MMIO(_ICL_PORT_COMP_DW(3, phy))
73 #define ICL_PORT_COMP_DW8(phy) _MMIO(_ICL_PORT_COMP_DW(8, phy))
76 #define ICL_PORT_COMP_DW9(phy) _MMIO(_ICL_PORT_COMP_DW(9, phy))
78 #define ICL_PORT_COMP_DW10(phy) _MMIO(_ICL_PORT_COMP_DW(10, phy))
90 #define ICL_PORT_PCS_DW1_AUX(phy) _MMIO(_ICL_PORT_PCS_DW_AUX(1, phy))
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Dintel_dmc_regs.h11 #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4)
36 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler))
41 _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler))
57 #define DMC_SSP_BASE _MMIO(0x8F074)
58 #define DMC_HTP_SKL _MMIO(0x8F004)
59 #define DMC_LAST_WRITE _MMIO(0x8F034)
79 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)
80 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)
81 #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)
82 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
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Dintel_audio_regs.h11 #define G4X_AUD_VID_DID _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x62020)
16 #define G4X_AUD_CNTL_ST _MMIO(0x620B4)
21 #define G4X_HDMIW_HDMIEDID _MMIO(0x6210C)
34 #define IBX_AUD_CNTL_ST2 _MMIO(0xE20C0)
44 #define CPT_AUD_CNTRL_ST2 _MMIO(0xE50C0)
52 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
121 #define HSW_AUD_PIPE_CONV_CFG _MMIO(0x6507c)
122 #define HSW_AUD_PIN_ELD_CP_VLD _MMIO(0x650c0)
133 #define HSW_AUD_CHICKENBIT _MMIO(0x65f10)
136 #define AUD_FREQ_CNTRL _MMIO(0x65900)
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Dintel_backlight_regs.h27 #define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+ only */
50 #define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
72 #define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
77 #define BLC_PWM_CPU_CTL2 _MMIO(0x48250)
78 #define BLC_PWM_CPU_CTL _MMIO(0x48254)
80 #define HSW_BLC_PWM2_CTL _MMIO(0x48350)
84 #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250)
88 #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254)
109 #define UTIL_PIN_CTL _MMIO(0x48400)
Dintel_gmbus_regs.h13 #define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
30 #define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
40 #define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
57 #define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
67 #define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
70 #define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
78 #define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
Dintel_hdcp_regs.h12 #define HDCP_KEY_CONF _MMIO(0x66c00)
16 #define HDCP_KEY_STATUS _MMIO(0x66c04)
22 #define HDCP_AKSV_LO _MMIO(0x66c10)
23 #define HDCP_AKSV_HI _MMIO(0x66c14)
26 #define HDCP_REP_CTL _MMIO(0x66d00)
57 #define HDCP_SHA_V_PRIME_H0 _MMIO(0x66d04)
58 #define HDCP_SHA_V_PRIME_H1 _MMIO(0x66d08)
59 #define HDCP_SHA_V_PRIME_H2 _MMIO(0x66d0C)
60 #define HDCP_SHA_V_PRIME_H3 _MMIO(0x66d10)
61 #define HDCP_SHA_V_PRIME_H4 _MMIO(0x66d14)
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Dvlv_dsi_pll_regs.h11 #define MIPIO_TXESC_CLK_DIV1 _MMIO(0x160004)
13 #define MIPIO_TXESC_CLK_DIV2 _MMIO(0x160008)
18 #define BXT_MIPI_CLOCK_CTL _MMIO(0x46090)
81 #define BXT_DSI_PLL_CTL _MMIO(0x161000)
105 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080)
Dintel_snps_phy_regs.h18 #define _MMIO_SNPS(phy, reg) _MMIO(_SNPS2(phy, reg))
19 #define _MMIO_SNPS_LN(ln, phy, reg) _MMIO(_SNPS2(phy, \
Dvlv_dsi_regs.h17 #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
35 #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
38 #define BXT_P_DSI_REGULATOR_TX_CTRL _MMIO(0x160054)
475 #define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA…
Dintel_tc_phy_regs.h12 _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1)))
146 #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off))
/linux-6.1.9/drivers/gpu/drm/i915/pxp/
Dintel_pxp_session.c16 #define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
19 #define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
Dintel_pxp.c58 #define KCR_INIT _MMIO(0x320f0)

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