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Searched refs:WREG32_PCIE (Results 1 – 24 of 24) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dnbio_v6_1.c189 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
209 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
272 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v6_1_init_registers()
278 WREG32_PCIE(smnPCIE_CI_CNTL, data); in nbio_v6_1_init_registers()
290 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); in nbio_v6_1_program_ltr()
295 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v6_1_program_ltr()
300 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); in nbio_v6_1_program_ltr()
305 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); in nbio_v6_1_program_ltr()
319 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v6_1_program_aspm()
324 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v6_1_program_aspm()
[all …]
Dnbio_v7_4.c272 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_4_update_medium_grain_light_sleep()
619 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO_ALDE, global_sts); in nbio_v7_4_query_ras_error_count()
621 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts); in nbio_v7_4_query_ras_error_count()
627 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2_ALDE, parity_sts); in nbio_v7_4_query_ras_error_count()
629 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2, parity_sts); in nbio_v7_4_query_ras_error_count()
635 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts); in nbio_v7_4_query_ras_error_count()
639 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi); in nbio_v7_4_query_ras_error_count()
681 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); in nbio_v7_4_program_ltr()
686 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v7_4_program_ltr()
691 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); in nbio_v7_4_program_ltr()
[all …]
Dnbio_v2_3.c254 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v2_3_update_medium_grain_clock_gating()
277 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v2_3_update_medium_grain_light_sleep()
340 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v2_3_init_registers()
380 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_enable_aspm()
388 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB); in nbio_v2_3_program_ltr()
398 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data); in nbio_v2_3_program_ltr()
403 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); in nbio_v2_3_program_ltr()
417 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_program_aspm()
422 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v2_3_program_aspm()
427 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v2_3_program_aspm()
[all …]
Dumc_v6_1.c56 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_enable_umc_index_mode()
71 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_disable_umc_index_mode()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
128 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
137 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
141 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
200 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
418 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel()
420 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_err_cnt_init_per_channel()
[all …]
Dumc_v8_7.c197 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
201 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
214 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
255 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
265 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
408 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
410 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
415 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
416 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
Dcik.c1605 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); in cik_pcie_gen3_enable()
1631 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1635 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1682 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1691 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1706 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); in cik_pcie_gen3_enable()
1737 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1742 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1747 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1760 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
[all …]
Dvi.c1138 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_enable_aspm()
1170 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_program_aspm()
1177 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in vi_program_aspm()
1182 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in vi_program_aspm()
1187 WREG32_PCIE(ixPCIE_P_CNTL, data); in vi_program_aspm()
1207 WREG32_PCIE(ixPCIE_LC_CNTL6, data); in vi_program_aspm()
1212 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); in vi_program_aspm()
1255 WREG32_PCIE(ixCPM_CONTROL, data); in vi_program_aspm()
1261 WREG32_PCIE(ixPCIE_CONFIG_CNTL, data); in vi_program_aspm()
1271 WREG32_PCIE(ixPCIE_LC_CNTL7, data); in vi_program_aspm()
[all …]
Dumc_v6_7.c297 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
307 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
393 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
397 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
406 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
410 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
Dumc_v8_10.c78 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_10_clear_error_count_per_channel()
311 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_10_err_cnt_init_per_channel()
313 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT); in umc_v8_10_err_cnt_init_per_channel()
Dnbio_v7_0.c162 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
204 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
Dsoc15.c763 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); in soc15_get_pcie_usage()
769 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in soc15_get_pcie_usage()
778 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in soc15_get_pcie_usage()
812 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); in vega20_get_pcie_usage()
818 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in vega20_get_pcie_usage()
827 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in vega20_get_pcie_usage()
Dsi.c1599 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in si_get_pcie_usage()
1605 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in si_get_pcie_usage()
1614 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in si_get_pcie_usage()
2475 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
2638 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
Damdgpu_xgmi.c778 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); in pcs_clear_status()
779 WREG32_PCIE(pcs_status_reg, 0); in pcs_clear_status()
Damdgpu_cgs.c92 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
Damdgpu.h1153 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
Dgmc_v7_0.c882 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
Damdgpu_debugfs.c444 WREG32_PCIE(*pos, value); in amdgpu_debugfs_regs_pcie_write()
/linux-6.1.9/drivers/gpu/drm/radeon/
Dr300.c95 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); in rv370_pcie_gart_tlb_flush()
97 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
166 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
167 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
170 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
173 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); in rv370_pcie_gart_enable()
175 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
176 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); in rv370_pcie_gart_enable()
[all …]
Dsi.c5577 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls()
7292 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
7455 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
Drv6xx_dpm.c135 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
Drv770_dpm.c128 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
Dradeon.h2555 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) macro
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dsmu_v11_0.c185 WREG32_PCIE(addr_start, src[i]); in smu_v11_0_load_microcode()
189 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()
191 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()
/linux-6.1.9/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0.c170 WREG32_PCIE(addr_start, src[i]); in smu_v13_0_load_microcode()
174 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v13_0_load_microcode()
176 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v13_0_load_microcode()