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Searched refs:UVD_MPC_SET_MUX__SET_0__SHIFT (Results 1 – 17 of 17) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h634 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Duvd_3_1_sh_mask.h510 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
Duvd_4_0_sh_mask.h529 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x00000000 macro
Duvd_4_2_sh_mask.h514 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
Duvd_5_0_sh_mask.h546 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
Duvd_6_0_sh_mask.h548 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 macro
/linux-6.1.9/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1141 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_2_5_sh_mask.h2882 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2647 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2874 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3955 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4205 #define UVD_MPC_SET_MUX__SET_0__SHIFT … macro
/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0.c927 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v4_0_start_dpg_mode()
1066 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v4_0_start()
Dvcn_v1_0.c840 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v1_0_start_spg_mode()
1023 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v1_0_start_dpg_mode()
Dvcn_v2_0.c855 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_0_start_dpg_mode()
990 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_0_start()
Dvcn_v2_5.c837 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_5_start_dpg_mode()
991 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v2_5_start()
Dvcn_v3_0.c1003 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v3_0_start_dpg_mode()
1169 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | in vcn_v3_0_start()